JP2783233B2 - LSI package - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI package in which an LSI chip is mounted on a pinglit array or a ball grid array. The present invention relates to an LSI package capable of achieving the above.

[0002]

2. Description of the Related Art Conventionally, an LSI chip such as a large-scale integrated circuit has been mounted on a pin grid array or a ball grid array as a suitable means for increasing the density of connection terminals in an LSI package. .

A pin grid array (or ball grid array) used in a conventional LSI package is:
A device hole for accommodating an LSI chip is formed at the center of an insulating substrate made of a glass cloth base epoxy resin, and the LS is formed around the device hole.
A plurality of electrode pads corresponding to the electrode terminals of the I chip are formed, and a plurality of through holes corresponding to the electrode pads are formed on the entire surface of the insulating substrate excluding the device holes. (Or ball) terminals are inserted, and the electrode pads and the through holes are connected by a lead pattern formed on the surface of the insulating substrate.

[0004] Each electrode terminal of the LSI chip and each electrode pad of the pin grid array are connected by bonding wires to form an LSI package.

According to the LSI package using such a pin grid array, it is possible to increase the density of connection terminals, and to connect to an external mounting substrate via the pin terminals of the pin grid array or the like. It was easy to implement.

As an LSI package having a configuration in which each electrode terminal of the LSI chip and each electrode pad of the pin grid array are connected by bonding wires, for example, there is an LSI package proposed in Japanese Patent Application Laid-Open No. 4-123445. .

On the other hand, as a conventional LSI package which does not use a pin grid array or the like, a tape carrier (T.sub.T) in which electrode pads and lead patterns are formed on an organic insulating film.
AB: Tape Automated Bonding) has an LSI chip mounted.

LSI using such a tape carrier
In the package, since the electrode pads and the lead patterns can be formed on the organic insulating film in a stable state, the electrode pads and the lead patterns can be miniaturized, and the package can be made thinner. I was able to plan.

[0009]

However, in the above-described LSI package using the conventional pin grid array or ball grid array, electrode pads and lead patterns are formed directly on a glass cloth base epoxy resin as an insulating substrate. There was a configuration. This glass cloth base epoxy resin has a limit in miniaturizing the pitch of the lead pattern and the electrode pad due to the material and the method of manufacturing the pattern. Therefore, in a conventional LSI package using a pin grid array or the like, there is a problem that it is not possible to achieve ultra-high density of connection terminals having a pitch of 500 μm or less.

In addition, since each electrode terminal of the LSI chip is connected to each electrode pad of the pin grid array by a bonding wire, bonding becomes more difficult as connection terminals are increased in density. There is also a problem that the pitch can be reduced to only about 100 μm at most.

Here, if the insulating substrate is formed of ceramic instead of the glass cloth base epoxy resin,
Although the pitch of the lead pattern and the like can be reduced, there is a problem that the use of a ceramic substrate makes the pin grid array and the like expensive.

On the other hand, L using the above-described tape carrier
The SI package has poor flatness because the tape carrier is soft, and has a certain degree of regularity due to the lead pattern and the like formed on the tape carrier. It was extremely difficult to flatten the carrier. For this reason, there is a problem that it is difficult to connect the tape carrier to the mounting substrate, and this problem becomes more remarkable as the density of the connection terminals increases.

Further, since the tape carrier is directly mounted on the mounting board on which various electronic components are mounted on both sides, it is possible to effectively use a support ring for flattening the tape carrier. I couldn't do it either.

Here, recently, a tape ball grid array using an organic insulating film has been put to practical use. However, when this tape ball grid array is used for an LSI package, the same problem as that of the tape carrier occurs. .

In Japanese Patent Application Laid-Open No. 4-96240, FIG.
As shown in FIG. 3, each electrode terminal of the LSI chip 101 and each electrode pad of the pin grid array 110 are connected to the TAB 12.
An LSI package having a configuration connected by 0 has been proposed. According to such a configuration, the LSI chip 101
Since no bonding wire is used for connection between each of the electrode terminals and each of the electrode pads of the pin grid array 110, the density of the connection terminals can be increased.

However, since the lead pattern 111a and the electrode pad 111b are formed directly on the insulating substrate 111 of the pin grid array 110, eventually,
There is a problem in that there is a limit to miniaturization of the pitch, and it is not possible to increase the density of the connection terminals.

In Japanese Patent Application Laid-Open No. 4-96257, FIG.
As shown in FIG. 1, an LSI package having a configuration in which an electrode terminal is formed at the center of an LSI chip 201 and a lead pattern 211a on an insulating substrate 211 of a pin grid array 210 is extended to the center of the LSI chip 201 has been proposed. . Then, the lead pattern 21 on the insulating substrate 211
As a means for extending 1a to the center of the LSI chip 201, a film 212 covering the LSI chip 201 is bonded on an insulating substrate 211, and a lead pattern 211a is formed on the film 212.

According to such a configuration, the LSI chip 2
01, the number of connection terminals can be increased.
Since the lead pattern 211a can be formed on the film 212 on the top one, the pitch of the lead pattern 211a and the like can be reduced.

However, in such an LSI package, a through hole 213 that penetrates the film 212 is formed after bonding the film 212 on the insulating substrate.
The diameter of the through-hole 213a formed in the film 212 was always the same as the diameter of the pin terminal 214 inserted into the through-hole 213b of the insulating substrate 211.

As described above, the pin terminals 2 are attached to the film 212.
Since only the through-hole 213 having the same diameter as 14 could be formed, if the number of the pin terminals 214 was increased in order to increase the density of the connection terminals, the proportion of the space on the film 212 occupied by the through-holes 213a increased. As a result, a space for forming the lead pattern 211a and the electrode pattern cannot be secured, and as a result, there is a problem that it is not possible to achieve ultra-high density of connection terminals.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and can achieve ultra-high density of connection terminals of an LSI chip and a pinglit array or a ball grid array, and can be applied to an external mounting board. It is an object of the present invention to provide an LSI package capable of easily performing connection.

[0022]

In order to achieve the above object, an LSI package according to claim 1 is provided with a pinglit.
A plurality of through holes corresponding to each pin terminal of the array,
Around the opening on the side where each through hole connects the LSI chip
The first electrode pad formed on the edge and the above of each through hole
Formed on the periphery of the opening to connect the pin grid array
The second electrode pad and the first electrode pad on the same surface.
Formed between the first electrode pad and the LSI chip.
And a lead pattern for connecting the pole terminals.
Insert the LSI chip through the rear
An LSI package mounted on an insulating substrate of
By reducing the diameter of the first electrode pad,
The through hole and the lead of the tape carrier
The configuration is such that the pattern formation area is widened .

According to such a configuration, the first electrode
By reducing the diameter of the tape carrier,
The number of the first electrode pads formed on the rear is increased.
First, it is necessary to secure a large area for forming the lead pattern.
Can be connected via the tape carrier
Electrode terminals of the LSI chip and the pin grid array
And the pin terminals can be made ultra-high density.

The LSI package according to claim 2, Bo
Multiple throughs corresponding to each pin terminal of the rugrid array
The side that connects the LSI chip to each hole
The first electrode pad formed around the opening
Around the opening on the side connecting the pin grid array
A second electrode pad formed on the edge, the first electrode pad and
The first electrode pad and the LSI formed on the same surface;
A lead pattern for connecting the electrode terminals of the chip,
The LSI chip is connected to the ball via a tape carrier.
LSI package mounted on grid array insulating substrate
The diameter of the first electrode pad is reduced.
And the through hole of the tape carrier and
And the area for forming the lead pattern is widened .

According to such a structure, the first electrode
By reducing the diameter of the tape carrier,
The number of the first electrode pads formed on the rear is increased.
First, it is necessary to secure a large area for forming the lead pattern.
Can be connected via the tape carrier
An electrode terminal of the LSI chip and the ball grid electrode;
The ball terminals of the ray can be made ultra-high density.

The LSI package according to claim 3, wherein the pin
Multiple through holes corresponding to each pin terminal of the grid array
To the LSI chip of each through hole
The first electrode pad formed on the periphery of the opening and each through hole
Of the opening on the side connecting the pin grid array
A second electrode pad formed at the same time as the first electrode pad.
The first electrode pad and the LSI chip are formed on one surface.
And a lead pattern for connecting the electrode terminals of the chip.
The LSI chip via the loop carrier
LSI package mounted on an insulating substrate of a chip array
And the through hoe formed on the tape carrier.
Only the opening diameter on the first electrode pad side of the
Thereby, the diameter of the first electrode pad is reduced .

The LSI package according to claim 4, Bo
Multiple throughs corresponding to each pin terminal of the rugrid array
The side that connects the LSI chip to each hole
The first electrode pad formed around the opening
Around the opening on the side connecting the pin grid array
A second electrode pad formed on the edge, the first electrode pad and
The first electrode pad and the LSI formed on the same surface;
A lead pattern for connecting the electrode terminals of the chip,
The LSI chip is connected to the ball via a tape carrier.
LSI package mounted on grid array insulating substrate
The through formed in the tape carrier
Only the opening diameter of the hole on the first electrode pad side is reduced.
By doing so, the diameter of the first electrode pad is reduced.
That it is constituted.

According to the third and fourth aspects of the present invention, the diameter of the through hole formed in the tape carrier on the side of the second electrode pad can be increased. The amount of solder entering the hole is increased, and a good connection can be made.

According to a fifth aspect of the present invention, the power supply layer and the GND layer are formed inside the multilayered insulating substrate, and a chip capacitor connected to the power supply layer and the GND layer is provided.

According to this structure, the LSI package which attained high density of connection terminals even when at high speed operation, GND noise generated by variations in power supply voltage when many signal lines and operated simultaneously Can be suppressed by the chip capacitor.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an LSI package according to the present invention will be described below with reference to the drawings.

Firstly, LS according to the first embodiment of the present invention
The I package will be described. FIG. 1 is a perspective view showing an LSI package according to the first embodiment of the present invention, and FIG. 2 is a partial side sectional view of the LSI package.

The LSI package of the present embodiment has a configuration in which an LSI chip and a pin grid array are connected via a tape carrier on which a lead pattern and a through hole are formed. The configuration is such that the area of the electrode pad (first electrode pad) formed on the periphery of the opening on the side to which the LSI chip is connected is reduced.

In FIGS. 1 and 2, reference numeral 1 denotes an LSI chip having an outer dimension of 17.5 mm × 17.5 mm. Around the periphery of the LSI chip 1, about 80
Zero electrode terminals (not shown) are formed at a pitch of about 80 μm.

Reference numeral 10 denotes a tape carrier having a thickness of 50 μm.
m of a polyimide film. Tape carrier 10
It is necessary that the organic insulating film used for (1) has heat resistance, good dimensional stability, and high adhesion strength to the printed wiring formed on the surface.

In the center of the tape carrier 10, LS
A device hole 10a for mounting the I chip 1 is formed. As shown in FIG. 2, about 800 electrode pads 11 corresponding to each electrode terminal of the LSI chip 1 are formed on the periphery of the device hole 10a.

In FIG. 1, the entirety of the tape carrier 10 except for the device holes 10a has about 800 holes corresponding to the through holes 22 of the pinglit array 20 described later.
The individual through holes 12 are formed in a square lattice shape. In FIG. 1, through holes, wiring patterns, and the like formed on the entire surface of the tape carrier are partially omitted.

In FIG. 2, the surface side of the tape carrier 10 of each through hole 12 (the side to which the LSI chip 1 is connected)
A first electrode pad 12a is formed on the periphery of the opening, and a second electrode pad 12a is formed on the periphery of the opening of the through hole 12 on the back side of the tape carrier 10 (the side connecting the pin grid array 20). A pad 12b is formed.

Further, on the tape carrier 10 surface side,
A lead pattern 13 that connects each electrode pad 11 and each first electrode pad 12a is formed.

FIG. 3 is a partially enlarged view showing a through hole of a tape carrier and a through hole of a pinlit array in the present LSI package.

In this embodiment, as shown in FIG. 3, the diameter of the through hole 12 of the tape carrier 10 is smaller than the diameter of the through hole 22 of the pinglit array 20. Also, the first electrode pad 12 of the through hole 12
The diameter L1 of a is smaller than the diameter L2 of the second electrode pad 12b (the electrode pad of the through hole 22).

Thus, while increasing the number of through holes 12 formed in the tape carrier 10, a large area for forming the first and second electrode pads 12a and 12b and the lead pattern 13 can be secured.

The electrode pad 1 of the tape carrier 10
1, through hole 12, first and second electrode pads 12
The whole except a, 12b and the lead pattern 13 is coated with a solder resist in order to prevent short circuit due to solder.

Each electrode terminal of the LSI chip 1 and each electrode pad 11 of the tape carrier 10 are connected to each other via a TAB tape 30.
The AB tape 30 is sealed with a sealing resin 31 such as silicon. Thus, the LSI chip 1 and the tape carrier 10 form a tape carrier package.

The pinglit array 20 is formed by forming approximately 800 through holes 22 corresponding to the through holes 12 of the tape carrier 10 on an insulating substrate 21 made of a glass cloth base epoxy resin at a pitch of 1.27 mm in a square lattice. And each of the through holes 22 has a diameter of 0.
The configuration is such that a 46 mm pin terminal 23 is inserted.

On the front side of the insulating substrate 21, only the electrode pads 22a connected to the through holes 22 are formed. Since such a pinglit array 20 has a configuration in which only the electrode pads 22a are formed on the surface of the insulating substrate 21 and no lead pattern or the like is formed, the through hole can be formed without considering the space for forming the lead pattern or the like. 22 (pin terminals 23) are provided at a very high density.

Further, as shown in FIG. 2, high melting point solder bumps 24 are formed on the electrode pads 22a of the through holes 22. Note that the solder bumps 24 in FIG. 2 show a state after reflow soldering.

The above-described tape carrier package including the LSI chip 1 and the tape carrier 10 is mounted on the insulating substrate 21 of the pinglit array 20, and the through holes 12 of the tape carrier 10 and the solder bumps 24 on the insulating substrate 21 are provided. After reflow soldering at a high temperature of 200 ° C. or more, the LSI shown in FIG.
A package is formed.

When the flatness of the tape carrier 10 is poor, after positioning the through holes 12 of the tape carrier 10 and the solder bumps 24 on the insulating substrate 21, the tape carrier 10 and the insulating substrate 21 are supported by two supports. The tape carrier 10 is sandwiched from above and below by a ring, and the tape carrier 10 is flattened by the pressing force of these support rings.

Here, a hole corresponding to the LSI chip 1 is formed in the support ring pressing the tape carrier 10 side, and the support ring pressing the insulating substrate 21 side corresponds to each pin terminal 23. It is preferable to make holes.

By using the two support rings having such a configuration, the tape carrier 10 can be effectively pressed and the pin terminals 23 can be prevented from being damaged.

According to the above-described LSI package of the present embodiment, since the lead patterns 13 and the like are formed on the tape carrier 10, the pitch of the lead patterns 13 and the like can be reduced, and the connection terminals Higher density can be achieved.

Further, since the LSI chip 1 is mounted on the insulating substrate 21 of the pinglit array 20, the LSI package can be easily connected to an external mounting substrate even when the density of connection terminals is increased. be able to.

Further, by reducing the diameter of the first electrode pad 12a, it is possible to increase the number of through holes 12 while securing a large area for forming the lead pattern 13 in the tape carrier 10. 10 and the electrode terminals of the LSI chip 1 connected via the
3 can be made ultra-high density.

In the LSI package of this embodiment, as shown in FIG. 3, the diameter L1 of the first electrode pad 12a is reduced by uniformly reducing the diameter of the through hole 12 of the tape carrier 10. However, the diameter L1 of the first electrode pad 12a can be reduced even if only the opening diameter of the through hole 12 on the first electrode pad 12a side is reduced as shown in FIG.

In the case of such a configuration, the opening diameter of the through hole 12 on the second electrode pad 12b side can be increased, so that the amount of the solder bump 24 entering the through hole 12 increases, resulting in a good connection. Can be performed.

Next, the LS according to the second embodiment of the present invention will be described.
The I package will be described with reference to FIG. FIG. 5 is a partial side sectional view showing an LSI package according to the second embodiment of the present invention.

Referring to FIG. 5, the LSI package of the present embodiment has a power supply layer 21a and a GND layer 21b formed inside a multi-layered insulating substrate 21 of a pinglit array 20, and the power supply layer 21a and the GND layer 21b are The configuration is such that a chip capacitor 25 to be connected is provided.

The LS of this embodiment having such a configuration
According to the I package, even when the present LSI package with a high connection terminal density is operated at a high speed, the GND noise generated by the fluctuation of the power supply voltage when many signal lines are operated at the same time is reduced by the chip capacitor 25. Can be suppressed.

Note that the first and second embodiments described above
In each case, the LSI package of the present invention is applied to the pin grid array 20. However, the present invention is not limited to this, and the same effect as in each embodiment can be obtained by applying the LSI package of the present invention to a ball grid array. be able to.

[0061]

As described above, according to the LSI package of the present invention, the connection density of the connection terminals of the LSI chip and the pinlit array or the ball grid array can be increased, and the LSI package can be connected to an external device. It can be easily connected to the mounting board.

[Brief description of the drawings]

FIG. 1 is a perspective view showing an LSI package according to a first embodiment of the present invention.

FIG. 2 is a partial side sectional view of the LSI package.

FIG. 3 is a partially enlarged view showing through holes of a tape carrier and through holes of a pinglit array in the LSI package.

FIG. 4 is a partially enlarged view showing a modification of the LSI package.

FIG. 5 is a partial side sectional view of an LSI package according to a second embodiment of the present invention.

FIG. 6 is a side sectional view showing a conventional LSI package.

FIG. 7 is a side sectional view showing another conventional LSI package.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 LSI chip 10 Tape carrier 10a Device hole 12, 22 Through hole 12a First electrode pad 12b Second electrode pad 20 Pin grid array 21 Insulating substrate 23 Pin terminal

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/60 311 H01L 23/12

Claims (5)

(57) [Claims] 1. Corresponds to each pin terminal of a pinglit array
Multiple through holes and the LSI chip of each through hole
The first electrode pad formed around the opening on the side where the
And the pin grid array of each through hole
A second electrode pad formed on the periphery of the opening on the side of
The first electrode pad is formed on the same surface as the first electrode pad.
Lead and a lead pad for connecting an electrode terminal of the LSI chip
The LSI chip via a tape carrier.
Was mounted on the insulating substrate of the Pinglit array
An LSI package, wherein the diameter of the first electrode pad is reduced,
The through hole and the lead of the tape carrier
LS characterized by widening the pattern formation area
I package. 2. The method according to claim 1 , wherein each pin terminal of the ball grid array is
Corresponding multiple through holes and LSI of each through hole
The first electrode pad formed on the periphery of the opening on the side where the chip is connected
And the pin grid array of each through hole.
A second electrode pad formed on the periphery of the opening on the connecting side;
Forming the first electrode on the same surface as the first electrode pad;
Leads for connecting pads and electrode terminals of the LSI chip
And the LSI via a tape carrier.
Chip mounted on the insulating substrate of the ball grid array
LSI package, wherein the diameter of the first electrode pad is reduced,
The through hole and the lead of the tape carrier
LS characterized by widening the pattern formation area
I package. 3. Corresponding to each pin terminal of a pinglit array
Multiple through holes and the LSI chip of each through hole
The first electrode pad formed around the opening on the side where the
And the pin grid array of each through hole
A second electrode pad formed on the periphery of the opening on the side of
The first electrode pad is formed on the same surface as the first electrode pad.
Lead and a lead pad for connecting an electrode terminal of the LSI chip
The LSI chip via a tape carrier.
Was mounted on the insulating substrate of the Pinglit array
An LSI package, wherein said through hole is formed in said tape carrier;
By reducing only the opening diameter on the first electrode pad side
And reducing the diameter of the first electrode pad.
LSI package. 4. Each pin terminal of the ball grid array is connected to
Corresponding multiple through holes and LSI of each through hole
The first electrode pad formed on the periphery of the opening on the side where the chip is connected
And the pin grid array of each through hole.
A second electrode pad formed on the periphery of the opening on the connecting side;
Forming the first electrode on the same surface as the first electrode pad;
Leads for connecting pads and electrode terminals of the LSI chip
And the LSI via a tape carrier.
Chip mounted on the insulating substrate of the ball grid array
An LSI package, wherein said through hole formed in said tape carrier is located in front of said through hole.
By reducing only the opening diameter on the first electrode pad side
And reducing the diameter of the first electrode pad.
LSI package. 5. A power supply layer and a GND layer are formed inside by making the insulating substrate a multilayer, and the power supply layer and the GND layer are formed.
A chip capacitor connected to a layer is provided.
An LSI package according to 2, 3, or 4.