JP2845218B2 - Electronic component mounting structure and method of manufacturing the same - Google Patents

Electronic component mounting structure and method of manufacturing the same

Info

Publication number
JP2845218B2
JP2845218B2 JP8261786A JP26178696A JP2845218B2 JP 2845218 B2 JP2845218 B2 JP 2845218B2 JP 8261786 A JP8261786 A JP 8261786A JP 26178696 A JP26178696 A JP 26178696A JP 2845218 B2 JP2845218 B2 JP 2845218B2
Authority
JP
Japan
Prior art keywords
electronic component
substrate
terminal
mounting structure
lsi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP8261786A
Other languages
Japanese (ja)
Other versions
JPH10107091A (en
Inventor
史男 森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=17366695&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=JP2845218(B2) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP8261786A priority Critical patent/JP2845218B2/en
Publication of JPH10107091A publication Critical patent/JPH10107091A/en
Application granted granted Critical
Publication of JP2845218B2 publication Critical patent/JP2845218B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92147—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、電子部品の実装構
造およびその製造方法に関し、特に、フィルムキャリア
基板等の基板を用いて実装される電子部品の実装構造お
よびその製造方法に関する。The present invention relates to a mounting structure of an electronic component and a method of manufacturing the same, and more particularly, to a mounting structure of an electronic component mounted using a substrate such as a film carrier substrate and a method of manufacturing the same.

【０００２】[0002]

【従来の技術】従来のこの種のフィルムキャリアを用い
て実装される電子部品の実装構造の一例が、特開昭６３
−３４９３６号公報に開示されている。2. Description of the Related Art An example of a conventional mounting structure of electronic parts mounted using a film carrier of this kind is disclosed in
No. 34936.

【０００３】この従来技術では、キャリアテープに複数
の接続リードが放射状に設けられ、該複数の接続リード
の各々の一端が電子部品の複数の外部接続端子に接続さ
れ、他端が該キャリアテープに形成されたスルーホール
を介して基板接続用の接続端子に電気的に接続される
（以下、「従来技術１」という）。In this prior art, a plurality of connection leads are radially provided on a carrier tape, one end of each of the plurality of connection leads is connected to a plurality of external connection terminals of an electronic component, and the other end is connected to the carrier tape. It is electrically connected to a connection terminal for connecting a substrate through the formed through hole (hereinafter, referred to as “prior art 1”).

【０００４】また、ワイヤボンディングにより電子部品
と基板とを電気的に接続させる従来の技術では、電子部
品は基板と密着しており、電子部品における基板と対向
しない面に設けられた外部接続端子と基板における電子
部品と対向する主面に設けられた端子とがワイヤボンデ
ィング接続される（以下、「従来技術２」という）。In a conventional technique for electrically connecting an electronic component and a substrate by wire bonding, the electronic component is in close contact with the substrate, and an external connection terminal provided on a surface of the electronic component that does not face the substrate is connected to an external connection terminal. A terminal provided on the main surface of the substrate facing the electronic component is connected by wire bonding (hereinafter, referred to as “prior art 2”).

【０００５】[0005]

【発明が解決しようとする課題】上述の従来技術では、
以下のような問題点がある。In the above-mentioned prior art,
There are the following problems.

【０００６】従来技術１では、電子部品の外部接続端子
は該電子部品の内部周辺領域に設けられており、一端が
該外部接続端子に接続されたリードが放射状に広がって
該リードの他端が基板のスルーホールに接続される構成
であるため、電子部品の実装領域が電子部品自体の大き
さよりも大きくなってしまうという問題があった。In the prior art 1, an external connection terminal of an electronic component is provided in an inner peripheral area of the electronic component, and a lead having one end connected to the external connection terminal is spread radially, and the other end of the lead is connected to the other end. Since the configuration is such that the electronic component is connected to the through hole of the substrate, there is a problem that the mounting area of the electronic component becomes larger than the size of the electronic component itself.

【０００７】さらに、従来技術１では、電子部品の外部
接続端子から送出される信号が基板に到達するまでの径
路が長くなってしまうため、高速な電子部品の場合に
は、信号伝達が遅延してしまうという問題もあった。Further, in the prior art 1, since the path required for a signal transmitted from the external connection terminal of the electronic component to reach the substrate becomes long, signal transmission is delayed in the case of a high-speed electronic component. There was also a problem that would.

【０００８】また、従来技術１では、テープキャリアに
は接続リードが設けられているが、多ピン狭ピッチにな
るに従って、該テープキャリアの製造が困難になってし
まうという問題があった。さらに、テープキャリアのリ
ードに形成されるスルーホールも該テープキャリア製造
を困難にしてしまう要因であった。In the prior art 1, the tape carrier is provided with connection leads. However, as the number of pins becomes narrower, the production of the tape carrier becomes more difficult. Furthermore, through holes formed in the leads of the tape carrier also made the tape carrier difficult to manufacture.

【０００９】また、従来技術１では、電子部品の外部接
続端子およびリードの接続には、インナー・リード・ボ
ンディング（ＩＬＢ）技術を要するが、該ＩＬＢのため
に専用の製造設備やプロセス、すなわち、フリップチッ
ププロセスやＬＳＩにバンプを設けるプロセスおよびこ
れらのための設備が必要となってしまうという問題もあ
った。In the prior art 1, the connection between the external connection terminal and the lead of the electronic component requires an inner lead bonding (ILB) technique. However, a dedicated manufacturing facility or process for the ILB, that is, There is also a problem that a flip chip process, a process of providing bumps on an LSI, and equipment for these are required.

【００１０】従来技術２では、電子部品が基板と密着し
ているため、電子部品の基板と対向する面からの放熱が
悪くなってしまうという問題がある。さらに、基板上の
接続端子は電子部品の搭載位置の外側に位置するため、
電子部品の搭載領域が電子部品自体の大きさよりも増大
してしまうという問題もある。In the prior art 2, since the electronic component is in close contact with the substrate, there is a problem that heat radiation from the surface of the electronic component facing the substrate is deteriorated. Furthermore, since the connection terminals on the board are located outside the mounting position of the electronic components,
There is also a problem that the mounting area of the electronic component becomes larger than the size of the electronic component itself.

【００１１】本発明の目的は、電子部品の実装のための
領域をより小さくすることができる電子部品の実装構造
およびその製造方法を提供することにある。An object of the present invention is to provide a mounting structure of an electronic component and a method of manufacturing the same, which can reduce the area for mounting the electronic component.

【００１２】また、本発明の他の目的は、電子部品の外
部接続端子から送出される信号を遅延させることのない
電子部品の実装構造およびその製造方法を提供すること
にある。It is another object of the present invention to provide a mounting structure of an electronic component which does not delay a signal transmitted from an external connection terminal of the electronic component, and a method of manufacturing the same.

【００１３】さらに、本発明の他の目的は、テープキャ
リアの製造をより容易にすることができる電子部品の実
装構造およびその製造方法を提供することにある。Still another object of the present invention is to provide a mounting structure of an electronic component and a method of manufacturing the same, which make it easier to manufacture a tape carrier.

【００１４】さらに、本発明の他の目的は、ＩＬＢのた
めの特別な設備やプロセスを不要とする電子部品の実装
構造およびその製造方法を提供することにある。Still another object of the present invention is to provide a mounting structure of an electronic component which does not require a special facility or process for ILB, and a method of manufacturing the same.

【００１５】また、本発明の他の目的は、電子部品の基
板と対向する面から放熱させることができる電子部品の
実装構造およびその製造方法を提供することにある。Another object of the present invention is to provide a mounting structure of an electronic component capable of radiating heat from a surface of the electronic component facing the substrate and a method of manufacturing the same.

【００１６】[0016]

【課題を解決するための手段】上記課題を解決するため
に本発明の電子部品の実装構造は、電子部品と、この電
子部品が搭載される第１の基板と、前記電子部品の、前
記第１の基板と対向する下面に設けられた第１の端子
と、前記第１の基板の、前記第１の端子に対向する位置
に設けられた開口部と、前記第１の基板の、前記電子部
品と対向していない主面における該電子部品の実装領域
に設けられた第２の端子と、前記開口部を通過して前記
第１の端子と前記第２の端子とを接続するワイヤとを備
えたことを特徴とする。According to the present invention, there is provided a mounting structure for an electronic component, comprising: an electronic component; a first substrate on which the electronic component is mounted; A first terminal provided on a lower surface facing the first substrate; an opening provided at a position of the first substrate facing the first terminal; and an electronic device provided on the first substrate. Mounting area of the electronic component on the main surface not facing the component
, And a wire that passes through the opening and connects the first terminal and the second terminal.

【００１７】また、本発明の他の電子部品の実装構造
は、電子部品と、この電子部品が搭載される第１の基板
と、前記電子部品の、前記第１の基板と対向する下面に
設けられた複数の第１の端子と、前記第１の基板の、前
記複数の第１の端子に対向する位置に該複数の第１の端
子に沿った長い穴として形成された開口部と、前記第１
の基板の、前記電子部品と対向していない主面における
該電子部品の実装領域に設けられた第２の端子と、前記
開口部を通過して前記第１の端子と前記第２の端子とを
接続するワイヤとを備えたことを特徴とする。According to another aspect of the present invention, there is provided a mounting structure of an electronic component, a first substrate on which the electronic component is mounted, and a lower surface of the electronic component facing the first substrate. A plurality of first terminals, and an opening formed as a long hole along the plurality of first terminals at a position of the first substrate facing the plurality of first terminals; First
The main surface of the substrate not facing the electronic component
A second terminal provided in a mounting area of the electronic component; and a wire passing through the opening and connecting the first terminal and the second terminal.

【００１８】また、本発明の他の電子部品の実装構造
は、前記第１の基板が実装される第２の基板をさらに含
む。Further, another electronic component mounting structure of the present invention further includes a second substrate on which the first substrate is mounted.

【００１９】また、本発明の他の電子部品の実装構造
は、前記第１の基板の前記電子部品と対向していない主
面における前記電子部品の実装領域に設けられ、前記電
子部品から外部への出力または前記電子部品への外部か
らの入力として用いられる第３の端子を含む。 The electronic component mounting structure according to another aspect of the present invention includes a main component of the first substrate which is not opposed to the electronic component.
Provided in the mounting area of the electronic component on the
Output from the child component to the outside or external to the electronic component
And a third terminal used as an input of the third terminal.

【００２０】また、本発明の他の電子部品の実装構造
は、前記第２の端子毎に設けられ前記第２の基板と電気
的に接続する半田をさらに含むことを特徴とする。According to another aspect of the present invention, there is provided a structure for mounting an electronic component, further comprising solder provided for each of the second terminals and electrically connected to the second substrate.

【００２１】また、本発明の他の電子部品の実装構造
は、前記第１の端子は前記電子部品の下面の周辺領域に
設けられていることを特徴とする。In another aspect of the present invention, the first terminal is provided in a peripheral area on a lower surface of the electronic component.

【００２２】また、本発明の他の電子部品の実装構造
は、前記開口部は前記ワイヤの一端を前記第１の端子に
接続するための治具が少なくとも挿入できる大きさであ
ることを特徴とする。According to another aspect of the present invention, there is provided a mounting structure for an electronic component, wherein the opening is large enough to insert at least a jig for connecting one end of the wire to the first terminal. I do.

【００２３】また、本発明の他の電子部品の実装構造
は、前記第１の基板は１ｍｍ以下の厚さを有する。According to another electronic component mounting structure of the present invention, the first substrate has a thickness of 1 mm or less.

【００２４】また、本発明の他の電子部品の実装構造
は、前記第１の基板は可撓性を有する。In another electronic component mounting structure of the present invention, the first substrate has flexibility.

【００２５】また、本発明の電子部品の実装構造の製造
方法は、電子部品とこの電子部品が実装される基板とを
含む電子部品の実装構造の製造方法であって、前記電子
部品を前記基板の搭載される位置に位置合わせを行い仮
固定する第１の工程と、前記電子部品に設けられた第１
の端子と前記基板の前記電子部品と対向していない主面
における該電子部品の実装領域に設けられた第２の端子
とをワイヤボンディングにより接続する第２の工程とを
含む。The present invention also relates to a method for manufacturing an electronic component mounting structure including an electronic component and a substrate on which the electronic component is mounted, wherein the electronic component is mounted on the substrate. A first step of performing positioning and temporary fixing at a position where the electronic component is mounted, and a first step provided on the electronic component.
Terminal and the main surface of the substrate not facing the electronic component
And a second step of connecting the second terminal provided in the mounting region of the electronic component by wire bonding.

【００２６】[0026]

【発明の実施の形態】次に本発明の電子部品の実装構造
の実施の形態について図面を参照して詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a mounting structure of an electronic component according to the present invention will be described in detail with reference to the drawings.

【００２７】本実施の形態の側面図である図１を参照す
ると、本発明の電子部品の実装構造の第一の実施の形態
は、ＬＳＩ（大規模集積回路）１に設けられたＬＳＩ外
部接続端子７と、テープキャリア基板３のＬＳＩ１と対
向しない主面に設けられＬＳＩ外部接続端子７とワイヤ
４により接続されるワイヤボンディングパッド９とを含
む。ＬＳＩ外部接続端子７はＬＳＩ１のテープキャリア
基板３と対向する主面に設けられている。ＬＳＩ１にお
けるＬＳＩ外部接続端子７の位置は、ＬＳＩ１の下面の
周辺領域であることが望ましい。Referring to FIG. 1 which is a side view of the present embodiment, a first embodiment of a mounting structure of an electronic component according to the present invention is an LSI external connection provided in an LSI (Large Scale Integrated Circuit) 1. It includes a terminal 7 and a wire bonding pad 9 provided on a main surface of the tape carrier substrate 3 not facing the LSI 1 and connected to the LSI external connection terminal 7 by a wire 4. The LSI external connection terminal 7 is provided on a main surface of the LSI 1 facing the tape carrier substrate 3. It is desirable that the position of the LSI external connection terminal 7 in the LSI 1 is in a peripheral area on the lower surface of the LSI 1.

【００２８】ＬＳＩ外部接続端子７とワイヤボンディン
グパッド９とを接続するワイヤ４は、テープキャリア基
板３に設けられた開口部８を通過している。開口部８は
ＬＳＩ外部接続端子７と対向する位置に設けられてい
る。The wires 4 connecting the LSI external connection terminals 7 and the wire bonding pads 9 pass through the openings 8 provided in the tape carrier substrate 3. The opening 8 is provided at a position facing the LSI external connection terminal 7.

【００２９】ＬＳＩ１は、ＬＳＩ外部接続端子７と開口
部８とが対向するように位置決めされてテープキャリア
基板３に搭載される。ＬＳＩ１とテープキャリア基板３
とは、封止樹脂２により封止される。The LSI 1 is mounted on the tape carrier substrate 3 with the LSI external connection terminal 7 and the opening 8 positioned so as to face each other. LSI 1 and tape carrier board 3
Is sealed by the sealing resin 2.

【００３０】テープキャリア基板３のＬＳＩ１と対向し
ない主面には、接続用パッド６が設けられ、接続用パッ
ド６は接続用はんだ５を介して基板１１のパッド１２に
電気的／機械的に接続される。A connection pad 6 is provided on the main surface of the tape carrier substrate 3 not facing the LSI 1, and the connection pad 6 is electrically / mechanically connected to the pad 12 of the substrate 11 via the connection solder 5. Is done.

【００３１】テープキャリア基板３のＬＳＩ１と対向す
る主面には、α線抑止のために厚さが０．１ｍｍ程度の
ポリイミドシートが貼付けられるか、または、シリコー
ンやエポキシ樹脂が塗布される。On the main surface of the tape carrier substrate 3 facing the LSI 1, a polyimide sheet having a thickness of about 0.1 mm is adhered for suppressing α rays, or silicone or epoxy resin is applied.

【００３２】ワイヤボンディングパッド９の材料は金が
望ましく、ワイヤ４の材料はアルミまたは金が良い。The material of the wire bonding pad 9 is preferably gold, and the material of the wire 4 is preferably aluminum or gold.

【００３３】接続用パッド６の材料は、半田と親和性が
あって半田がつきやすい銅や金が良いが、表面が酸化さ
れにくいという性質から金が最適である。The material of the connection pad 6 is preferably copper or gold, which has an affinity for solder and easily adheres to the solder, but gold is optimal because the surface is hardly oxidized.

【００３４】開口部８は、ワイヤボンディングのための
治具を挿入可能な大きさである必要がある。具体的には
１ｍｍ程度の穴が最適である。The opening 8 needs to be large enough to insert a jig for wire bonding. Specifically, a hole of about 1 mm is optimal.

【００３５】基板１１の材料はガラスセラミック、アル
ミナセラミック、樹脂板のいずれでも全く問題は無い
が、反りやうねりが少なく、平面性のよいセラミックが
望ましい。テープキャリア基板３の厚さは、ワイヤ４の
長さが短くなるように１ｍｍ以下が最適である。The material of the substrate 11 may be any one of glass ceramic, alumina ceramic and resin plate, but it is preferable to use a ceramic which has less warpage and undulation and has good flatness. The thickness of the tape carrier substrate 3 is optimally 1 mm or less so that the length of the wire 4 is shortened.

【００３６】テープキャリア基板３が実装される基板１
１の主面にはパッド１２が設けられており、パッド１２
と接続用はんだ５とが接続されてＬＳＩ１が基板１１に
実装される。The substrate 1 on which the tape carrier substrate 3 is mounted
1 is provided with a pad 12 on its main surface.
And the connection solder 5 are connected, and the LSI 1 is mounted on the substrate 11.

【００３７】本実施の形態の斜視図である図２を参照す
ると、開口部８は各ワイヤボンディングパッド９の近傍
に形成されている。これはワイヤ４を極力短くするため
である。ワイヤーボンディングパッド９と接続用パッド
６とは配線１０により接続されている。接続用パッド
６、接続用はんだ５および配線１０は、テープキャリア
基板３のＬＳＩ１が実装される領域の該ＬＳＩ１と対向
しない面にも設けられている。Referring to FIG. 2 which is a perspective view of the present embodiment, an opening 8 is formed near each wire bonding pad 9. This is to make the wire 4 as short as possible. The wire bonding pad 9 and the connection pad 6 are connected by a wiring 10. The connection pad 6, the connection solder 5, and the wiring 10 are also provided on a surface of the tape carrier substrate 3 where the LSI 1 is mounted, which is not opposed to the LSI 1.

【００３８】本実施の形態では、ワイヤ長をより短くす
る目的でワイヤーボンディングパッド９を開口部８の近
傍に形成するようにしたが、ワイヤボンディングを用い
ているためテープキャリア基板３上の任意の位置に配置
してもワイヤーボンディングパッド９とＬＳＩ外部接続
端子７との接続は可能である。。In this embodiment, the wire bonding pad 9 is formed near the opening 8 for the purpose of shortening the wire length. However, since wire bonding is used, any wire bonding pad 9 on the tape carrier substrate 3 can be formed. The wire bonding pad 9 can be connected to the LSI external connection terminal 7 even if it is arranged at the position. .

【００３９】このように、本実施の形態によれば、ＬＳ
Ｉ外部接続端子７がＬＳＩ１の下面の周辺領域に設けら
れ、ワイヤボンディングパッド９がテープキャリア基板
３のＬＳＩ１と対向しない主面に設けられ、ＬＳＩ外部
接続端子７とワイヤボンディングパッド９とが開口部８
を通してワイヤ４により接続される。このため、テープ
キャリア基板３に対するＬＳＩ１の実装領域をより小さ
くすることができる。また、テープキャリア基板３のＬ
ＳＩ１が実装された領域の該ＬＳＩ１と対向しない面に
配線１０を形成できるとともに該面と基板との間に隙間
ができるため、ＬＳＩ１の発生する熱を該隙間から放熱
させることができる。さらに、ＩＬＢのための特別な治
具やプロセスを不要とすることができる。As described above, according to the present embodiment, LS
I external connection terminals 7 are provided in a peripheral area on the lower surface of the LSI 1, wire bonding pads 9 are provided on a main surface of the tape carrier substrate 3 not facing the LSI 1, and the LSI external connection terminals 7 and the wire bonding pads 9 are formed in an opening. 8
Through a wire 4. Therefore, the mounting area of the LSI 1 on the tape carrier substrate 3 can be made smaller. In addition, L of the tape carrier substrate 3
Since the wiring 10 can be formed on a surface of the area where the SI1 is not opposed to the LSI1 and a gap is formed between the surface and the substrate, the heat generated by the LSI1 can be radiated from the gap. Further, a special jig or process for ILB can be eliminated.

【００４０】また、開口部８を各ワイヤボンディングパ
ッド９の近傍に設けたため、ワイヤ４の長さをより短く
することができる。よって、ＬＳＩ１と基板１１との間
での信号伝播遅延を低減できる。Further, since the opening 8 is provided near each wire bonding pad 9, the length of the wire 4 can be further reduced. Therefore, the signal propagation delay between the LSI 1 and the substrate 11 can be reduced.

【００４１】また、開口部８を、ワイヤボンディングの
ための治具が少なくとも挿入可能な大きさとしたため、
テープキャリア基板３における配線領域をより大きくす
ることができる。Since the opening 8 has a size at which a jig for wire bonding can be inserted at least,
The wiring area on the tape carrier substrate 3 can be made larger.

【００４２】次に本発明の電子部品の実装構造の製造方
法について図面を参照して詳細に説明する。Next, a method of manufacturing the electronic component mounting structure of the present invention will be described in detail with reference to the drawings.

【００４３】図３（ａ）を参照すると、第１の工程にお
いて、ＬＳＩ１の回路面上にテープキャリア基板３を位
置あわせし、仮固定をする。まず、ＬＳＩ１の回路面を
上にしておき、その面に封止樹脂２を塗布する。塗布す
る量は、ＬＳＩ１と基板との間隙（約０．１ｍｍ〜０．
５ｍｍ）を充填するのに十分な量とする。この樹脂はα
線対策樹脂である。ＬＳＩの位置あわせは、基板に設け
られた開口部の位置とＬＳＩ上の外部接続端子とを合わ
せることにより行う。Referring to FIG. 3A, in a first step, the tape carrier substrate 3 is positioned on the circuit surface of the LSI 1 and temporarily fixed. First, the circuit surface of the LSI 1 is set up, and the sealing resin 2 is applied to the surface. The amount to be applied is the gap between the LSI 1 and the substrate (about 0.1 mm to 0.1 mm).
5 mm). This resin is α
It is a resin for line protection. The alignment of the LSI is performed by aligning the position of the opening provided in the substrate with the external connection terminal on the LSI.

【００４４】図３（ｂ）を参照すると、第２の工程にお
いて、ＬＳＩの外部接続端子７とテープキャリア基板３
のワイヤボンディングパッド９とをワイヤボンデイング
プロセスを用いて接続する。まず、ワイヤを、テープキ
ャリア基板の開口部８を通してＬＳＩ１の外部接続端子
７に接続し、次に、テープキャリア基板３のワイヤボン
ディングパッド９に接続する。Referring to FIG. 3B, in the second step, the external connection terminals 7 of the LSI and the tape carrier substrate 3
Is connected to the wire bonding pad 9 by using a wire bonding process. First, the wires are connected to the external connection terminals 7 of the LSI 1 through the openings 8 of the tape carrier substrate, and then to the wire bonding pads 9 of the tape carrier substrate 3.

【００４５】図３（ｃ）を参照すると、第３の工程にお
いて、ワイヤボンディング部や基板開口部８が覆われる
ように、また、ＬＳＩ１とテープキャリア基板３との間
隙部分やＬＳＩの側面を覆うように封止樹脂を塗布し、
充填し、硬化させる。Referring to FIG. 3C, in the third step, the wire bonding portion and the substrate opening 8 are covered, and the gap between the LSI 1 and the tape carrier substrate 3 and the side surfaces of the LSI are covered. Apply sealing resin so that
Fill and cure.

【００４６】図３（ｄ）を参照すると、第４の工程にお
いて、ＬＳＩ１が搭載されたテープキャリア基板３を実
装するための外部接続端子に接続用はんだ５を供給す
る。この後、ＬＳＩ１が搭載されたテープキャリア基板
３を基板に実装して基板のパッド１２と接続用はんだ５
とを接続する。Referring to FIG. 3D, in a fourth step, connection solder 5 is supplied to external connection terminals for mounting the tape carrier substrate 3 on which the LSI 1 is mounted. Thereafter, the tape carrier substrate 3 on which the LSI 1 is mounted is mounted on the substrate, and the pads 12 of the substrate and the connection solder 5 are mounted.
And connect.

【００４７】次に、本発明の第二の実施の形態について
図面を参照して詳細に説明する。本実施の形態の特徴は
開口部１３が複数のＬＳＩ外部接続端子７に対向する位
置に該複数のＬＳＩ外部接続端子７に沿った長い穴とし
て形成されている点にある。Next, a second embodiment of the present invention will be described in detail with reference to the drawings. The feature of this embodiment is that the opening 13 is formed as a long hole along the plurality of LSI external connection terminals 7 at a position facing the plurality of LSI external connection terminals 7.

【００４８】図４を参照すると、開口部１３は複数のＬ
ＳＩ外部接続端子７に沿って、長方形状に設けてある。Referring to FIG. 4, opening 13 has a plurality of L's.
It is provided in a rectangular shape along the SI external connection terminal 7.

【００４９】このように、本実施の形態によると、ＬＳ
Ｉ１の外部接続端子７の配列ピッチが微細化された場合
であっても、ワイヤボンディング工程においてワイヤボ
ンディング用の治具を開口部１３に容易に挿入させるこ
とができる。よって、ＬＳＩの微細化、多ピン化に対応
させることができる。As described above, according to the present embodiment, LS
Even if the arrangement pitch of the external connection terminals 7 of I1 is reduced, a jig for wire bonding can be easily inserted into the opening 13 in the wire bonding step. Therefore, it is possible to cope with the miniaturization and the increase in the number of pins of the LSI.

【００５０】また、ＬＳＩの外形が合っていればＬＳＩ
外部接続端子７やワイヤーボンディングパッド９のピッ
チに左右されずに接続させることができるため、ＬＳＩ
の種類によらずに適用できる。If the external shape of the LSI matches,
Since the connection can be made without being influenced by the pitch of the external connection terminal 7 and the wire bonding pad 9, the LSI
It can be applied regardless of the type.

【００５１】上記実施の形態ではテープキャリア基板３
を設けるようにしたが、これに代わってプリンティド・
ワイヤリング・ボード（ＰＷＢ）や、セラミック基板を
設けてもよい。In the above embodiment, the tape carrier substrate 3
, But instead of this,
A wiring board (PWB) or a ceramic substrate may be provided.

【００５２】また、本実施の形態では、α線抑止のため
に封止樹脂２を用いるようにしたが、テープキャリア基
板３自体がα線を抑止可能な樹脂により形成されている
場合やテープキャリア基板３の表面にα線を抑止可能な
樹脂がコーティングされている場合は、テープキャリア
基板３そのものによりα線を抑止できる。In this embodiment, the sealing resin 2 is used to suppress the α-ray. However, the tape carrier substrate 3 itself may be formed of a resin capable of suppressing the α-ray, If the surface of the substrate 3 is coated with a resin capable of suppressing α-rays, the α-rays can be suppressed by the tape carrier substrate 3 itself.

【００５３】[0053]

【発明の効果】以上の説明で明らかなように、本発明
は、ＬＳＩ外部接続端子とワイヤボンディングパッドと
を開口部を通してワイヤにより接続することにより、テ
ープキャリア基板に対するＬＳＩの実装領域をより小さ
くすることができるという効果がある。さらに、本発明
には、テープキャリア基板のＬＳＩが実装された領域の
該ＬＳＩと対向しない面に配線を形成できるとともに該
面と基板との間に隙間ができるため、ＬＳＩの発する熱
を該隙間から放熱させることができるという効果藻あ
る。さらに、ＩＬＢのための特別な治具やプロセスを不
要とすることもできる。As is apparent from the above description, according to the present invention, the LSI mounting area on the tape carrier substrate can be made smaller by connecting the LSI external connection terminal and the wire bonding pad by a wire through the opening. There is an effect that can be. Further, according to the present invention, wiring can be formed on a surface of the tape carrier substrate where the LSI is not mounted and not facing the LSI, and a gap is formed between the surface and the substrate. There is an effect that heat can be released from the algae. Furthermore, a special jig or process for ILB can be eliminated.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第一の実施の形態の断面図である。FIG. 1 is a cross-sectional view of a first embodiment of the present invention.

【図２】本発明の第一の実施の形態の斜視図である。FIG. 2 is a perspective view of the first embodiment of the present invention.

【図３】本発明の製造方法を示す断面図である。FIG. 3 is a cross-sectional view illustrating the manufacturing method of the present invention.

【図４】本発明の第二の実施の形態の斜視図である。FIG. 4 is a perspective view of a second embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１ ＬＳＩ ２ 封止樹脂 ３ テープキャリア基板 ４ ワイヤ ５ 接続用はんだ ６ 接続用パッド ７ ＬＳＩ外部接続端子 ８ 開口部 ９ ワイヤボンディングパッド １０ 配線 １１ 基板 １２ パッド １３ 開口部 DESCRIPTION OF SYMBOLS 1 LSI 2 Sealing resin 3 Tape carrier board 4 Wire 5 Connection solder 6 Connection pad 7 LSI external connection terminal 8 Opening 9 Wire bonding pad 10 Wiring 11 Substrate 12 Pad 13 Opening

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/60 311 H01L 21/60 301──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 21/60 311 H01L 21/60 301

Claims (10)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 電子部品と、 この電子部品が搭載される第１の基板と、 前記電子部品の、前記第１の基板と対向する下面に設け
られた第１の端子と、 前記第１の基板の、前記第１の端子に対向する位置に設
けられた開口部と、 前記第１の基板の、前記電子部品と対向していない主面
における該電子部品の実装領域に設けられた第２の端子
と、 前記開口部を通過して前記第１の端子と前記第２の端子
とを接続するワイヤとを備えたことを特徴とする電子部
品の実装構造。An electronic component; a first substrate on which the electronic component is mounted; a first terminal provided on a lower surface of the electronic component facing the first substrate; An opening provided at a position of the substrate facing the first terminal; and a main surface of the first substrate not facing the electronic component.
A second terminal provided in a mounting area of the electronic component according to the above, and a wire passing through the opening and connecting the first terminal and the second terminal. Component mounting structure. 【請求項２】 電子部品と、 この電子部品が搭載される第１の基板と、 前記電子部品の、前記第１の基板と対向する下面に設け
られた複数の第１の端子と、 前記第１の基板の、前記複数の第１の端子に対向する位
置に該複数の第１の端子に沿った長い穴として形成され
た開口部と、 前記第１の基板の、前記電子部品と対向していない主面
における該電子部品の実装領域に設けられた第２の端子
と、 前記開口部を通過して前記第１の端子と前記第２の端子
とを接続するワイヤとを備えたことを特徴とする電子部
品の実装構造。2. An electronic component; a first substrate on which the electronic component is mounted; a plurality of first terminals provided on a lower surface of the electronic component facing the first substrate; An opening formed as a long hole along the plurality of first terminals in a position of the one substrate facing the plurality of first terminals; and an opening facing the electronic component of the first substrate. Not the main face
A second terminal provided in a mounting area of the electronic component according to the above, and a wire passing through the opening and connecting the first terminal and the second terminal. Component mounting structure. 【請求項３】 前記第１の基板が実装される第２の基板
をさらに含むことを特徴とする請求項１または２記載の
電子部品の実装構造。3. The electronic component mounting structure according to claim 1, further comprising a second substrate on which the first substrate is mounted. 【請求項４】 前記第１の基板の前記電子部品と対向し
ていない主面における前記電子部品の実装領域に設けら
れ、前記電子部品から外部への出力または前記電子部品
への外部からの入力として用いられる第３の端子を含む
ことを特徴とする請求項１または２記載の電子部品の実
装構造。 4. The electronic device of claim 1, wherein said first substrate is opposed to said electronic component.
In the mounting area of the electronic component on the main surface that is not
Output from the electronic component to the outside or the electronic component
The electronic component mounting structure according to claim 1 , further comprising a third terminal used as an external input to the electronic component. 【請求項５】 前記第２の端子毎に設けられ前記第２の
基板と電気的に接続する半田をさらに含むことを特徴と
する請求項１または２記載の電子部品の実装構造。5. The electronic component mounting structure according to claim 1, further comprising a solder provided for each of said second terminals and electrically connected to said second substrate. 【請求項６】 前記第１の端子は前記電子部品の下面の
周辺領域に設けられていることを特徴とする請求項１ま
たは２記載の電子部品の実装構造。6. The electronic component mounting structure according to claim 1, wherein the first terminal is provided in a peripheral region on a lower surface of the electronic component. 【請求項７】 前記開口部は、前記ワイヤの一端を前記
第１の端子に接続するための治具が少なくとも挿入でき
る大きさであることを特徴とする請求項１記載の電子部
品の実装構造。7. The electronic component mounting structure according to claim 1, wherein the opening has a size in which at least a jig for connecting one end of the wire to the first terminal can be inserted. . 【請求項８】 前記第１の基板は１ｍｍ以下の厚さを有
することを特徴とする請求項１または２記載の電子部品
の実装構造。8. The electronic component mounting structure according to claim 1, wherein the first substrate has a thickness of 1 mm or less. 【請求項９】 前記第１の基板は可撓性を有することを
特徴とする請求項１または２記載の電子部品の実装構
造。9. The electronic component mounting structure according to claim 1, wherein the first substrate has flexibility. 【請求項１０】 電子部品とこの電子部品が実装される
基板とを含む電子部品の実装構造の製造方法において、 前記電子部品を前記基板の搭載される位置に位置合わせ
を行い仮固定する第１の工程と、 前記電子部品に設けられた第１の端子と前記基板の前記
電子部品と対向していない主面における該電子部品の実
装領域に設けられた第２の端子とをワイヤボンディング
により接続する第２の工程とを含むことを特徴とする電
子部品の実装構造の製造方法。10. A method of manufacturing a mounting structure of an electronic component including an electronic component and a substrate on which the electronic component is mounted, wherein the electronic component is positioned at a position where the substrate is mounted and temporarily fixed. the steps and, the first terminal and the substrate provided in the electronic component
The realization of the electronic component on the main surface not facing the electronic component
A second step of connecting the second terminal provided in the mounting region to the second terminal by wire bonding.
JP8261786A 1996-10-02 1996-10-02 Electronic component mounting structure and method of manufacturing the same Expired - Lifetime JP2845218B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8261786A JP2845218B2 (en) 1996-10-02 1996-10-02 Electronic component mounting structure and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8261786A JP2845218B2 (en) 1996-10-02 1996-10-02 Electronic component mounting structure and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JPH10107091A JPH10107091A (en) 1998-04-24
JP2845218B2 true JP2845218B2 (en) 1999-01-13

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JP (1) JP2845218B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000156435A (en) 1998-06-22 2000-06-06 Fujitsu Ltd Semiconductor device and manufacture thereof
JP2001298043A (en) * 2000-02-08 2001-10-26 Mitsubishi Electric Corp Semiconductor device and its manufacturing method
KR100713931B1 (en) * 2006-03-29 2007-05-07 주식회사 하이닉스반도체 Semiconductor package having high-speed and high-performance
JP5005636B2 (en) * 2008-08-11 2012-08-22 新光電気工業株式会社 Wiring board and method for manufacturing wiring board
KR101894823B1 (en) * 2011-10-03 2018-09-04 인벤사스 코포레이션 Stub minimization for multi-die wirebond assemblies with parallel windows

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