JPH08288316A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH08288316A JPH08288316A JP8893795A JP8893795A JPH08288316A JP H08288316 A JPH08288316 A JP H08288316A JP 8893795 A JP8893795 A JP 8893795A JP 8893795 A JP8893795 A JP 8893795A JP H08288316 A JPH08288316 A JP H08288316A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- pattern
- solder resist
- circuit board
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Die Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は回路基板にＩＣチップを
実装し、そのＩＣチップを樹脂封止してなる半導体装置
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which an IC chip is mounted on a circuit board and the IC chip is resin-sealed.
【０００２】[0002]
【従来の技術】近年、ＩＣチップの高密度実装に伴い、
多数の電極を有する樹脂封止型半導体装置が開発されて
いる。その代表的なものとしては、ＰＧＡ（ピングリッ
ドアレイ）がある。ＰＧＡは回路基板の一方の面にＩＣ
チップを搭載して樹脂で封止し、他方の面にはＩＣチッ
プと接続した複数のピンを配置した構造をしている。Ｐ
ＧＡはマザーボードに対して着脱可能であるという利点
があるものの、ピンがあるので大型となり小型化が難し
いという問題があった。2. Description of the Related Art In recent years, with the high-density mounting of IC chips,
A resin-sealed semiconductor device having a large number of electrodes has been developed. A typical example thereof is PGA (pin grid array). PGA is an IC on one side of the circuit board
The chip is mounted and sealed with resin, and a plurality of pins connected to the IC chip are arranged on the other surface. P
The GA has an advantage that it can be attached to and detached from the motherboard, but it has a problem that it has a large size because it has a pin and it is difficult to reduce the size.
【０００３】そこで、このＰＧＡに代わる小型の樹脂封
止型半導体装置として、ＢＧＡ（ボールグリッドアレ
イ）が開発されている。以下、図面を用いて一般的なＢ
ＧＡの構造について説明する。Therefore, a BGA (ball grid array) has been developed as a small-sized resin-sealed semiconductor device that replaces the PGA. Below, using the drawings, a general B
The structure of GA will be described.
【０００４】図３は従来のＢＧＡを示す断面図である。
図３において、樹脂基板１１は四角形で板厚が０．２ｍ
ｍ程度のガラスエポキシ樹脂等よりなる上下両面に厚さ
１８μｍ程度の銅箔張りの樹脂基板で、その樹脂基板１
１には複数のスルーホール１３が切削ドリル等の手段に
より加工される。スルーホール１３の壁面を含む基板面
を洗浄した後、樹脂基板１１の全表面に無電解銅メッキ
および電解銅メッキにより銅メッキ層を設ける。その銅
メッキ層はスルーホール１３内まで施される。FIG. 3 is a sectional view showing a conventional BGA.
In FIG. 3, the resin substrate 11 has a square shape and a plate thickness of 0.2 m.
A resin board made of glass epoxy resin or the like having a thickness of about 18 μm and copper foil clad on the upper and lower surfaces.
A plurality of through-holes 13 are processed in 1 by means such as a cutting drill. After cleaning the substrate surface including the wall surface of the through hole 13, a copper plating layer is provided on the entire surface of the resin substrate 11 by electroless copper plating and electrolytic copper plating. The copper plating layer is applied to the inside of the through hole 13.
【０００５】パターンエッチングによって、樹脂基板１
１の上面側にはＩＣチップのダイパターン１５、ワイヤ
ーボンディング用の接続電極２１を、下面側には半田バ
ンプを形成するためのパット電極２３を設ける。なお、
接続電極２１とパット電極２３はスルーホール１３を介
して接続されている。The resin substrate 1 is formed by pattern etching.
A die pattern 15 of an IC chip and a connection electrode 21 for wire bonding are provided on the upper surface side of 1, and a pad electrode 23 for forming a solder bump is provided on the lower surface side. In addition,
The connection electrode 21 and the pad electrode 23 are connected via the through hole 13.
【０００６】次に樹脂基板１１の上下両面の露出してい
る電極の銅メッキ層の表面に、２〜５μｍ程度のＮｉメ
ッキ層を施す。さらにＮｉメッキ層の上にボンディング
ワイヤと接着性の優れた０．５μｍ程度の金メッキ層を
施す。Next, a Ni plating layer of about 2 to 5 μm is applied to the exposed surfaces of the copper plating layers of the electrodes on the resin substrate 11. Further, a gold plating layer of about 0.5 μm having excellent adhesiveness to the bonding wire is applied on the Ni plating layer.
【０００７】また、所定の部分にレジスト処理を行い、
ソルダーレジスト２５を設ける。樹脂基板１１の上面側
のダイパターン１５と接続電極２１および下面側のパッ
ト電極２３にソルダーレジストの開口部を設け、回路基
板２７が完成される。Further, a resist process is applied to a predetermined portion,
A solder resist 25 is provided. The circuit board 27 is completed by providing solder resist openings in the die pattern 15 on the upper surface side of the resin substrate 11, the connection electrodes 21, and the pad electrode 23 on the lower surface side.
【０００８】次に回路基板２７上のダイパターン１５の
金メッキ層の上にＩＣチップ２９を接着剤３１を用いて
直接固着し、そのＩＣチップ２９の電源端子と接続電極
２１とをボンディングワイヤ３５で接続した後、そのＩ
Ｃチップ２９およびボンディングワイヤ３５を熱硬化性
の封止樹脂３７でトランスファーモールドにより樹脂封
止することで、ＩＣチップ２９の遮光と保護を行う。Next, the IC chip 29 is directly fixed on the gold plating layer of the die pattern 15 on the circuit board 27 using an adhesive 31, and the power supply terminal of the IC chip 29 and the connection electrode 21 are bonded by the bonding wire 35. After connecting, I
The C chip 29 and the bonding wire 35 are resin-sealed with a thermosetting sealing resin 37 by transfer molding, so that the IC chip 29 is shielded from light and protected.
【０００９】また、樹脂基板１１の下面側のパット電極
２３には半田ボールを供給し、加熱炉で加熱することに
より、半田バンプ３９が設けられる。この半田バンプ３
９により、図示しないマザーボード基板のパターンと導
通される。以上によりＢＧＡ４１が完成される。Also, solder bumps 39 are provided by supplying solder balls to the pad electrodes 23 on the lower surface side of the resin substrate 11 and heating them in a heating furnace. This solder bump 3
By means of 9, the pattern is electrically connected to the pattern on the mother board (not shown). The BGA 41 is completed by the above.
【００１０】[0010]
【発明が解決しようとする課題】前述した半導体装置に
は次のような問題点がある。The above-mentioned semiconductor device has the following problems.
【００１１】ＢＧＡ４１は、ＢＧＡ４１を構成する樹脂
基板１１に使用するガラスエポキシ樹脂と、封止樹脂３
７に使用する熱硬化性樹脂およびダイパターン１５を構
成する銅パターンとで、それぞれの線膨張係数が異な
る。その値は、樹脂基板１１のガラスエポキシ樹脂が１
４ｐｐｍ／℃、封止樹脂３７の熱硬化性樹脂が１６ｐｐ
ｍ／℃、ダイパターン１５を構成する銅パターンが１７
ｐｐｍ／℃である。The BGA 41 comprises a glass epoxy resin used for the resin substrate 11 constituting the BGA 41 and a sealing resin 3.
The coefficient of linear expansion differs between the thermosetting resin used for No. 7 and the copper pattern forming the die pattern 15. The value is 1 for the glass epoxy resin of the resin substrate 11.
4ppm / ℃, thermosetting resin of sealing resin 37 is 16pp
m / ° C, the copper pattern composing the die pattern 15 is 17
ppm / ° C.
【００１２】ＢＧＡをマザーボード基板に実装する際、
加熱炉で加熱する。この時、前述したガラスエポキシ樹
脂、熱硬化性樹脂および銅パターンの線膨張係数が異な
ることから、三者の収縮率が異なり、図３に示すＢＧＡ
４１は、図４に示すようにＩＣチップ２９側に反る。When mounting the BGA on the mother board,
Heat in a heating furnace. At this time, since the glass epoxy resin, the thermosetting resin, and the copper pattern described above have different linear expansion coefficients, the shrinkage rates of the three differ, and the BGA shown in FIG.
41 bends toward the IC chip 29 side as shown in FIG.
【００１３】図４に示すように、ＢＧＡ４１がＩＣチッ
プ側に反ることから、接着剤の密着力は低下し、ＩＣチ
ップは、外周周辺部より剥離する。As shown in FIG. 4, since the BGA 41 is warped toward the IC chip side, the adhesive force of the adhesive is reduced, and the IC chip is peeled off from the peripheral area.
【００１４】また接着剤３１の密着力は接着する対象物
で異なり、ダイパターン１５上の金メッキ層の場合は特
に密着力は低下する。またＢＧＡ４１のパッケージの大
きさに対し、ＩＣチップ２９の大きさが大きくなるにし
たがってこの傾向は、さらに大きくなる。Further, the adhesive force of the adhesive 31 differs depending on the objects to be adhered, and particularly the adhesive force is lowered in the case of the gold plating layer on the die pattern 15. This tendency becomes even larger as the size of the IC chip 29 becomes larger than the size of the package of the BGA 41.
【００１５】ＩＣチップ２９の外周周辺部付近の剥離に
より、ＩＣチップ２９が動き、ボンディングワイヤ３５
の切れ等が発生し、半導体装置の信頼性を損なう可能性
があった。By peeling off the periphery of the IC chip 29, the IC chip 29 moves, and the bonding wire 35
There is a possibility that the semiconductor device may be broken and the reliability of the semiconductor device may be deteriorated.
【００１６】本発明の目的は、上記課題を解決して、Ｂ
ＧＡがＩＣチップ側に反っても密着力は低下せず、ＩＣ
チップの外周周辺部付近で剥離しない、信頼性の高い半
導体装置を提供することである。The object of the present invention is to solve the above problems by
Even if the GA warps to the IC chip side, the adhesion does not decrease, and the IC
It is an object of the present invention to provide a highly reliable semiconductor device that does not peel off near the periphery of the chip.
【００１７】[0017]
【課題を解決するための手段】上記目的を達成するため
に、本発明における半導体装置は、下記記載の構成を採
用する。In order to achieve the above object, the semiconductor device of the present invention adopts the structure described below.
【００１８】樹脂基板とその樹脂基板上に設けられた金
属パターンおよびソルダーレジストよりなる回路基板に
ＩＣチップを接着剤で固着し、そのＩＣチップを樹脂封
止してなる半導体装置において、ＩＣチップ固着部の回
路基板のＩＣチップ固着側に、ＩＣチップサイズより小
さいダイパターンおよびＩＣチップサイズより大きいソ
ルダーレジストを全面に、また、ＩＣチップ固着部の回
路基板のＩＣチップ固着側の反対側にＩＣチップ固着側
とほぼ同面積の金属パターンおよびソルダーレジストが
設けられていることを特徴とするものである。In a semiconductor device in which an IC chip is fixed to a circuit board made of a resin substrate, a metal pattern provided on the resin substrate and a solder resist with an adhesive, and the IC chip is resin-sealed, the IC chip is fixed. A die pattern smaller than the IC chip size and a solder resist larger than the IC chip size on the entire surface of the circuit board of the IC chip fixing side, and an IC chip on the opposite side of the IC chip fixing side of the circuit board of the IC chip fixing portion. A metal pattern and a solder resist having substantially the same area as the fixed side are provided.
【００１９】また、ＩＣチップの周囲に電源パターンを
設け、この電源パターンとＩＣチップが導電性接着剤で
固着され、さらに電源パターンとＩＣチップサイズより
小さい金属パターンが配線パターンで電気的に接続され
ていることを特徴とするものである。Further, a power source pattern is provided around the IC chip, the power source pattern and the IC chip are fixed by a conductive adhesive, and the power source pattern and a metal pattern smaller than the IC chip size are electrically connected by a wiring pattern. It is characterized by that.
【００２０】[0020]
【作用】本発明において、回路基板のＩＣチップ固着側
の反対側にＩＣチップ固着側とほぼ同面積の金属パター
ンおよびソルダーレジストを設けることによって、回路
基板両面のパターンバランスが良好となり、回路基板の
反りを抑制できる。In the present invention, by providing the metal pattern and the solder resist of the same area as the IC chip fixing side on the side opposite to the IC chip fixing side of the circuit board, the pattern balance on both sides of the circuit board becomes good, and the circuit board Warp can be suppressed.
【００２１】ダイパターンをＩＣチップサイズより小さ
くし、このダイパターンをＩＣチップサイズより大きい
ソルダーレジストで覆う。ＩＣチップは導電性接着剤を
用いて、ソルダーレジスト上に固着される。このために
ＩＣチップとソルダーレジストの密着力が高まる。The die pattern is made smaller than the IC chip size, and the die pattern is covered with a solder resist larger than the IC chip size. The IC chip is fixed on the solder resist using a conductive adhesive. Therefore, the adhesion between the IC chip and the solder resist is enhanced.
【００２２】ＩＣチップを取り囲むように電源パターン
を設け、この電源パターンとＩＣチップの電源端子とが
電源パターンの延長がなくても自由に接続することがで
きる。A power supply pattern is provided so as to surround the IC chip, and the power supply pattern and the power supply terminal of the IC chip can be freely connected without extending the power supply pattern.
【００２３】導電性接着剤を用いてＩＣチップを固着す
る際、導電性接着剤は電源パターン上にも塗布される。
これにより、ＩＣチップとダイパターンは電気的に接続
される。When the IC chip is fixed by using the conductive adhesive, the conductive adhesive is also applied on the power supply pattern.
As a result, the IC chip and the die pattern are electrically connected.
【００２４】[0024]
【実施例】以下、図面を用いて本発明の実施例における
半導体装置について説明する。図１および図２は本発明
の実施例で、図１はＢＧＡパッケージの要部断面図、図
２は図１の平面図である。図において、従来技術と同一
部材は同一符号で示す。DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. 1 and 2 show an embodiment of the present invention. FIG. 1 is a sectional view of a main part of a BGA package, and FIG. 2 is a plan view of FIG. In the drawings, the same members as those in the conventional technique are designated by the same reference numerals.
【００２５】まず図１および図２において、前述した従
来技術の図３と同様に、樹脂基板１１の両面に薄い銅箔
が積層されていて、スルーホール１３の穴開け加工後、
両面銅張りされた樹脂基板１１の全表面に無電解銅メッ
キおよび電解銅メッキにより銅メッキ層を設ける。その
銅メッキ層はスルーホール１３内まで施される。First, in FIGS. 1 and 2, similar to FIG. 3 of the above-mentioned prior art, thin copper foils are laminated on both surfaces of the resin substrate 11, and after the through hole 13 is drilled,
A copper plating layer is provided on the entire surface of the resin substrate 11 which is copper-coated on both sides by electroless copper plating and electrolytic copper plating. The copper plating layer is applied to the inside of the through hole 13.
【００２６】次にパターンエッチングによって、樹脂基
板１１の上面側にはＩＣチップのダイパターン１５、Ｉ
Ｃチップの周囲を取り囲むグランド系の電源パターン１
７ａ、電源系の電源パターン１７ｂ、ダイパターン１５
と電源パターン１７ａを接続する配線パターン１９およ
びワイヤーボンディング用の接続電極２１を設ける。ま
た樹脂基板１１の下面側には半田バンプを形成するため
のパット電極２３をマトリックス状に設ける。この時、
下面側のパット電極２３を含めた金属パターンは、上面
側のダイパターン１５、電源パターン１７ａ、１７ｂ、
配線パターン１９、接続電極２１を合わせた面積とほぼ
同面積になるように設けられる。なおダイパターン１
５、電源パターン１７ａ、１７ｂ、接続電極２１および
パット電極２３はスルーホール１３を介して接続されて
いる。Next, by pattern etching, the die patterns 15, I of the IC chip are formed on the upper surface of the resin substrate 11.
Ground-type power supply pattern 1 surrounding the C chip
7a, power supply pattern 17b of power supply system, die pattern 15
A wiring pattern 19 for connecting the power supply pattern 17a with the wiring pattern 19 and a connection electrode 21 for wire bonding are provided. Further, on the lower surface side of the resin substrate 11, pad electrodes 23 for forming solder bumps are provided in a matrix. This time,
The metal pattern including the pad electrode 23 on the lower surface side includes the die pattern 15 on the upper surface side, the power source patterns 17a and 17b,
The wiring pattern 19 and the connection electrode 21 are provided so as to have almost the same area. Die pattern 1
5, the power supply patterns 17a and 17b, the connection electrode 21 and the pad electrode 23 are connected through the through hole 13.
【００２７】次に樹脂基板１１の上下両面の露出してい
る電極の銅メッキ層の表面に、２〜５μｍ程度のＮｉメ
ッキ層を施す。さらにＮｉメッキ層の上にボンディング
ワイヤと接着性の優れた０．５μｍ程度の金メッキ層を
施す。Next, a Ni plating layer having a thickness of about 2 to 5 μm is formed on the surfaces of the copper plating layers of the exposed electrodes on the upper and lower surfaces of the resin substrate 11. Further, a gold plating layer of about 0.5 μm having excellent adhesiveness to the bonding wire is applied on the Ni plating layer.
【００２８】次に樹脂基板１１にレジスト処理を行い、
樹脂基板１１の上面側には、電源パターン１７ａ、１７
ｂ、接続電極２１に開口部を有するソルダーレジスト２
５を設ける。樹脂基板１１の下面側には、パット電極２
３に半田バンプを形成するための開口部を有するソルダ
ーレジストを設ける。これで回路基板２７が完成され
る。Next, the resin substrate 11 is subjected to resist treatment,
On the upper surface side of the resin substrate 11, the power supply patterns 17a, 17
b, a solder resist 2 having an opening in the connection electrode 21
5 is provided. The pad electrode 2 is provided on the lower surface side of the resin substrate 11.
3 is provided with a solder resist having openings for forming solder bumps. This completes the circuit board 27.
【００２９】樹脂基板１１の上面側のソルダーレジスト
２５と、下面側のソルダーレジスト２５は、ほぼ同面積
になるように設けられる。The solder resist 25 on the upper surface side and the solder resist 25 on the lower surface side of the resin substrate 11 are provided so as to have substantially the same area.
【００３０】次に回路基板２７の上面側のに設けられて
いるソルダーレジスト２５上に、ＩＣチップ２９を導電
性接着剤３３を用いて固着する。この導電性接着剤３３
は、電源パターン１７ａ上にも塗布され、ＩＣチップ２
９とダイパターン１５が電気的に接続されている。Next, the IC chip 29 is fixed on the solder resist 25 provided on the upper surface side of the circuit board 27 using the conductive adhesive 33. This conductive adhesive 33
Is also applied on the power supply pattern 17a, and the IC chip 2
9 and the die pattern 15 are electrically connected.
【００３１】次にＩＣチップ２９の電源端子は、ソルダ
ーレジスト２５の外側に露出した電源パターン１７ｂお
よび回路基板２７の外周周辺部に設けられている接続電
極２１とボンディングワイヤ３５でワイヤーボンディン
グされる。Next, the power supply terminal of the IC chip 29 is wire-bonded with the bonding wire 35 to the power supply pattern 17b exposed on the outside of the solder resist 25 and the connection electrode 21 provided on the outer peripheral portion of the circuit board 27.
【００３２】次にＩＣチップの遮光と保護のために熱硬
化性の封止樹脂３７でトランスファーモールドにより、
樹脂封止する。さらに回路基板２７の下面側には、複数
の半田付け可能なパット電極２３に半田ボールを供給
し、加熱炉中で加熱することにより半田バンプ３９が設
けられる。この半田バンプ３９により、図示しないマザ
ーボード基板のパターンと導通される。以上により、Ｂ
ＧＡ４１が完成される。Next, transfer molding is performed with a thermosetting encapsulating resin 37 for light shielding and protection of the IC chip.
Seal with resin. Further, solder bumps 39 are provided on the lower surface side of the circuit board 27 by supplying solder balls to a plurality of solderable pad electrodes 23 and heating them in a heating furnace. The solder bumps 39 are electrically connected to a pattern on a mother board (not shown). From the above, B
GA41 is completed.
【００３３】本発明の半導体装置において、ＩＣチップ
２９は、導電性接着剤３３を用いて全面、ソルダーレジ
スト２５上に確実に固着される。In the semiconductor device of the present invention, the IC chip 29 is securely fixed on the entire surface of the solder resist 25 by using the conductive adhesive 33.
【００３４】なお、本実施例はＢＧＡの半導体装置につ
いて説明したが、樹脂封止型半導体装置、例えば、ピン
グリッドアレイ（ＰＧＡ）の半導体装置についても適用
される。Although this embodiment describes the BGA semiconductor device, the present invention is also applicable to a resin-sealed semiconductor device such as a pin grid array (PGA) semiconductor device.
【００３５】[0035]
【発明の効果】以上の説明で明らかなように、本発明に
おいては、ＩＣチップが位置決めされる部分にＩＣチッ
プサイズより小さいダイパターンおよびＩＣチップサイ
ズより大きいソルダーレジストが全面に設けられ、ＩＣ
チップは導電性接着剤を用いて、ソルダーレジスト上に
固着されている。As is apparent from the above description, in the present invention, a die pattern smaller than the IC chip size and a solder resist larger than the IC chip size are provided on the entire surface in the portion where the IC chip is positioned.
The chip is fixed on the solder resist using a conductive adhesive.
【００３６】したがって、従来の金メッキ層の上に接着
する場合と異なり、接着剤の密着力は低下せず、ＩＣチ
ップは外周周辺部で剥離しない。このためＩＣチップは
確実に固定され、ボンディングワイヤの切れ等の発生も
なく、信頼性の高い半導体装置が得られる。Therefore, unlike the conventional case of adhering on the gold-plated layer, the adhesive strength of the adhesive does not decrease, and the IC chip does not peel off at the peripheral portion. Therefore, the IC chip is securely fixed, the bonding wire is not broken, and a highly reliable semiconductor device can be obtained.
【００３７】また、ＩＣチップの周囲に電源パターンを
設けることによって、特別に電源パターンの引き回しを
行わなくても、電源パターンとＩＣチップの電源端子位
置とを接続することができる。さらに、電源パターンと
ＩＣチップを導電性接着剤で固着することにより、ＩＣ
チップの電源端子と電源パターンとをボンディングワイ
ヤによる接続を行う必要がない。Further, by providing the power supply pattern around the IC chip, the power supply pattern and the power supply terminal position of the IC chip can be connected without specially arranging the power supply pattern. Furthermore, by fixing the power supply pattern and the IC chip with a conductive adhesive, the IC
It is not necessary to connect the power supply terminal of the chip and the power supply pattern with a bonding wire.
【図１】本発明の実施例における半導体装置の要部断面
図である。FIG. 1 is a cross-sectional view of essential parts of a semiconductor device according to an embodiment of the present invention.
【図２】図１の平面図である。FIG. 2 is a plan view of FIG.
【図３】従来技術における半導体装置の要部断面図であ
る。FIG. 3 is a cross-sectional view of a main part of a semiconductor device according to a conventional technique.
【図４】従来技術における半導体装置の反りを示す要部
断面図である。FIG. 4 is a cross-sectional view of a main part showing a warp of a semiconductor device according to a conventional technique.
１１ 樹脂基板 １５ ダイパターン １７ 電源パターン １９ 配線パターン ２５ ソルダーレジスト ２７ 回路基板 ２９ ＩＣチップ ３３ 導電性接着剤 11 Resin Substrate 15 Die Pattern 17 Power Supply Pattern 19 Wiring Pattern 25 Solder Resist 27 Circuit Board 29 IC Chip 33 Conductive Adhesive
Claims (2)
金属パターンおよびソルダーレジストよりなる回路基板
にＩＣチップを接着剤で固着し、そのＩＣチップを樹脂
封止してなる半導体装置において、ＩＣチップ固着部の
回路基板のＩＣチップ固着側に、ＩＣチップサイズより
小さいダイパターンおよびＩＣチップサイズより大きい
ソルダーレジストを全面に、またＩＣチップ固着部の回
路基板のＩＣチップ固着側の反対側に、ＩＣチップ固着
側とほぼ同面積の金属パターンおよびソルダーレジスト
が設けられていることを特徴とする半導体装置。1. A semiconductor device in which an IC chip is fixed to a circuit board composed of a resin substrate, a metal pattern provided on the resin substrate, and a solder resist with an adhesive, and the IC chip is resin-sealed. A die pattern smaller than the IC chip size and a solder resist larger than the IC chip size are provided on the entire surface of the chip fixing portion on the IC chip fixing side of the circuit board, and on the opposite side of the IC chip fixing side of the circuit board of the IC chip fixing portion. A semiconductor device, wherein a metal pattern and a solder resist having substantially the same area as the IC chip fixed side are provided.
け、この電源パターンとＩＣチップが導電性接着剤で固
着され、かつ電源パターンとダイパターンが配線パター
ンで電気的に接続されていることを特徴とする請求項１
記載の半導体装置。2. A power supply pattern is provided around the IC chip, the power supply pattern and the IC chip are fixed by a conductive adhesive, and the power supply pattern and the die pattern are electrically connected by a wiring pattern. Claim 1
13. The semiconductor device according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8893795A JPH08288316A (en) | 1995-04-14 | 1995-04-14 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8893795A JPH08288316A (en) | 1995-04-14 | 1995-04-14 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08288316A true JPH08288316A (en) | 1996-11-01 |
Family
ID=13956810
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8893795A Pending JPH08288316A (en) | 1995-04-14 | 1995-04-14 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08288316A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998043288A1 (en) * | 1997-03-24 | 1998-10-01 | Seiko Epson Corporation | Semiconductor device and method for manufacturing the same |
| JP2003092374A (en) * | 2001-09-18 | 2003-03-28 | Hitachi Ltd | Semiconductor device and method of manufacturing the same |
| US6731013B2 (en) * | 2000-06-28 | 2004-05-04 | Sharp Kabushiki Kaisha | Wiring substrate, semiconductor device and package stack semiconductor device |
| JP2007227609A (en) * | 2006-02-23 | 2007-09-06 | Seiko Epson Corp | Semiconductor device and method of manufacturing semiconductor device |
| JP2008172267A (en) * | 2000-07-21 | 2008-07-24 | Agere Systems Guardian Corp | Method of manufacturing integrated circuit package and integrated circuit package |
| US7566969B2 (en) | 2005-01-05 | 2009-07-28 | Renesas Technology Corp. | Semiconductor device with improved arrangement of a through-hole in a wiring substrate |
| WO2009121200A1 (en) * | 2008-03-31 | 2009-10-08 | 巨擘科技股份有限公司 | Method of balancing multilayer substrate stress and multilayer substrate |
-
1995
- 1995-04-14 JP JP8893795A patent/JPH08288316A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998043288A1 (en) * | 1997-03-24 | 1998-10-01 | Seiko Epson Corporation | Semiconductor device and method for manufacturing the same |
| US6489668B1 (en) | 1997-03-24 | 2002-12-03 | Seiko Epson Corporation | Semiconductor device and method for manufacturing the same |
| US6731013B2 (en) * | 2000-06-28 | 2004-05-04 | Sharp Kabushiki Kaisha | Wiring substrate, semiconductor device and package stack semiconductor device |
| JP2008172267A (en) * | 2000-07-21 | 2008-07-24 | Agere Systems Guardian Corp | Method of manufacturing integrated circuit package and integrated circuit package |
| JP2003092374A (en) * | 2001-09-18 | 2003-03-28 | Hitachi Ltd | Semiconductor device and method of manufacturing the same |
| US7566969B2 (en) | 2005-01-05 | 2009-07-28 | Renesas Technology Corp. | Semiconductor device with improved arrangement of a through-hole in a wiring substrate |
| JP2007227609A (en) * | 2006-02-23 | 2007-09-06 | Seiko Epson Corp | Semiconductor device and method of manufacturing semiconductor device |
| WO2009121200A1 (en) * | 2008-03-31 | 2009-10-08 | 巨擘科技股份有限公司 | Method of balancing multilayer substrate stress and multilayer substrate |
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