JP2007227609A - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Semiconductor device and method of manufacturing semiconductor device Download PDF

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JP2007227609A
JP2007227609A JP2006046460A JP2006046460A JP2007227609A JP 2007227609 A JP2007227609 A JP 2007227609A JP 2006046460 A JP2006046460 A JP 2006046460A JP 2006046460 A JP2006046460 A JP 2006046460A JP 2007227609 A JP2007227609 A JP 2007227609A
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carrier substrate
semiconductor chip
resin
protective film
semiconductor
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Hirohisa Nakayama
浩久 中山
Toru Fujita
透 藤田
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Seiko Epson Corp
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Seiko Epson Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Abstract

<P>PROBLEM TO BE SOLVED: To seal a facedown-mounted semiconductor chip while preventing the occurrence of a gap between the side of the semiconductor chip and a carrier substrate. <P>SOLUTION: Resins 8a, 8b are each arranged on the carrier substrate 1, and then, the semiconductor chips 5a, 5b are facedown-mounted on the carrier substrate 1, thereby forming the semiconductor chips 5a, 5b on the carrier substrate 1 with the resins 8a, 8b. Protruding electrodes 7a, 7b are joined onto a land 3, and a protective film 9 arranged so as to cover the entire of the resins 8a, 8b overflown to the side of the semiconductor chips 5a, 5b is formed. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は半導体装置および半導体装置の製造方法に関し、特に、半導体パッケージの封止方法に適用して好適なものである。   The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device, and is particularly suitable for application to a semiconductor package sealing method.

従来の半導体装置では、バンプ電極を介して基板上にフェースダウン実装された半導体チップの表面を封止するため、アンダーチップフィラーと呼ばれる樹脂を半導体チップとキャリア基板との間に充填する方法がある。
また、例えば、特許文献１には、特性の劣化を招くことなく、高密度実装を達成するために、配線基板に半導体チップをフェースダウン実装する時に、半導体チップの回路面と対向する位置に消失可能な犠牲層を設け、半導体チップを配線基板に実装した後に犠牲層を消失させて、半導体チップの回路面と配線基板との間に空隙を形成する方法が開示されている。
特開２００１−６０６４２号公報 In a conventional semiconductor device, there is a method in which a resin called an under-chip filler is filled between a semiconductor chip and a carrier substrate in order to seal the surface of a semiconductor chip face-down mounted on a substrate via a bump electrode. .
In addition, for example, in Patent Document 1, when a semiconductor chip is face-down mounted on a wiring board in order to achieve high-density mounting without causing deterioration of characteristics, it disappears at a position facing the circuit surface of the semiconductor chip. A method is disclosed in which a possible sacrificial layer is provided, the sacrificial layer is eliminated after the semiconductor chip is mounted on the wiring substrate, and a gap is formed between the circuit surface of the semiconductor chip and the wiring substrate.
JP 2001-60642 A

しかしながら、従来の半導体装置では、アンダーチップフィラーの硬化収縮により半導体チップの側面とキャリア基板との間に隙間が発生するため、この隙間を介して水分が浸透し、半導体パッケージの信頼性を低下させるという問題があった。
そこで、本発明の目的は、半導体チップの側面とキャリア基板との間に隙間が発生することを防止しつつ、フェースダウン実装された半導体チップを封止することが可能な半導体装置および半導体装置の製造方法を提供することである。 However, in the conventional semiconductor device, a clearance is generated between the side surface of the semiconductor chip and the carrier substrate due to curing shrinkage of the underchip filler, so that moisture permeates through the clearance and decreases the reliability of the semiconductor package. There was a problem.
Accordingly, an object of the present invention is to provide a semiconductor device and a semiconductor device capable of sealing a semiconductor chip mounted face-down while preventing a gap from being generated between the side surface of the semiconductor chip and the carrier substrate. It is to provide a manufacturing method.

上述した課題を解決するために、本発明の一態様に係る半導体装置によれば、電極パッドが形成された半導体チップと、前記電極パッド上に配置された突出電極を介して前記半導体チップがフェースダウン実装されたキャリア基板と、前記半導体チップと前記キャリア基板との間に充填された樹脂と、前記半導体チップの側面にはみ出した部分の前記樹脂全体を覆うように配された保護膜とを備えることを特徴とする。   In order to solve the above-described problem, according to a semiconductor device of one embodiment of the present invention, a semiconductor chip on which an electrode pad is formed and the semiconductor chip faced through a protruding electrode disposed on the electrode pad. A down-mounted carrier substrate; a resin filled between the semiconductor chip and the carrier substrate; and a protective film disposed so as to cover the entire resin at a portion protruding from a side surface of the semiconductor chip. It is characterized by that.

これにより、半導体チップの側面と樹脂との間に隙間が生じた場合においても、半導体チップの側面と樹脂との間の隙間を保護膜にて塞ぐことができる。このため、半導体チップと樹脂との結合性を向上させることが可能となるとともに、樹脂が形成された半導体チップの側面を介して水分が浸透することを防止することが可能となり、フェースダウン実装された半導体チップの信頼性を向上させることができる。   Thus, even when a gap is generated between the side surface of the semiconductor chip and the resin, the gap between the side surface of the semiconductor chip and the resin can be closed with the protective film. This makes it possible to improve the bonding between the semiconductor chip and the resin, and to prevent moisture from penetrating through the side surface of the semiconductor chip on which the resin is formed. The reliability of the semiconductor chip can be improved.

また、本発明の一態様に係る半導体装置によれば、電極パッドが形成された半導体チップと、前記電極パッド上に配置された突出電極を介して前記半導体チップがフェースダウン実装されたキャリア基板と、前記半導体チップと前記キャリア基板との間に充填された樹脂と、前記樹脂が充填された前記キャリア基板の全面を覆うように配された保護膜とを備えることを特徴とする。   In addition, according to the semiconductor device of one aspect of the present invention, a semiconductor chip on which an electrode pad is formed, a carrier substrate on which the semiconductor chip is mounted face-down via a protruding electrode disposed on the electrode pad, And a resin filled between the semiconductor chip and the carrier substrate, and a protective film disposed to cover the entire surface of the carrier substrate filled with the resin.

これにより、製造工程の煩雑化を抑制しつつ、半導体チップと樹脂との結合性を向上させることが可能となるとともに、半導体チップの側面と樹脂との間に隙間が生じた場合においても、樹脂が形成された半導体チップの側面を介して水分が浸透することを防止することが可能となり、フェースダウン実装された半導体チップの信頼性を向上させることができる。   As a result, it is possible to improve the bonding between the semiconductor chip and the resin while suppressing complication of the manufacturing process, and the resin can be used even when a gap is generated between the side surface of the semiconductor chip and the resin. It is possible to prevent moisture from penetrating through the side surface of the semiconductor chip on which the semiconductor chip is formed, and the reliability of the semiconductor chip mounted face-down can be improved.

また、本発明の一態様に係る半導体装置によれば、電極パッドが形成された半導体チップと、前記電極パッド上に配置された突出電極を介して前記半導体チップがフェースダウン実装されたキャリア基板と、前記半導体チップと前記キャリア基板との間に充填された樹脂と、前記樹脂が充填された前記キャリア基板の全面および裏面を覆うように配された保護膜とを備えることを特徴とする。   In addition, according to the semiconductor device of one aspect of the present invention, a semiconductor chip on which an electrode pad is formed, a carrier substrate on which the semiconductor chip is mounted face-down via a protruding electrode disposed on the electrode pad, And a resin filled between the semiconductor chip and the carrier substrate, and a protective film disposed so as to cover the entire surface and the back surface of the carrier substrate filled with the resin.

これにより、製造工程の煩雑化を抑制しつつ、半導体チップと樹脂との結合性を向上させることが可能となるとともに、半導体チップの側面と樹脂との間に隙間が生じた場合においても、樹脂が形成された半導体チップの側面を介して水分が浸透することを防止することが可能となり、フェースダウン実装された半導体チップの信頼性を向上させることができる。   As a result, it is possible to improve the bonding between the semiconductor chip and the resin while suppressing complication of the manufacturing process, and the resin can be used even when a gap is generated between the side surface of the semiconductor chip and the resin. It is possible to prevent moisture from penetrating through the side surface of the semiconductor chip on which the semiconductor chip is formed, and the reliability of the semiconductor chip mounted face-down can be improved.

また、本発明の一態様に係る半導体装置によれば、前記保護膜の膜厚は５〜３０μｍの範囲内であることを特徴とする。
これにより、キャリア基板上に保護膜を形成した場合においても、保護膜との熱膨張係数差に起因するキャリア基板の反りを抑制することが可能となるとともに、熱ストレスに起因する保護膜のクラックを防止することができる。また、保護膜にて半導体チップが覆われた場合においても、半導体チップに形成された識別マークの視認性を確保することができる。 In the semiconductor device according to one embodiment of the present invention, the protective film has a thickness in the range of 5 to 30 μm.
As a result, even when a protective film is formed on the carrier substrate, it is possible to suppress the warpage of the carrier substrate due to the difference in thermal expansion coefficient from the protective film and to prevent the protective film from cracking due to thermal stress. Can be prevented. Further, even when the semiconductor chip is covered with the protective film, the visibility of the identification mark formed on the semiconductor chip can be ensured.

また、本発明の一態様に係る半導体装置の製造方法によれば、樹脂を介してキャリア基板上に半導体チップをフェースダウン実装する工程と、前記半導体チップの側面にはみ出した部分の前記樹脂全体が覆われるように配された保護膜を形成する工程とを備えることを特徴とする。
これにより、半導体チップの側面と樹脂との間に隙間が生じた場合においても、半導体チップの側面と樹脂との間の隙間を保護膜にて塞ぐことができ、樹脂が形成された半導体チップの側面を介して水分が浸透することを防止することを可能として、フェースダウン実装された半導体チップの信頼性を向上させることができる。 In addition, according to the method for manufacturing a semiconductor device of one embodiment of the present invention, the step of mounting the semiconductor chip face down on the carrier substrate via the resin, and the entire resin at the portion protruding from the side surface of the semiconductor chip And a step of forming a protective film disposed so as to be covered.
Thereby, even when a gap is generated between the side surface of the semiconductor chip and the resin, the gap between the side surface of the semiconductor chip and the resin can be closed by the protective film, and the semiconductor chip on which the resin is formed can be closed. It is possible to prevent moisture from penetrating through the side surface, and the reliability of the semiconductor chip mounted face-down can be improved.

また、本発明の一態様に係る半導体装置の製造方法によれば、樹脂を介してキャリア基板上に半導体チップをフェースダウン実装する工程と、前記半導体チップがフェースダウン実装されたキャリア基板上の全面を覆うように配された保護膜を形成する工程とを備えることを特徴とする。
これにより、半導体チップの側面と樹脂との間に隙間が生じた場合においても、製造工程の煩雑化を抑制しつつ、半導体チップの側面と樹脂との間の隙間を保護膜にて塞ぐことができ、フェースダウン実装された半導体チップの信頼性を向上させることができる。 In addition, according to the method for manufacturing a semiconductor device according to one aspect of the present invention, a step of face-down mounting a semiconductor chip on a carrier substrate via a resin, and an entire surface of the carrier substrate on which the semiconductor chip is face-down mounted And a step of forming a protective film disposed so as to cover the surface.
Thereby, even when a gap is formed between the side surface of the semiconductor chip and the resin, the gap between the side surface of the semiconductor chip and the resin can be blocked with a protective film while suppressing the complexity of the manufacturing process. In addition, the reliability of the semiconductor chip mounted face down can be improved.

また、本発明の一態様に係る半導体装置の製造方法によれば、樹脂を介してキャリア基板上に半導体チップをフェースダウン実装する工程と、前記キャリア基板の裏面に形成されたランドをマスク材にてマスクする工程と、前記半導体チップがフェースダウン実装されたキャリア基板上の全面および前記マスク材にてマスクされたキャリア基板の裏面を覆うように配された保護膜を形成する工程と、前記マスク材を前記キャリア基板から除去する工程と、前記ランド上に半田ボールを形成する工程とを備えることを特徴とする。
これにより、保護膜の位置決め作業を行うことなく、半導体チップの側面と樹脂との間の隙間を保護膜にて塞ぐことができ、製造工程の煩雑化を抑制しつつ、フェースダウン実装された半導体チップの信頼性を向上させることができる。 In addition, according to the method for manufacturing a semiconductor device of one embodiment of the present invention, a step of mounting a semiconductor chip face down on a carrier substrate via a resin, and a land formed on the back surface of the carrier substrate as a mask material Masking, forming a protective film so as to cover the entire surface of the carrier substrate on which the semiconductor chip is face-down mounted and the back surface of the carrier substrate masked with the mask material, and the mask Removing the material from the carrier substrate; and forming a solder ball on the land.
This allows the gap between the side surface of the semiconductor chip and the resin to be closed with the protective film without performing the positioning operation of the protective film, and the semiconductor mounted face down while suppressing the complication of the manufacturing process. The reliability of the chip can be improved.

以下、本発明の実施形態に係る半導体装置およびその製造方法について図面を参照しながら説明する。
図１は、本発明の一実施形態に係る半導体装置の製造方法を示す断面図である。 Hereinafter, a semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

図１（ａ）において、キャリア基板１には、複数の半導体チップ５ａ、５ｂを搭載する搭載領域が設けられている。そして、キャリア基板１の表面にはランド３が形成されるとともに、キャリア基板１の裏面にはランド２が形成され、キャリア基板１内には内部配線４が形成されている。また、半導体チップ５ａ、５ｂには電極パッド６ａ、６ｂがそれぞれ形成され、電極パッド６ａ、６ｂ上には突出電極７ａ、７ｂがそれぞれ形成されている。なお、キャリア基板１としては、例えば、両面基板、多層配線基板、ビルドアップ基板、テープ基板またはフィルム基板などを用いることができ、キャリア基板１の材質としては、例えば、ポリイミド樹脂、ガラスエポキシ樹脂、ＢＴレジン、アラミドとエポキシのコンポジットまたはセラミックなどを用いることができる。また、突出電極７ａ、７ｂとしては、例えば、Ａｕバンプ、半田材などで被覆されたＣｕバンプやＮｉバンプ、あるいは半田ボールなどを用いることができる。   In FIG. 1A, the carrier substrate 1 is provided with a mounting area for mounting a plurality of semiconductor chips 5a and 5b. A land 3 is formed on the front surface of the carrier substrate 1, a land 2 is formed on the back surface of the carrier substrate 1, and an internal wiring 4 is formed in the carrier substrate 1. Further, electrode pads 6a and 6b are formed on the semiconductor chips 5a and 5b, respectively, and protruding electrodes 7a and 7b are formed on the electrode pads 6a and 6b, respectively. As the carrier substrate 1, for example, a double-sided substrate, a multilayer wiring substrate, a build-up substrate, a tape substrate, or a film substrate can be used. Examples of the material of the carrier substrate 1 include polyimide resin, glass epoxy resin, BT resin, aramid and epoxy composite, ceramic, or the like can be used. Further, as the protruding electrodes 7a and 7b, for example, Au bumps, Cu bumps or Ni bumps covered with a solder material, or solder balls can be used.

そして、半導体チップ５ａ、５ｂをキャリア基板１上にフェースダウン実装する場合、キャリア基板１上に樹脂８ａ、８ｂをそれぞれ配置する。ここで、樹脂８ａ、８ｂとしては、例えば、エポキシ樹脂などの熱硬化性樹脂を用いることができる。また、キャリア基板１上に樹脂８ａ、８ｂを配置する方法としては、フィルム状の樹脂８ａ、８ｂをキャリア基板１上に貼り付けるようにしてもよいし、粘性を有する樹脂８ａ、８ｂをキャリア基板１上に塗布するようにしてもよい。   Then, when the semiconductor chips 5 a and 5 b are face-down mounted on the carrier substrate 1, the resins 8 a and 8 b are disposed on the carrier substrate 1, respectively. Here, as the resins 8a and 8b, for example, a thermosetting resin such as an epoxy resin can be used. Further, as a method of disposing the resins 8a and 8b on the carrier substrate 1, the film-like resins 8a and 8b may be attached to the carrier substrate 1, or the viscous resins 8a and 8b are used as the carrier substrate. You may make it apply | coat on 1st.

次に、図１（ｂ）に示すように、半導体チップ５ａ、５ｂとキャリア基板１との位置決めを行った後、半導体チップ５ａ、５ｂをキャリア基板１上にフェースダウン実装することにより、樹脂８ａ、８ｂにて半導体チップ５ａ、５ｂをキャリア基板１上にそれぞれ固着するとともに、突出電極７ａ、７ｂをランド３上に接合する。なお、突出電極７ａ、７ｂをランド３上に接合する場合、例えば、半田接合や合金接合などの金属接合を用いるようにしてもよく、ＡＣＦ（Ａｎｉｓｏｔｒｏｐｉｃ Ｃｏｎｄｕｃｔｉｖｅ Ｆｉｌｍ）接合、ＮＣＦ（Ｎｏｎｃｏｎｄｕｃｔｉｖｅ Ｆｉｌｍ）接合、ＡＣＰ（Ａｎｉｓｏｔｒｏｐｉｃ Ｃｏｎｄｕｃｔｉｖｅ Ｐａｓｔｅ）接合、ＮＣＰ（Ｎｏｎｃｏｎｄｕｃｔｉｖｅ Ｐａｓｔｅ）接合などの圧接接合を用いるようにしてもよい。   Next, as shown in FIG. 1B, after positioning the semiconductor chips 5a and 5b and the carrier substrate 1, the semiconductor chips 5a and 5b are mounted face-down on the carrier substrate 1 to thereby form the resin 8a. 8b, the semiconductor chips 5a and 5b are fixed to the carrier substrate 1, respectively, and the protruding electrodes 7a and 7b are bonded to the land 3. When the protruding electrodes 7a and 7b are bonded to the land 3, for example, metal bonding such as solder bonding or alloy bonding may be used. You may make it use press-contact joining, such as an ACP (Anisotropic Conductive Paste) junction and a NCP (Nonductive Paste) junction.

次に、図１（ｃ）に示すように、半導体チップ５ａ、５ｂの側面にはみ出した部分の樹脂８ａ、８ｂ全体を覆うように配された保護膜９を形成する。なお、保護膜９は、半導体チップ５ａ、５ｂがフェースダウン実装されたキャリア基板１上の全面を覆うように配してもよいし、半導体チップ５ａ、５ｂがフェースダウン実装されたキャリア基板１上の表面全体だけでなく、キャリア基板１の裏面全体を覆うように配してもよい。だだし、キャリア基板１の裏面全体を保護膜９にて覆う場合、キャリア基板１の裏面のランド３上には保護膜９が付着しないようにすることが好ましい。この場合、マスキングテープなどのマスク材でランド３上を覆ってから、保護膜９を形成することができる。また、保護膜９としては、例えば、シランカップリング剤やシランカップリング剤との混合材、ポリイミドや防水性塗料などを用いることができる。なお、シランカップリング剤との混合材としては、感光性樹脂と混合された材料を用いるようにしてもよい。また、保護膜９の形成方法としては、半導体チップ５ａ、５ｂがフェースダウン実装されたキャリア基板１上に保護膜９をローラやブラシなどで塗布する方法の他、半導体チップ５ａ、５ｂがフェースダウン実装されたキャリア基板１を保護膜９の原料となる液体の中に浸漬するようにしてもよい。   Next, as shown in FIG. 1C, a protective film 9 is formed so as to cover the entire portion of the resin 8a, 8b protruding from the side surfaces of the semiconductor chips 5a, 5b. The protective film 9 may be arranged so as to cover the entire surface of the carrier substrate 1 on which the semiconductor chips 5a and 5b are mounted face down, or on the carrier substrate 1 on which the semiconductor chips 5a and 5b are mounted face down. It may be arranged so as to cover not only the entire front surface but also the entire back surface of the carrier substrate 1. However, when the entire back surface of the carrier substrate 1 is covered with the protective film 9, it is preferable that the protective film 9 does not adhere to the land 3 on the back surface of the carrier substrate 1. In this case, the protective film 9 can be formed after the land 3 is covered with a mask material such as a masking tape. Moreover, as the protective film 9, a silane coupling agent, a mixed material with a silane coupling agent, a polyimide, a waterproof paint, etc. can be used, for example. In addition, as a mixed material with a silane coupling agent, you may make it use the material mixed with the photosensitive resin. As a method for forming the protective film 9, in addition to a method in which the protective film 9 is applied with a roller or a brush on the carrier substrate 1 on which the semiconductor chips 5a and 5b are mounted face down, the semiconductor chips 5a and 5b are face down. The mounted carrier substrate 1 may be immersed in a liquid that is a raw material for the protective film 9.

また、保護膜９の膜厚は５〜３０μｍの範囲内であることが好ましい。これにより、キャリア基板１上に保護膜９を形成した場合においても、保護膜９との熱膨張係数差に起因するキャリア基板１の反りを抑制することが可能となるとともに、熱ストレスに起因する保護膜９のクラックを防止することができる。また、保護膜９にて半導体チップ５ａ、５ｂが覆われた場合においても、半導体チップ５ａ、５ｂに形成された識別マークの視認性を確保することができる。   Moreover, it is preferable that the film thickness of the protective film 9 exists in the range of 5-30 micrometers. As a result, even when the protective film 9 is formed on the carrier substrate 1, it is possible to suppress the warpage of the carrier substrate 1 due to the difference in thermal expansion coefficient from the protective film 9, and also due to thermal stress. Cracks of the protective film 9 can be prevented. In addition, even when the semiconductor chips 5a and 5b are covered with the protective film 9, the visibility of the identification marks formed on the semiconductor chips 5a and 5b can be ensured.

次に、図１（ｄ）に示すように、キャリア基板１の裏面に設けられたランド２上に、キャリア基板１をマザー基板上に実装するための突出電極１０を形成する。なお、突出電極１０としては、例えば、Ａｕバンプ、半田材などで被覆されたＣｕバンプやＮｉバンプ、あるいは半田ボールなどを用いることができる。
次に、図１（ｅ）に示すように、突出電極１０が形成されたキャリア基板１を個々の半導体チップ５ａ、５ｂごとに切断することにより、半導体チップ５ａ、５ｂごとにキャリア基板１を分割する。 Next, as illustrated in FIG. 1D, the protruding electrode 10 for mounting the carrier substrate 1 on the mother substrate is formed on the land 2 provided on the back surface of the carrier substrate 1. As the protruding electrode 10, for example, an Au bump, a Cu bump coated with a solder material, a Ni bump, or a solder ball can be used.
Next, as shown in FIG. 1 (e), the carrier substrate 1 on which the protruding electrodes 10 are formed is cut into individual semiconductor chips 5a and 5b, whereby the carrier substrate 1 is divided into semiconductor chips 5a and 5b. To do.

これにより、半導体チップ５ａ、５ｂの側面と樹脂８ａ、８ｂとの間に隙間が生じた場合においても、半導体チップ５ａ、５ｂの側面と樹脂８ａ、８ｂとの間の隙間を保護膜９にて塞ぐことができる。このため、半導体チップ５ａ、５ｂと樹脂８ａ、８ｂとの結合性を向上させることが可能となるとともに、樹脂８ａ、８ｂが形成された半導体チップ５ａ、５ｂの側面を介して水分が浸透することを防止することが可能となり、フェースダウン実装された半導体チップ５ａ、５ｂの信頼性を向上させることができる。   Thus, even when a gap is generated between the side surfaces of the semiconductor chips 5a and 5b and the resins 8a and 8b, the gap between the side surfaces of the semiconductor chips 5a and 5b and the resins 8a and 8b is formed by the protective film 9. Can be closed. For this reason, it becomes possible to improve the bonding between the semiconductor chips 5a and 5b and the resins 8a and 8b, and that moisture permeates through the side surfaces of the semiconductor chips 5a and 5b on which the resins 8a and 8b are formed. Can be prevented, and the reliability of the semiconductor chips 5a and 5b mounted face-down can be improved.

本発明の一実施形態に係る半導体装置の製造方法を示す断面図。Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention.

符号の説明Explanation of symbols

１ キャリア基板、２、３ ランド、４ 内部配線、５ａ、５ｂ 半導体チップ、６ａ、６ｂ 電極パッド、７ａ、７ｂ、１０ 突出電極、８ａ、８ｂ 樹脂、９ 保護膜   DESCRIPTION OF SYMBOLS 1 Carrier substrate, 2, 3 land, 4 Internal wiring, 5a, 5b Semiconductor chip, 6a, 6b Electrode pad, 7a, 7b, 10 Protruding electrode, 8a, 8b Resin, 9 Protective film

Claims (7)

電極パッドが形成された半導体チップと、
前記電極パッド上に配置された突出電極を介して前記半導体チップがフェースダウン実装されたキャリア基板と、
前記半導体チップと前記キャリア基板との間に充填された樹脂と、
前記半導体チップの側面にはみ出した部分の前記樹脂全体を覆うように配された保護膜とを備えることを特徴とする半導体装置。 A semiconductor chip on which electrode pads are formed;
A carrier substrate on which the semiconductor chip is mounted face down via protruding electrodes disposed on the electrode pads;
A resin filled between the semiconductor chip and the carrier substrate;
A semiconductor device comprising: a protective film disposed so as to cover the entire portion of the resin protruding from a side surface of the semiconductor chip. 電極パッドが形成された半導体チップと、
前記電極パッド上に配置された突出電極を介して前記半導体チップがフェースダウン実装されたキャリア基板と、
前記半導体チップと前記キャリア基板との間に充填された樹脂と、
前記樹脂が充填された前記キャリア基板の全面を覆うように配された保護膜とを備えることを特徴とする半導体装置。 A semiconductor chip on which electrode pads are formed;
A carrier substrate on which the semiconductor chip is mounted face down via protruding electrodes disposed on the electrode pads;
A resin filled between the semiconductor chip and the carrier substrate;
And a protective film disposed to cover the entire surface of the carrier substrate filled with the resin. 電極パッドが形成された半導体チップと、
前記電極パッド上に配置された突出電極を介して前記半導体チップがフェースダウン実装されたキャリア基板と、
前記半導体チップと前記キャリア基板との間に充填された樹脂と、
前記樹脂が充填された前記キャリア基板の全面および裏面を覆うように配された保護膜とを備えることを特徴とする半導体装置。 A semiconductor chip on which electrode pads are formed;
A carrier substrate on which the semiconductor chip is mounted face-down through a protruding electrode disposed on the electrode pad;
A resin filled between the semiconductor chip and the carrier substrate;
A semiconductor device comprising: a protective film disposed so as to cover an entire surface and a back surface of the carrier substrate filled with the resin. 前記保護膜の膜厚は５〜３０μｍの範囲内であることを特徴とする請求項１から３のいずれか１項記載の半導体装置。   4. The semiconductor device according to claim 1, wherein a thickness of the protective film is in a range of 5 to 30 μm. 樹脂を介してキャリア基板上に半導体チップをフェースダウン実装する工程と、
前記半導体チップの側面にはみ出した部分の前記樹脂全体が覆われるように配された保護膜を形成する工程とを備えることを特徴とする半導体装置の製造方法。 Mounting a semiconductor chip face down on a carrier substrate via resin;
Forming a protective film disposed so as to cover the entire portion of the resin protruding from the side surface of the semiconductor chip. 樹脂を介してキャリア基板上に半導体チップをフェースダウン実装する工程と、
前記半導体チップがフェースダウン実装されたキャリア基板上の全面を覆うように配された保護膜を形成する工程とを備えることを特徴とする半導体装置の製造方法。 Mounting a semiconductor chip face down on a carrier substrate via resin;
Forming a protective film arranged to cover the entire surface of the carrier substrate on which the semiconductor chip is face-down mounted. 樹脂を介してキャリア基板上に半導体チップをフェースダウン実装する工程と、
前記キャリア基板の裏面に形成されたランドをマスク材にてマスクする工程と、
前記半導体チップがフェースダウン実装されたキャリア基板上の全面および前記マスク材にてマスクされたキャリア基板の裏面を覆うように配された保護膜を形成する工程と、
前記マスク材を前記キャリア基板から除去する工程と、
前記ランド上に半田ボールを形成する工程とを備えることを特徴とする半導体装置の製造方法。 Mounting a semiconductor chip face down on a carrier substrate via resin;
Masking the lands formed on the back surface of the carrier substrate with a mask material;
Forming a protective film disposed so as to cover the entire surface of the carrier substrate on which the semiconductor chip is face-down mounted and the back surface of the carrier substrate masked with the mask material;
Removing the mask material from the carrier substrate;
Forming a solder ball on the land. A method for manufacturing a semiconductor device, comprising:
JP2006046460A 2006-02-23 2006-02-23 Semiconductor device and method of manufacturing semiconductor device Withdrawn JP2007227609A (en)

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