JPH1197574A - Electronic parts with bump - Google Patents

Electronic parts with bump

Info

Publication number
JPH1197574A
JPH1197574A JP25556897A JP25556897A JPH1197574A JP H1197574 A JPH1197574 A JP H1197574A JP 25556897 A JP25556897 A JP 25556897A JP 25556897 A JP25556897 A JP 25556897A JP H1197574 A JPH1197574 A JP H1197574A
Authority
JP
Japan
Prior art keywords
electrode
electrodes
solder
outermost
electronic component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP25556897A
Other languages
Japanese (ja)
Other versions
JP3262040B2 (en
Inventor
Kenji Kondo
賢司 近藤
Masayuki Aoyama
雅之 青山
Koji Kondo
宏司 近藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP25556897A priority Critical patent/JP3262040B2/en
Priority to US09/121,303 priority patent/US6303878B1/en
Publication of JPH1197574A publication Critical patent/JPH1197574A/en
Priority to US09/858,500 priority patent/US6548765B2/en
Application granted granted Critical
Publication of JP3262040B2 publication Critical patent/JP3262040B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks

Landscapes

  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a package structure which can prevent a contact failure by preventing a solder bump from being stripped out of the electrode on the backside of a BGA package even if an external shock is applied thereto. SOLUTION: In an outermost electrode 11a at the outer periphery of a plurality of electrodes 11 arranged in an array on the backside of an interposer 3, its contact part with a solder bump 8 ends at the outermost periphery thereof. To be specific, the outermost electrode 11a is not covered with solder resist 13. In this arrangement, the solder bump 8 is bonded not only to the surface of the outermost electrode 11a but also to the end of the outermost periphery, and hence the solder bump 8 is bonded more strongly than it ends in the electrodes. This can prevent the solder bump 9 from being stripped out of the outermost electrode 11a by an external impact and hence prevent a contact failure.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、電子部品の裏面に
アレイ状に配置されたはんだバンプによって、電子部品
と実装基板との電気的接続を行うバンプを有する電子部
品に関し、特に携帯機器に用いる電子部品に適用して好
適である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic component having a bump for electrically connecting an electronic component and a mounting board by solder bumps arranged in an array on the back surface of the electronic component, and more particularly to a portable device. It is suitable for application to electronic components.

【０００２】[0002]

【従来の技術】従来におけるボールグリッドアレイ（以
下、ＢＧＡという）パッケージ１０１の模式的断面図を
図３に示す。ＢＧＡパッケージ１０１とは、回路配線１
０２を有するインターポーザ１０３に接着剤１０４等を
介して半導体チップ１０５を搭載し、回路配線１０２に
接続された電極１０２ａと半導体チップ１０５とをＡｕ
ワイヤ１０６等で電気的に接続したのち、封止樹脂１０
７で半導体チップ１０５及びＡｕワイヤ１０６を封止し
たものである。2. Description of the Related Art FIG. 3 is a schematic sectional view of a conventional ball grid array (BGA) package 101. As shown in FIG. The BGA package 101 is a circuit wiring 1
The semiconductor chip 105 is mounted on the interposer 103 having the semiconductor chip 105 via the adhesive 104 or the like, and the electrode 102a connected to the circuit wiring 102 and the semiconductor chip 105 are Au.
After being electrically connected by the wire 106 or the like, the sealing resin 10
7, the semiconductor chip 105 and the Au wire 106 are sealed.

【０００３】ＢＧＡパッケージ１０１の裏面となるイン
ターポーザ１０３には、回路配線１０２と電気的に接続
された電極（パッド）１０８が形成されている。ＢＧＡ
パッケージ１０１の裏面の模式図を図４に示す。この図
に示すように、電極１０８はアレイ状の配列を成して形
成されている。そして、この電極１０８のそれぞれにハ
ンダボールを溶融接合してアレイ状の配列を成すはんだ
バンプ１０９を形成し、このはんだバンプ１０９によっ
て実装基板への実装を行っている。An electrode (pad) 108 electrically connected to the circuit wiring 102 is formed on the interposer 103 on the back surface of the BGA package 101. BGA
FIG. 4 is a schematic diagram of the back surface of the package 101. As shown in this figure, the electrodes 108 are formed in an array. Then, solder balls are melt-bonded to each of the electrodes 108 to form solder bumps 109 in an array, and the solder bumps 109 are used for mounting on a mounting board.

【０００４】このはんだバンプ１０９の形成に際し、実
装工程における実装性を確保するべく、はんだバンプ１
０９の高さや位置を揃えている。具体的には、所定の開
口パターンのソルダレジスト１１０を印刷して、引き出
し配線及び電極１０８の外周部を覆い、電極１０８の所
定部分だけを露出させることによって、はんだバンプ１
０９の形成位置を揃えると共に、はんだバンプ１０９の
高さを揃えている。When forming the solder bumps 109, the solder bumps 1 are formed in order to secure the mountability in the mounting process.
09 are aligned in height and position. More specifically, a solder resist 110 having a predetermined opening pattern is printed to cover the outer peripheral portions of the lead-out wiring and the electrode 108, and only a predetermined portion of the electrode 108 is exposed.
09 are aligned, and the height of the solder bumps 109 is also adjusted.

【０００５】[0005]

【発明が解決しようとする課題】ＢＧＡパッケージ１０
１や実装基板に外部衝撃が加わった場合、特に実装基板
が曲がりやすい樹脂等からなる場合には、アレイ状に配
置された複数のはんだバンプ１０９のうち最外周に位置
するものが接合されている電極（以下、最外周電極とい
う）１０８ａの部分に応力集中が起こるため、最外周電
極１０８ａとはんだバンプ１０９との接合部分ではこの
応力集中に耐えうる接合強度が要求される。SUMMARY OF THE INVENTION BGA Package 10
When an external impact is applied to the mounting board 1 or the mounting board, particularly when the mounting board is made of a resin or the like that is easily bent, the solder bump 109 located at the outermost periphery among the plurality of solder bumps 109 arranged in an array is joined. Since stress concentration occurs in the portion of the electrode (hereinafter, referred to as the outermost peripheral electrode) 108a, a bonding strength between the outermost peripheral electrode 108a and the solder bump 109 that can withstand this stress concentration is required.

【０００６】しかしながら、従来におけるＢＧＡパッケ
ージ１０１においては、はんだバンプ１０９が電極１０
８の内部で終端するため、はんだバンプ１０９と電極１
０８の接合が弱くなってしまい、外部衝撃によって最外
周電極１０８ａからはんだバンプ１０９が剥離（クラッ
ク）して、接触不良が発生するという問題がある。本発
明は上記点に鑑みてなされたもので、外部衝撃によって
も電子部品の裏面に備えられた電極からはんだバンプが
剥離することを防止することにより、接触不良を防止で
きるバンプを有する電子部品を提供することを目的とす
る。However, in the conventional BGA package 101, the solder bump 109 is
8, the solder bump 109 and the electrode 1
08 is weakened, and the external impact causes the solder bump 109 to peel (crack) from the outermost peripheral electrode 108a, resulting in a problem of poor contact. The present invention has been made in view of the above points, and an electronic component having a bump that can prevent a contact failure by preventing a solder bump from peeling off from an electrode provided on a back surface of the electronic component even by an external impact. The purpose is to provide.

【０００７】[0007]

【課題を解決するための手段】本発明は上記目的を達成
するため、以下の技術的手段を採用する。請求項１乃至
３に記載の発明においては、インターポーザ（３）の裏
面側にアレイ状に配列された複数の電極（１１）のう
ち、外周部分に位置する最外周電極（１１ａ）において
は、はんだバンプ（８）との接合部分が全て最外周電極
（１１ａ）の外周部で終端するようになっていることを
特徴としている。In order to achieve the above object, the present invention employs the following technical means. According to the first to third aspects of the present invention, of the plurality of electrodes (11) arranged in an array on the back side of the interposer (3), the outermost peripheral electrode (11a) located at the outer peripheral portion has a solder. It is characterized in that all the joints with the bumps (8) end at the outer peripheral portion of the outermost peripheral electrode (11a).

【０００８】このように、はんだバンプ（８）の接合部
分全てが最外周電極（１１ａ）の外周部で終端するよう
にすれば、すなわち最外周電極（１１ａ）においてはイ
ンターポーザ（３）の表面から露出するような引き出し
線を設けないようにすれば、最外周電極（１１ａ）の表
面だけでなく端面の部分においてもはんだバンプ（８）
が接合するため、最外周電極（１１ａ）とはんだバンプ
（８）との接合が弱い部分がなくなる。従って、外部衝
撃によっても最外周電極（１１ａ）からはんだバンプ
（８）が剥離しにくくなる。これにより、電子部品
（１）と実装基板との接触不良を防止することができ
る。As described above, if all the joining portions of the solder bumps (8) are terminated at the outer peripheral portion of the outermost peripheral electrode (11a), that is, at the outermost peripheral electrode (11a) from the surface of the interposer (3). If the lead wire is not provided so as to be exposed, the solder bump (8) can be formed not only on the surface of the outermost peripheral electrode (11a) but also on the end face.
Are bonded, so that there is no portion where the bonding between the outermost peripheral electrode (11a) and the solder bump (8) is weak. Therefore, the solder bumps (8) hardly peel off from the outermost peripheral electrode (11a) even by an external impact. Thereby, the contact failure between the electronic component (1) and the mounting board can be prevented.

【０００９】なお、最外周電極（１１ａ）の内側の内周
電極（１１ｂ）においては、インターポーザ（３）の表
面から露出するような引き出し配線（２ｂ）を設けるよ
うにしてもよい。すなわち、配線保護用のソルダレジス
ト（１３）で引き出し配線（２ｂ）及び内周電極（１１
ｂ）の外周部分を覆うようにすればはんだバンプ（８）
の高さや位置を揃えることができるからであり、また最
外周電極（１１ａ）が剥離しなければ最外周電極（１１
ａ）より内側にある内周電極（１１ｂ）が剥離すること
がないからである。[0009] In the inner electrode (11b) inside the outermost electrode (11a), a lead-out wiring (2b) exposed from the surface of the interposer (3) may be provided. That is, the lead-out wiring (2b) and the inner peripheral electrode (11) are formed by the solder resist (13) for protecting the wiring.
If the outer peripheral portion of b) is covered, the solder bump (8)
This is because the heights and positions of the outermost peripheral electrodes (11a) can be adjusted if the outermost peripheral electrodes (11a) are not peeled off.
This is because the inner peripheral electrode (11b) located inside from a) does not peel off.

【００１０】請求項３に記載の発明のように、インター
ポーザ（３）として多層配線基板を用いて、多層配線基
板に内蔵された配線層（８）を最外周電極（１１ａ）の
引き出し配線とすれば、ダミー電極ではない通常の電極
によって請求項１に示すような構造で最外周電極（１１
ａ）を構成することができる。請求項４に記載の発明に
おいては、前記電子部品は、携帯機器に搭載されるもの
であることを特徴としている。According to a third aspect of the present invention, a multi-layer wiring board is used as the interposer (3), and the wiring layer (8) built in the multi-layer wiring board is used as a lead wiring for the outermost peripheral electrode (11a). For example, the outermost peripheral electrode (11) is formed by a normal electrode which is not a dummy electrode in the structure as shown in claim 1.
a) can be configured. According to a fourth aspect of the present invention, the electronic component is mounted on a portable device.

【００１１】携帯機器においては、落下等による外部衝
撃を受けやすく、電子部品（１）と実装基板との接触不
良が発生し易い。このため、請求項１乃至２に記載の発
明を携帯機器に適用すると効果的である。なお、上記各
手段の括弧内の符号は、後述する実施形態記載の具体的
手段との対応関係を示すものである。In a portable device, an external impact due to a drop or the like is easily received, and a poor contact between the electronic component (1) and the mounting board is apt to occur. Therefore, it is effective to apply the invention according to claims 1 and 2 to a portable device. In addition, the code | symbol in the parenthesis of each said means shows the correspondence with the concrete means of embodiment mentioned later.

【００１２】[0012]

【発明の実施の形態】以下、本発明の実施の形態を図に
基づいて説明する。図１に、はんだバンプを備えたＢＧ
Ａパッケージ１の断面図を示す。ＢＧＡパッケージ１
は、回路配線２を有するインターポーザ３と、このイン
ターポーザ３上に接着剤４等を介して搭載された半導体
チップ５と、回路配線２と半導体チップ５とを電気的に
接続するＡｕワイヤ６と、半導体チップ５及びＡｕワイ
ヤ６を封止するエポキシ樹脂等の封止樹脂７とによって
構成されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. Figure 1 shows a BG with solder bumps.
1 shows a sectional view of an A package 1. FIG. BGA package 1
A semiconductor chip 5 mounted on the interposer 3 via an adhesive 4 and the like; an Au wire 6 for electrically connecting the circuit wiring 2 to the semiconductor chip 5; It is composed of a semiconductor chip 5 and a sealing resin 7 such as an epoxy resin for sealing the Au wire 6.

【００１３】このＢＧＡパッケージ１の裏面に相当する
インターポーザ３には、コア材３ａを介して多数の配線
層９を積層形成することで回路配線２を構成する多層配
線基板が用いられている。インターポーザ３の両面のう
ち半導体チップ５が搭載される側には、半導体チップ５
に備えられた複数の電極に接続される電極１０が形成さ
れており、インターポーザ３の両面のうちＢＧＡパッケ
ージ１の裏面となる側には、はんだバンプと接続される
複数の電極１１が形成されている。これらインターポー
ザ３の両側に形成された電極１０と電極１１が回路配線
２によって電気的に接続されている。As the interposer 3 corresponding to the back surface of the BGA package 1, a multi-layer wiring board is used which constitutes the circuit wiring 2 by laminating a large number of wiring layers 9 via a core material 3a. The semiconductor chip 5 is mounted on the side of the interposer 3 on which the semiconductor chip 5 is mounted.
The electrodes 10 connected to the plurality of electrodes provided on the BGA package 1 are formed on both sides of the interposer 3 on the side of the back surface of the BGA package 1. I have. The electrodes 10 and 11 formed on both sides of the interposer 3 are electrically connected by the circuit wiring 2.

【００１４】インターポーザ３の両面は、電極１０や電
極１１の部分が開口したソルダレジスト１３、１４で覆
われており、インターポーザ３の両表面に形成された配
線の保護が成されている。インターポーザ３の両面のう
ちＢＧＡパッケージ１の裏面となる側においては、ソル
ダレジスト１３は、はんだバンプ８の高さや位置を揃え
る役割も果たしている。ここで、ＢＧＡパッケージ１の
裏面となるインターポーザ３の一面を表す模式図を図２
に示し、ソルダレジスト１３の詳細について説明する。
なお、図中の斜線部がソルダレジスト１３を表してい
る。Both surfaces of the interposer 3 are covered with solder resists 13 and 14 having openings in the electrodes 10 and 11 to protect the wiring formed on both surfaces of the interposer 3. On the back surface of the BGA package 1 on both sides of the interposer 3, the solder resist 13 also plays the role of aligning the height and position of the solder bumps 8. FIG. 2 is a schematic diagram showing one surface of the interposer 3 serving as the back surface of the BGA package 1.
And the details of the solder resist 13 will be described.
The hatched portions in the figure represent the solder resist 13.

【００１５】ＢＧＡパッケージ１の裏面に形成された電
極１１は、円形状を成しており、アレイ状の配列パター
ンで配置されている。このような配列パターンを成す電
極１１のうち、最外周電極１１ａ（図２中の領域Ｘにお
ける電極１１）は、引き出し配線が埋め込み形成されて
いて電極部しかコア材３ａから露出しないような独立パ
ッドとなっており、最外周電極１１ａの内側の内周電極
１１ｂ（図２中の領域Ｙにおける電極１１）において
は、引き出し配線２ａがコア材３ａから露出するパッド
となっている。The electrodes 11 formed on the back surface of the BGA package 1 have a circular shape and are arranged in an array pattern. Of the electrodes 11 having such an arrangement pattern, the outermost peripheral electrode 11a (the electrode 11 in the region X in FIG. 2) is an independent pad in which a lead wire is buried and only the electrode portion is exposed from the core material 3a. In the inner electrode 11b (the electrode 11 in the region Y in FIG. 2) inside the outermost electrode 11a, the lead wiring 2a is a pad exposed from the core material 3a.

【００１６】ソルダレジスト１３の開口パターンは、電
極１１の配列パターンと同様にアレイ状のものとなって
いる。そして、最外周電極１１ａにおいては、ソルダレ
ジスト１３によって最外周電極１１ａが覆われないよう
になっており、内周電極１１ｂにおいては、ソルダレジ
スト１３によって内周電極１１ｂの外周部が覆われるよ
うになっている。The opening pattern of the solder resist 13 is in the form of an array similarly to the arrangement pattern of the electrodes 11. In the outermost electrode 11a, the outermost electrode 11a is not covered by the solder resist 13, and in the inner electrode 11b, the outer periphery of the inner electrode 11b is covered by the solder resist 13. Has become.

【００１７】一般的に、所定の径を有する開口部をソル
ダレジストに設けて、この開口部の所で電極とはんだバ
ンプとが接合するようにして、はんだバンプの高さや位
置を揃える。すなわち、はんだバンプは、電極や配線等
の金属部と接合するため、電極からの引き出し配線等と
はんだバンプが接合すると、アレイ状の配置から位置ズ
レしたり、高さが揃わなかったりしてしまうが、ソルダ
レジストで配線部分を覆うことによって、はんだバンプ
が電極のみと接合して、はんだバンプ８の高さや位置が
揃うからである。しかしながら、このソルダレジスト
は、印刷手法によって形成されるため、印刷ズレが発生
し、配線部分のみを確実に覆うことができない。このた
め、電極の外周も覆うようにすることで確実に配線部分
を覆うようにしているのである。Generally, an opening having a predetermined diameter is provided in the solder resist, and the height and position of the solder bump are aligned such that the electrode and the solder bump are joined at the opening. That is, since the solder bump is bonded to a metal part such as an electrode or a wiring, when the wiring drawn from the electrode or the like and the solder bump are bonded, the solder bump is displaced from the array-like arrangement or the height is not uniform. This is because, by covering the wiring portion with the solder resist, the solder bumps are joined only to the electrodes, and the heights and positions of the solder bumps 8 are aligned. However, since this solder resist is formed by a printing method, printing deviation occurs, and it is impossible to reliably cover only the wiring portion. For this reason, by covering the outer periphery of the electrode, the wiring portion is surely covered.

【００１８】従って、引き出し配線２ａがコア材３ａか
ら露出している内周電極１１ｂに関しては、外周部をソ
ルダレジスト１３で覆うようにすることによって、引き
出し配線２ａを完全に覆うようにしている。一方、本実
施形態においては、最外周電極１１ａを独立パッドとし
て、コア材３ａから引き出し配線が露出しないようにし
ているため、外周部をソルダレジスト１３で覆う必要が
ない。このため、最外周電極１１ａに関しては、ソルダ
レジスト１３で覆わないように、ソルダレジスト１３の
開口部１３ａの径を最外周電極１１ａの径よりも大きく
して、電極部が完全に露出するようにしている。Accordingly, the outer peripheral portion of the inner peripheral electrode 11b where the lead wiring 2a is exposed from the core material 3a is covered with the solder resist 13, so that the lead wiring 2a is completely covered. On the other hand, in the present embodiment, since the outermost peripheral electrode 11a is used as an independent pad so that the lead-out wiring is not exposed from the core material 3a, it is not necessary to cover the outer peripheral portion with the solder resist 13. For this reason, the diameter of the opening 13a of the solder resist 13 is made larger than the diameter of the outermost electrode 11a so that the outermost electrode 11a is not covered with the solder resist 13, so that the electrode portion is completely exposed. ing.

【００１９】なお、最外周電極１１ａと内周電極１１ｂ
におけるはんだバンプ８が接合する部分の面積を同等に
することにより、はんだバンプ８の高さや位置を一定に
するため、最外周電極１１ａの径と内周電極１１ｂに位
置するソルダレジスト１３の開口部１３ｂの径を同等に
している。このように構成されたＢＧＡパッケージ１の
裏面に形成された電極１１のそれぞれに、はんだボール
を溶融接合することによって、図１に示すようなはんだ
バンプを備えたＢＧＡパッケージ１が完成する。The outermost electrode 11a and the inner electrode 11b
In order to make the height and the position of the solder bump 8 constant by equalizing the area of the portion where the solder bump 8 is joined in the above, the diameter of the outermost electrode 11a and the opening of the solder resist 13 located at the inner electrode 11b 13b have the same diameter. The BGA package 1 having the solder bumps as shown in FIG. 1 is completed by melting and bonding the solder balls to each of the electrodes 11 formed on the back surface of the BGA package 1 configured as described above.

【００２０】以下、インターポーザ３の製造方法につい
て説明する。なお、簡略化のため、４層からなるインタ
ーポーザ３について説明する。まず、両面に銅箔処理が
成されたコア材３ａを用意し、所定の位置にドリルで穴
を空けてスルーホール（ブラインドビアホール）３ｂを
形成する。そして、このスルーホール３ｂを通じて、コ
ア材３ａの両面における銅を電気的に導通させるべく、
銅メッキによるスルーホールメッキを行う。これによ
り、スルーホールメッキ処理が施された基板が完成す
る。Hereinafter, a method of manufacturing the interposer 3 will be described. Note that, for simplification, an interposer 3 having four layers will be described. First, a core material 3a having both surfaces subjected to copper foil treatment is prepared, and a through hole (blind via hole) 3b is formed by drilling a hole at a predetermined position. Then, in order to electrically conduct copper on both surfaces of the core material 3a through the through holes 3b,
Perform through-hole plating by copper plating. As a result, a substrate subjected to through-hole plating is completed.

【００２１】次に、このようなスルーホールメッキ処理
が施された基板を２枚用意し、この２枚の基板のうち、
後に張り合わせる側同士の面の銅箔をエッチングによっ
てパターニングする。そして、ガラスクロスにエポキシ
樹脂を含有させたプリプレグを２枚の基板間に挟み込ん
だ状態で加熱プレス処理を行い、２枚の基板を張り合わ
せる。これにより、４層に分かれた銅箔の層が形成され
る。Next, two substrates subjected to such a through-hole plating process are prepared, and out of the two substrates,
The copper foil on the surfaces to be bonded later is patterned by etching. Then, a heat press process is performed with the prepreg containing the epoxy resin contained in the glass cloth sandwiched between the two substrates, and the two substrates are bonded to each other. Thus, a copper foil layer divided into four layers is formed.

【００２２】そして、４層分全てを貫通するようにドリ
ルで穴を空けてスルーホール（貫通バイアホール）３ｃ
を形成し、銅メッキによるスルーホールメッキを行って
４層に分かれた銅箔が電気的に導通するようにする。こ
の後、張り合わせた基板の両面における銅箔をエッチン
グによってパターニングし、電極部分の銅箔を残すと共
に所定の引き出し配線２ａを形成する。但し、このエッ
チングで形成する引き出し配線２ａは、最外周電極１１
ａに対応するスルーホール３ｃ以外からの引き出された
ものであり、最外周電極１１ａに対応するスルーホール
３ｃからの引き出し配線は、コア材３ａの表面に該当す
る銅箔によっては形成していない。Then, a hole is made by drilling so as to penetrate all the four layers, and a through hole (through via hole) 3c is formed.
Is formed and through-hole plating is performed by copper plating so that the copper foil divided into four layers is electrically connected. Thereafter, the copper foil on both surfaces of the bonded substrate is patterned by etching, leaving the copper foil of the electrode portion and forming a predetermined lead wiring 2a. However, the lead wiring 2a formed by this etching is the outermost peripheral electrode 11
The wiring is drawn out of the through hole 3c corresponding to the outermost peripheral electrode 11a, and is not formed by the copper foil corresponding to the surface of the core material 3a.

【００２３】さらに、基板に樹脂を印刷塗布することに
よって、スルーホール３ｃ内を樹脂埋めすることによっ
て、基板に形成された穴をなくす。この後、引き出し配
線２ａ等を保護するために、ソルダレジスト１３を印刷
形成して、ソルダレジスト１３にて引き出し配線２ａ等
を覆う。このとき、印刷ズレによって、最外周電極１１
ａがソルダレジスト１３に覆われないように、ソルダレ
ジスト１３の開口部１３ａは印刷ズレを考慮した大きさ
になっている。Further, the through holes 3c are filled with resin by printing and applying a resin to the substrate, thereby eliminating holes formed in the substrate. Thereafter, in order to protect the lead wiring 2a and the like, the solder resist 13 is printed and formed, and the lead wiring 2a and the like are covered with the solder resist 13. At this time, the outermost peripheral electrode 11
The opening 13a of the solder resist 13 is sized in consideration of printing deviation so that a is not covered with the solder resist 13.

【００２４】なお、この後、必要に応じて無電解メッキ
法により、電極１１上にニッケル−金（Ｎｉ−Ａｕ）メ
ッキを施したり、錫（Ｓｎ）メッキやパラジウム（Ｐ
ｄ）メッキを施す等して、複数の配線層９を備えたイン
ターポーザ３が完成する。但し、ニッケル−金メッキ等
を施さない銅のままの状態の方が、はんだバンプ８と電
極１１との接合界面が延性金属となり、はんだバンプ８
との接合が強くなるため好ましい。After this, if necessary, nickel-gold (Ni-Au) plating, tin (Sn) plating or palladium (P) plating is performed on the electrode 11 by electroless plating.
d) By performing plating or the like, the interposer 3 including the plurality of wiring layers 9 is completed. However, in a state where copper is not subjected to nickel-gold plating or the like, the bonding interface between the solder bump 8 and the electrode 11 becomes ductile metal, and the solder bump 8
It is preferable because the bonding with the metal is strengthened.

【００２５】このように完成されたインターポーザ３上
に接着材を介して半導体チップ５を搭載したのち、半導
体チップ５に備えられた電極とインターポーザ３の電極
１０とをＡｕワイヤ６でボンディングを行い、さらに半
導体チップ５とＡｕワイヤ６を封止樹脂７で封入するこ
とによってＢＧＡパッケージ１が完成する。この後、Ｂ
ＧＡパッケージ１の裏面にはんだボールを溶融接合する
ことで、はんだバンプ８が付いたＢＧＡパッケージ１が
完成する。After the semiconductor chip 5 is mounted on the completed interposer 3 via an adhesive, the electrodes provided on the semiconductor chip 5 and the electrodes 10 of the interposer 3 are bonded with Au wires 6. Furthermore, the BGA package 1 is completed by encapsulating the semiconductor chip 5 and the Au wires 6 with a sealing resin 7. After this, B
The BGA package 1 with the solder bumps 8 is completed by melting and joining the solder balls to the back surface of the GA package 1.

【００２６】なお、このように完成したはんだバンプ８
が付いたＢＧＡパッケージ１を実装基板上に位置決め搭
載したのち、はんだバンプ８を溶融することでＢＧＡパ
ッケージ１が実装基板に実装される。この実装基板を介
して外部との接続を行っている。ここで、本実施形態に
いては、上述したように、最外周電極１１ａにおいて
は、引き出し配線が埋め込み形成された独立パッドとな
っていて、かつソルダレジスト１３で覆われておらず、
最外周電極１１ａが全て露出するようにするようなって
いる。The solder bumps 8 thus completed
After the BGA package 1 marked with is positioned and mounted on the mounting board, the BGA package 1 is mounted on the mounting board by melting the solder bumps 8. Connection to the outside is made via this mounting board. Here, in the present embodiment, as described above, the outermost peripheral electrode 11a is an independent pad in which a lead-out wiring is embedded and formed, and is not covered with the solder resist 13,
The outermost peripheral electrodes 11a are all exposed.

【００２７】このため、最外周電極１１ａの外周部の端
部ではんだバンプ８の接合が終端し、接合が強くなる。
すなわち、最外周電極１１ａの部分ではんだバンプ８は
最外周電極１１ａの表面だけでなく、その側面（図１中
の断面図に示される台形上の最外周電極１１ａの斜め部
分）においても接合するようになるため、電極の内部で
はんだバンプ８の接合が終端する場合のように、電極の
表面でのみ接合している場合に比してはんだバンプ８と
最外周電極１１ａとの接合が強くなる。For this reason, the joining of the solder bumps 8 is terminated at the end of the outer peripheral portion of the outermost peripheral electrode 11a, and the joining is strengthened.
That is, the solder bump 8 is bonded not only on the surface of the outermost electrode 11a but also on the side surface (the oblique portion of the outermost electrode 11a on the trapezoid shown in the cross-sectional view in FIG. 1) at the outermost electrode 11a. Therefore, the bonding between the solder bump 8 and the outermost peripheral electrode 11a is stronger than when the bonding is performed only on the surface of the electrode, such as when the bonding of the solder bump 8 is terminated inside the electrode. .

【００２８】従って、はんだバンプ８を介してＢＧＡパ
ッケージ１を実装基板に備えた場合に、外部衝撃による
応力集中によって、はんだバンプ８が最外周電極１１ａ
から剥離することがなく、ＢＧＡパッケージ１と実装基
板との接触不良を防止することができる。また、最外周
電極１１ａにおいては上述したように応力集中が発生す
るため、この応力集中によってコア部材に亀裂が発生す
る場合があるが、上記実施形態のように最外周電極１１
ａにおける引き出し配線をスルーホールメッキによって
形成すれば、亀裂がこのスルーホールメッキ部分で止ま
るため、亀裂によって最外周電極１１ａ全体が剥がれる
ことを防止することができるという効果を得ることがで
きる。Therefore, when the BGA package 1 is provided on the mounting board via the solder bumps 8, the solder bumps 8 are concentrated on the outermost peripheral electrodes 11a due to stress concentration due to external impact.
Therefore, it is possible to prevent the BGA package 1 from being in poor contact with the mounting substrate without peeling off from the mounting board. Further, since stress concentration occurs in the outermost peripheral electrode 11a as described above, the stress concentration may cause a crack in the core member.
If the lead wiring in a is formed by through-hole plating, the crack stops at this through-hole plated portion, so that the effect of preventing the entire outermost peripheral electrode 11a from being peeled off by the crack can be obtained.

【００２９】なお、本実施形態においては、最外周電極
１１ａの引き出し配線をインターポーザ３の内部に形成
することによって最外周電極１１ａを独立パッドにして
いるが、最外周電極１１ａをＢＧＡパッケージ１内の半
導体チップ５と電気的導通を取らないようなダミー電極
として、このダミー電極によって外部衝撃による応力集
中から発生するＢＧＡパッケージ１と実装基板との接触
不良を防止するようにすることもできる。但し、この場
合には、ダミー電極を形成するスペースが必要になるた
めＢＧＡパッケージ１及び多層プリント配線基板３が全
体的に大きくなるため、上記実施形態の方法が有効であ
る。In the present embodiment, the outermost peripheral electrode 11a is formed as an independent pad by forming a lead-out wiring for the outermost peripheral electrode 11a inside the interposer 3. However, the outermost peripheral electrode 11a is formed inside the BGA package 1. As a dummy electrode that does not establish electrical conduction with the semiconductor chip 5, the dummy electrode can also prevent a contact failure between the BGA package 1 and the mounting board, which is caused by stress concentration due to an external impact. However, in this case, a space for forming a dummy electrode is required, so that the size of the BGA package 1 and the multilayer printed wiring board 3 are increased as a whole, so that the method of the above embodiment is effective.

【００３０】また、上述したように、外部衝撃によって
最外周電極１１ａからはんだバンプ８が剥離するのは、
最外周電極１１ａの内部においてはんだバンプ８の接合
が終端しているためであるが、外部衝撃による応力集中
が特にかかるのは、最外周電極１１ａのうち、隣接する
最外周電極１１ａの中心同士を結んだときにできる多角
形の外側の部分である。従って、この部分においてはん
だバンプ８の接合が最外周電極１１ａの外周部の端部で
終端していればよいと考えられるため、最外周電極１１
ａを独立パッドとする必要がないともいえる。しかしな
がら、露出した引き出し配線にもはんだバンプ８が接合
してしまうため、はんだバンプ８の位置ズレ及び変形が
発生する。このため、実装時にマウンターにてＢＧＡパ
ッケージ１を認識する際はんだバンプ８の位置ズレ及び
変形により照射光が乱反射してしまい、ＢＧＡパッケー
ジ１の認識が難しくなるため、最外周電極１１ａを独立
パッドとする必要がある。As described above, the peeling of the solder bump 8 from the outermost peripheral electrode 11a due to the external impact is caused by
This is because the bonding of the solder bumps 8 is terminated inside the outermost peripheral electrode 11a. The reason why stress concentration due to an external impact is particularly applied is that the centers of the adjacent outermost peripheral electrodes 11a among the outermost peripheral electrodes 11a are connected to each other. It is the outer part of the polygon formed when tied. Therefore, in this portion, it is considered sufficient that the joining of the solder bumps 8 terminates at the end of the outer peripheral portion of the outermost peripheral electrode 11a.
It can be said that a does not need to be an independent pad. However, since the solder bumps 8 are also joined to the exposed lead-out wirings, displacement and deformation of the solder bumps 8 occur. Therefore, when the mounter recognizes the BGA package 1 at the time of mounting, the irradiation light is irregularly reflected due to the positional shift and deformation of the solder bumps 8, and it becomes difficult to recognize the BGA package 1. There is a need to.

【００３１】本実施形態に示したＢＧＡパッケージ１の
実装構造を携帯機器、例えば携帯電話等に用いた場合、
携帯機器は落下等による外部衝撃を受けやすく、電子部
品と実装基板との接触不良が発生し易いことから、特に
有効に上記接触不良を防止することができる。When the mounting structure of the BGA package 1 shown in this embodiment is used in a portable device, for example, a portable telephone, etc.
Since the portable device is easily affected by an external impact due to a drop or the like and a contact failure between the electronic component and the mounting board is likely to occur, the contact failure can be particularly effectively prevented.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明を適用した一実施形態であって、ＢＧＡ
パッケージ１の断面模式図である。FIG. 1 shows an embodiment to which the present invention is applied, and a BGA
FIG. 2 is a schematic cross-sectional view of the package 1.

【図２】ＢＧＡパッケージ１の裏面に設けられた電極１
１の配列パターンを示す模式図である。FIG. 2 shows an electrode 1 provided on the back surface of the BGA package 1.
FIG. 3 is a schematic diagram showing an array pattern of No. 1;

【図３】従来におけるＢＧＡパッケージ１０１の断面模
式図である。FIG. 3 is a schematic cross-sectional view of a conventional BGA package 101.

【図４】ＢＧＡパッケージ１０１の裏面に設けられた電
極１０８の配列パターンを示す模式図である。FIG. 4 is a schematic diagram showing an arrangement pattern of electrodes provided on the back surface of the BGA package.

【符号の説明】[Explanation of symbols]

１…ＢＧＡパッケージ、２…回路配線、２ａ…引き出し
配線、３…インターポーザ、３ａ…コア材、３ｂ…スル
ーホール、８…はんだバンプ、１１…電極、１１ａ…最
外周電極、１１ｂ…内周電極、１３…ソルダレジスト。DESCRIPTION OF SYMBOLS 1 ... BGA package, 2 ... circuit wiring, 2a ... lead-out wiring, 3 ... interposer, 3a ... core material, 3b ... through hole, 8 ... solder bump, 11 ... electrode, 11a ... outermost peripheral electrode, 11b ... inner peripheral electrode, 13 ... Solder resist.

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】 一面側にアレイ状に配列された複数の電
極（１１）が備えられたインターポーザ（３）を有し、
前記複数の電極（１１）のそれぞれと接合されるはんだ
バンプ（８）を備えることによって、前記はんだバンプ
（８）をアレイ状に配列させて外部との電気的接続を行
う電子部品において、 前記アレイ状に配列された複数の電極（１１）のうち、
外周部分に位置する最外周電極（１１ａ）においては、
前記はんだバンプ（８）の接合部分の全てが前記最外周
電極（１１ａ）の外周部の端部で終端していることを特
徴とするバンプを有する電子部品。An interposer (3) provided with a plurality of electrodes (11) arranged in an array on one surface side,
An electronic component that includes a solder bump (8) joined to each of the plurality of electrodes (11) and arranges the solder bumps (8) in an array to make an electrical connection with the outside. Of the plurality of electrodes (11) arranged in a
In the outermost peripheral electrode (11a) located at the outer peripheral portion,
An electronic component having a bump, characterized in that all of the bonding portions of the solder bump (8) are terminated at the outer peripheral edge of the outermost electrode (11a). 【請求項２】 電気素子（５）と、 この電気素子（５）を表面側に配すると共に、裏面側に
アレイ状に配列された複数の電極（１１）を有してな
り、前記電気素子（５）と前記複数の電極（１１）とを
電気的に接続する回路配線（２）を備えたインターポー
ザ（３）と、 前記複数の電極（１１）のそれぞれと電気的に接合され
るはんだバンプ（８）とを備え、 前記はんだバンプ（８）をアレイ状に配列させて外部と
の電気的接続を行う電子部品において、 前記アレイ状に配列された複数の電極（１１）のうち、
外周部分に位置する最外周電極（１１ａ）においては、
前記はんだバンプ（８）の接合部分の全てが前記最外周
電極（１１ａ）の外周部の端部で終端していることを特
徴とするバンプを有する電子部品。2. An electric element comprising: an electric element; and a plurality of electrodes arranged in an array on an underside of the electric element. (5) an interposer (3) including circuit wiring (2) for electrically connecting the plurality of electrodes (11); and a solder bump electrically connected to each of the plurality of electrodes (11). (8) In the electronic component which arranges the solder bumps (8) in an array and makes an electrical connection with the outside, among the plurality of electrodes (11) arranged in the array,
In the outermost peripheral electrode (11a) located at the outer peripheral portion,
An electronic component having a bump, characterized in that all of the joining portions of the solder bumps (8) are terminated at ends of the outer peripheral portion of the outermost peripheral electrode (11a). 【請求項３】 前記インターポーザ（３）は、スルーホ
ール（３ｂ）を介して配線層（８）が電気的に接続され
た多層配線基板で構成されており、 前記最外周電極（１１ａ）の下部には、前記スルーホー
ル（３ｂ）が形成されており前記インターポーザ（３）
の内部における前記配線層（８）が引き出し配線となっ
ていることを特徴とする請求項１又は２に記載のバンプ
を有する電子部品。3. The interposer (3) is composed of a multilayer wiring board to which a wiring layer (8) is electrically connected via a through hole (3b), and a lower portion of the outermost peripheral electrode (11a). The through hole (3b) is formed in the interposer (3).
3. The electronic component having bumps according to claim 1, wherein the wiring layer (8) in the interior of the electronic component is a lead wiring. 4. 【請求項４】 請求項１乃至３のいずれかにおける前記
電子部品（１）を搭載されてなることを特徴とする携帯
機器用電子部品。4. An electronic component for a portable device, comprising the electronic component (1) according to claim 1.
JP25556897A 1997-07-24 1997-09-19 Mounting structure of electronic components for mobile devices Expired - Fee Related JP3262040B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP25556897A JP3262040B2 (en) 1997-09-19 1997-09-19 Mounting structure of electronic components for mobile devices
US09/121,303 US6303878B1 (en) 1997-07-24 1998-07-23 Mounting structure of electronic component on substrate board
US09/858,500 US6548765B2 (en) 1997-07-24 2001-05-17 Mounting structure of electronic component on substrate board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25556897A JP3262040B2 (en) 1997-09-19 1997-09-19 Mounting structure of electronic components for mobile devices

Publications (2)

Publication Number Publication Date
JPH1197574A true JPH1197574A (en) 1999-04-09
JP3262040B2 JP3262040B2 (en) 2002-03-04

Family

ID=17280532

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25556897A Expired - Fee Related JP3262040B2 (en) 1997-07-24 1997-09-19 Mounting structure of electronic components for mobile devices

Country Status (1)

Country Link
JP (1) JP3262040B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003100949A (en) * 2001-09-26 2003-04-04 Hitachi Ltd Semiconductor device
JP2007227609A (en) * 2006-02-23 2007-09-06 Seiko Epson Corp Semiconductor device and method of manufacturing semiconductor device
JP2007235009A (en) * 2006-03-03 2007-09-13 Renesas Technology Corp Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003100949A (en) * 2001-09-26 2003-04-04 Hitachi Ltd Semiconductor device
JP4677152B2 (en) * 2001-09-26 2011-04-27 エルピーダメモリ株式会社 Semiconductor device
JP2007227609A (en) * 2006-02-23 2007-09-06 Seiko Epson Corp Semiconductor device and method of manufacturing semiconductor device
JP2007235009A (en) * 2006-03-03 2007-09-13 Renesas Technology Corp Semiconductor device

Also Published As

Publication number Publication date
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