JPH1146053A - Package structure of electronic component - Google Patents
Package structure of electronic componentInfo
- Publication number
- JPH1146053A JPH1146053A JP9198829A JP19882997A JPH1146053A JP H1146053 A JPH1146053 A JP H1146053A JP 9198829 A JP9198829 A JP 9198829A JP 19882997 A JP19882997 A JP 19882997A JP H1146053 A JPH1146053 A JP H1146053A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- electronic component
- wiring board
- outermost peripheral
- outermost
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、電子部品の裏面に
アレイ状に配置されたはんだバンプによって、電子部品
と実装基板とを電気的に接続する電子部品の実装構造に
関し、特に携帯機器に用いる電子部品の実装構造に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting structure of an electronic component for electrically connecting the electronic component and a mounting board by solder bumps arranged in an array on the back surface of the electronic component, and more particularly to a portable device. The present invention relates to an electronic component mounting structure.
【0002】[0002]
【従来の技術】従来におけるボールグリッドアレイ(以
下、BGAという)パッケージ101の実装構造を図4
に示す。この図に示されるように、BGAパッケージ1
01の実装は、BGAパッケージ101の裏面にアレイ
状に配置された複数のはんだボールを溶融させてはんだ
バンプ102とし、この複数のはんだバンプ102を多
層プリント配線基板103に設けられた複数の電極10
4とをそれぞれ接合させることによって成される。具体
的には、多層プリント配線基板103には、複数の引き
出し配線となる配線層がコア材等を介して積層形成され
ていると共に、コア材の表面に複数の引き出し配線のそ
れぞれに電気的に接続された電極104が形成されてお
り、はんだバンプ102を電極104に接合させること
によって複数の引き出し配線のそれぞれと電気的接続を
行っている。2. Description of the Related Art A conventional mounting structure of a ball grid array (BGA) package 101 is shown in FIG.
Shown in As shown in this figure, the BGA package 1
The mounting of the solder bumps 102 is performed by melting a plurality of solder balls arranged in an array on the back surface of the BGA package 101 to form solder bumps 102, and using the plurality of solder bumps 102 on a plurality of electrodes 10 provided on a multilayer printed wiring board 103.
4 are joined together. Specifically, on the multilayer printed wiring board 103, a wiring layer serving as a plurality of lead-out wirings is laminated and formed via a core material or the like, and electrically connected to each of the plurality of lead-out wirings on the surface of the core material. The connected electrodes 104 are formed, and the solder bumps 102 are joined to the electrodes 104 to electrically connect to each of the plurality of lead wirings.
【0003】この多層プリント配線基板103にアレイ
状に配置された複数のはんだバンプ102のうち最外周
に位置するものと接合される電極(以下、最外周電極と
いう)104aにおける引き出し配線105は、外部と
の電気的導通を容易にするために、多層プリント配線基
板103の表面に形成される。この最外周電極104a
における拡大図を図5(a)に示し、図5(a)の上面
図を図5(b)に示す。図5(b)の斜線部分で示され
るように、引き出し配線105は保護用のソルダレジス
ト106によって覆われる。このとき、はんだバンプ1
02と電極104との接合面積を大きくとるために電極
104の表面を全面的に露出させているため、最外周電
極104aにおいてははんだバンプ102が最外周電極
104a及び引き出し配線105の一部と接合した状態
となる。A lead wire 105 at an electrode (hereinafter, referred to as an outermost electrode) 104a joined to an outermost one of a plurality of solder bumps 102 arranged in an array on the multilayer printed wiring board 103 is connected to an external device. Is formed on the surface of the multilayer printed wiring board 103 in order to facilitate electrical conduction with the substrate. This outermost electrode 104a
5A is shown in FIG. 5A, and a top view of FIG. 5A is shown in FIG. As shown by the hatched portion in FIG. 5B, the lead wiring 105 is covered with a solder resist 106 for protection. At this time, solder bump 1
Since the surface of the electrode 104 is entirely exposed in order to increase the bonding area between the second electrode 02 and the electrode 104, the solder bump 102 is bonded to a part of the outermost electrode 104a and a part of the lead-out wiring 105 in the outermost electrode 104a. It will be in the state of having done.
【0004】このため、はんだバンプ102は、引き出
し配線105と接合した部分においてはソルダレジスト
に接する状態となり、その他の部分においてはソルダレ
ジストに接しない状態となる。[0004] Therefore, the solder bump 102 is in a state of contacting the solder resist at a portion joined to the lead wiring 105, and is not in contact with the solder resist at other portions.
【0005】[0005]
【発明が解決しようとする課題】BGAパッケージ1や
多層プリント配線基板103に外部衝撃が加わった場
合、最外周電極104aの部分に応力集中が起こるた
め、最外周電極104aとはんだバンプ102との接合
部分ではこの応力集中によってはんだバンプ102が最
外周電極104aから剥離しない程度の接合強度が要求
される。When an external impact is applied to the BGA package 1 or the multilayer printed wiring board 103, stress concentration occurs at the outermost peripheral electrode 104a, so that the outermost peripheral electrode 104a and the solder bump 102 are joined. In such a portion, a bonding strength that does not cause the solder bumps 102 to be separated from the outermost peripheral electrode 104a due to the stress concentration is required.
【0006】しかしながら、最外周電極104aにおけ
る接合部分の接合強度が上記応力集中に耐えられる場合
であっても、図6(a)の2点鎖線で示されるように、
最外周電極104aのうち引き出し配線105が形成さ
れていない外周部であって、最外周電極104aとコア
材との界面の端部Aからコア材に亀裂が発生し、この亀
裂が大きくなって引き出し配線を断線させて接触不良を
発生させるという問題がある。However, even when the bonding strength of the bonding portion of the outermost peripheral electrode 104a can withstand the stress concentration, as shown by a two-dot chain line in FIG.
A crack is generated in the core material from the end A of the interface between the outermost peripheral electrode 104a and the core material in the outer peripheral portion of the outermost peripheral electrode 104a where the lead-out wiring 105 is not formed. There is a problem that the wiring is broken and a contact failure occurs.
【0007】本発明は上記点に鑑みてなされ、外部衝撃
によって発生する配線基板の亀裂を防止することによっ
て、配線基板に備えられた引き出し配線の断線を防止
し、電子部品と実装基板との接触不良を防止できる電子
部品の実装構造を提供することを目的とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and thereby prevents breakage of a wiring board provided on a wiring board by preventing cracks of the wiring board caused by an external impact, thereby preventing contact between an electronic component and a mounting board. It is an object of the present invention to provide an electronic component mounting structure that can prevent a defect.
【0008】[0008]
【課題を解決するための手段】上記問題を解決するため
に、本発明者らは多層プリント配線基板103に亀裂が
発生する原因を検討した。図7に最外周電極104aの
近傍における拡大断面図を示す。最外周電極104aに
おけるはんだバンプ102の接合部について、引き出し
配線105が形成されていない部分を見てみると、はん
だバンプ102が最外周電極104aとコア材との界面
の端部Aにまで回り込んで終端していることが判る。こ
の端部Aは外部衝撃によってコア材に最も亀裂が発生し
易い部分であり、この端部Aが外部衝撃時における応力
集中点と一致してしまうことが上記亀裂を発生させる原
因であると考えられる。In order to solve the above problem, the present inventors have studied the cause of the occurrence of cracks in the multilayer printed wiring board 103. FIG. 7 shows an enlarged sectional view near the outermost peripheral electrode 104a. Looking at the portion of the outermost peripheral electrode 104a where the solder bump 102 is joined, where the lead-out wiring 105 is not formed, the solder bump 102 wraps around to the end A of the interface between the outermost peripheral electrode 104a and the core material. It can be seen that it is terminated at. The end A is a portion where the core material is most likely to crack due to an external impact, and it is considered that the fact that the end A coincides with the stress concentration point at the time of the external impact is the cause of the crack. Can be
【0009】そこで、本発明は上記目的を達成するた
め、以下の技術的手段を採用する。請求項1に記載の発
明においては、実装基板(3)にアレイ状に配列された
複数の電極(2)のうち、該配列の外周に位置する最外
周電極(2a)においては、はんだバンプ(7)と最外
周電極(2a)との接合の終端部全てが最外周電極(2
a)の内周部分にあることを特徴としている。Therefore, the present invention employs the following technical means to achieve the above object. According to the first aspect of the present invention, of the plurality of electrodes (2) arranged in an array on the mounting board (3), the outermost peripheral electrode (2a) located on the outer periphery of the arrangement has a solder bump (2). 7) and the outermost peripheral electrode (2a) are all joined to the outermost peripheral electrode (2a).
a) in the inner peripheral portion.
【0010】このように、はんだバンプ(7)と最外周
電極(2a)の終端部全てが最外周電極(2a)の内周
部分にあるようにすれば、最も亀裂が発生し易い最外周
電極(2a)の端部と、外部衝撃時における応力集中点
が一致したないため、実装基板(3)に亀裂が発生する
ことを防止することができる。これにより、引き出し配
線の断線を防止することができ、電子部品(1)と実装
基板(3)の接触不良を防止することができる。As described above, if all the terminal portions of the solder bump (7) and the outermost electrode (2a) are located on the inner peripheral portion of the outermost electrode (2a), the outermost electrode where cracks are most likely to occur. Since the end of (2a) does not coincide with the stress concentration point at the time of external impact, it is possible to prevent the mounting substrate (3) from cracking. Accordingly, disconnection of the lead-out wiring can be prevented, and poor contact between the electronic component (1) and the mounting board (3) can be prevented.
【0011】請求項2に記載の発明においては、最外周
電極(2a)の外周部分が保護膜(10)で覆われてい
ることを特徴としている。このように、保護膜(10)
によって最外周電極(2a)の外周部分を覆うようにす
れば、はんだバンプ(7)の接合部分が最外周電極(2
a)の内周部分で終端するようにすることができる。こ
れにより、請求項1と同様の効果を得ることができる。The invention according to claim 2 is characterized in that the outer peripheral portion of the outermost peripheral electrode (2a) is covered with a protective film (10). Thus, the protective film (10)
If the outer peripheral portion of the outermost peripheral electrode (2a) is covered by the outermost peripheral electrode (2a), the joining portion of the solder bump (7) is
It may be terminated at the inner peripheral portion of a). Thereby, the same effect as the first aspect can be obtained.
【0012】請求項3に記載の発明においては、前記電
子部品(1)は、携帯機器に搭載されるものであること
を特徴としている。携帯機器においては、落下等による
外部衝撃を受けやすく、電子部品(1)と実装基板
(3)との接触不良が発生し易い。このため、請求項1
又は2に記載の発明を携帯機器に適用すると効果的であ
る。According to a third aspect of the present invention, the electronic component (1) is mounted on a portable device. In a portable device, it is easy to receive an external impact due to a drop or the like, and poor contact between the electronic component (1) and the mounting board (3) is likely to occur. Therefore, claim 1
Alternatively, it is effective to apply the invention described in 2 to a portable device.
【0013】なお、上記各手段の括弧内の符号は、後述
する実施形態記載の具体的手段との対応関係を示すもの
である。The reference numerals in parentheses of the above means indicate the correspondence with the concrete means described in the embodiments described later.
【0014】[0014]
【発明の実施の形態】以下、本発明の実施の形態を図に
基づいて説明する。図1に、BGAパッケージ1を所定
の電極2(パッド)が備えられた多層プリント配線基板
3に実装したときの模式図を示す。また、図2に多層プ
リント配線基板3に備えられた電極2の配列パターンを
示す。但し、図2は電極2の配列パターンを簡略化して
表したものであり、斜線部で示されたような円形の電極
がアレイ状に配置されていることを示している。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic diagram when the BGA package 1 is mounted on a multilayer printed wiring board 3 provided with predetermined electrodes 2 (pads). FIG. 2 shows an arrangement pattern of the electrodes 2 provided on the multilayer printed wiring board 3. However, FIG. 2 is a simplified representation of the arrangement pattern of the electrodes 2, and shows that circular electrodes as shown by hatched portions are arranged in an array.
【0015】ここで、BGAパッケージ1とは、回路配
線6を有するインターポーザ4に接着剤等を介して半導
体チップを搭載し、回路配線6と半導体チップとをAu
ワイヤ等で電気的に接続したのち、封止樹脂5で半導体
チップ及びAuワイヤを封止したものを示す。本実施形
態では、薄型化や生産性を考慮してインターポーザ4に
はポリイミドを用いており、また封止樹脂5としてはエ
ポキシ樹脂等を用いている。Here, the BGA package 1 is such that a semiconductor chip is mounted on an interposer 4 having a circuit wiring 6 via an adhesive or the like, and the circuit wiring 6 and the semiconductor chip are connected to each other by Au.
This shows a semiconductor chip and an Au wire sealed with a sealing resin 5 after being electrically connected by a wire or the like. In the present embodiment, polyimide is used for the interposer 4 and epoxy resin or the like is used for the sealing resin 5 in consideration of thinning and productivity.
【0016】このBGAパッケージ1の裏面に相当する
インターポーザ4には、アレイ状に穴が空けられてお
り、この穴を介して回路配線6にはんだボールを溶融接
合することによって、BGAパッケージ1の裏面にはん
だバンプ7がアレイ状に配置された状態となっている。
一方、多層プリント配線基板3は、多数の配線層8を積
層状に形成したものであり、図2に示すような配置パタ
ーンで形成された電極2を備えている。この電極2の配
置パターンは、はんだバンプ7の配置と対応するように
なっていて、実装時にBGAパッケージ1に設けられた
はんだバンプ7と多層プリント配線基板3に設けられた
電極2とがそれぞれ組合わされるようになっている。そ
して、本実施形態では、多層プリント配線基板3に備え
られた複数の電極2のうちの少なくとも最外周電極2a
(図2における領域Xにおける電極2)においては、最
外周電極2aの外周部分をソルダレジスト10で覆うよ
うにしている。なお、本実施形態においては、最外周電
極2a内に配置される内周電極2b(図2における領域
Yにおける電極2)においては、内周電極2bの外周部
分を覆っていないが、最外周電極2aと同様に外周部分
を覆うようにしても良い。The interposer 4 corresponding to the back surface of the BGA package 1 is provided with holes in an array. The solder balls are melt-bonded to the circuit wiring 6 through the holes, thereby forming the back surface of the BGA package 1. The solder bumps 7 are arranged in an array.
On the other hand, the multilayer printed wiring board 3 is formed by laminating a large number of wiring layers 8 and has the electrodes 2 formed in an arrangement pattern as shown in FIG. The arrangement pattern of the electrodes 2 corresponds to the arrangement of the solder bumps 7, and the solder bumps 7 provided on the BGA package 1 and the electrodes 2 provided on the multilayer printed wiring board 3 at the time of mounting are respectively assembled. It is to be combined. In the present embodiment, at least the outermost peripheral electrode 2a of the plurality of electrodes 2 provided on the multilayer printed wiring board 3
In (the electrode 2 in the region X in FIG. 2), the outer peripheral portion of the outermost peripheral electrode 2a is covered with the solder resist 10. In the present embodiment, the inner peripheral electrode 2b (the electrode 2 in the region Y in FIG. 2) disposed inside the outermost peripheral electrode 2a does not cover the outer peripheral portion of the inner peripheral electrode 2b, but the outermost peripheral electrode 2b is not covered. You may make it cover an outer peripheral part similarly to 2a.
【0017】以下、多層プリント配線基板3の製造方法
について説明する。なお、簡略化のため、4層からなる
多層プリント配線基板3について説明する。まず、両面
に銅箔処理が成されたコア材を用意し、所定の位置にド
リルで穴を空けてスルーホール(ブラインドビアホー
ル)を形成する。そして、このスルーホールを通じて、
コア材の両面における銅を電気的に導通させるべく、銅
メッキによるスルーホールメッキを行う。これにより、
スルーホールメッキ処理が施された基板が完成する。Hereinafter, a method for manufacturing the multilayer printed wiring board 3 will be described. For simplicity, a multilayer printed wiring board 3 composed of four layers will be described. First, a core material having copper foil treated on both surfaces is prepared, and a through hole (blind via hole) is formed by drilling a hole at a predetermined position. And through this through hole,
Through-hole plating by copper plating is performed to electrically conduct copper on both surfaces of the core material. This allows
A substrate subjected to through-hole plating is completed.
【0018】次に、このようなスルーホールメッキ処理
が施された基板を2枚用意し、この2枚の基板のうち、
後に張り合わせる側同士の面の銅箔をエッチングによっ
てパターニングする。そして、ガラスクロスにエポキシ
樹脂を含有させたプリプレグを2枚の基板間に挟み込ん
だ状態で加熱プレス処理を行い、2枚の基板を張り合わ
せる。これにより、4層に分かれた銅箔の層が形成され
る。Next, two substrates subjected to such a through-hole plating process are prepared, and out of the two substrates,
The copper foil on the surfaces to be bonded later is patterned by etching. Then, a heat press process is performed with the prepreg containing the epoxy resin contained in the glass cloth sandwiched between the two substrates, and the two substrates are bonded to each other. Thus, a copper foil layer divided into four layers is formed.
【0019】そして、4層分全てを貫通するようにドリ
ルで穴を空けてスルーホールを形成し、銅メッキによる
スルーホールメッキを行って4層に分かれた銅箔が電気
的に導通するようにする。この後、BGAパッケージ1
を実装する側、つまり多層プリント配線基板3の表面に
該当する側の銅箔をエッチングによってパターニング
し、電極部分の銅箔を残すと共に所定の引き出し配線を
形成する。A through hole is formed by drilling a hole so as to penetrate all four layers, and through-hole plating is performed by copper plating so that the copper foil divided into four layers is electrically connected. I do. After that, BGA package 1
Is etched, the copper foil on the side corresponding to the surface of the multilayer printed wiring board 3 is patterned by etching, leaving the copper foil on the electrode portion and forming a predetermined lead-out wiring.
【0020】この後、引き出し配線を保護するために、
ソルダレジスト10を印刷形成して、ソルダレジスト1
0にて引き出し配線と最外周電極2aの外周部分を覆
う。このときの最外周電極2aの部分の拡大断面図を図
3(a)に示す。また、図3(a)の上面図を図3
(b)に示す。図3(a)、(b)に示すように、最外
周電極2aの外周部の全てを覆うように、すなわち最外
周電極2aの外周部とソルダレジスト10がオーバラッ
プするようにソルダレジスト10を形成している。ま
た、最外周電極2aの内周部分(外周部分以外)をソル
ダレジスト10によって覆わないように、ソルダレジス
ト10の一部を円形状に開口させており、最外周電極2
aとはんだバンプ7との接合が可能になっている。Thereafter, in order to protect the lead wiring,
The solder resist 10 is printed and formed, and the solder resist 1 is formed.
0 covers the lead wiring and the outer peripheral portion of the outermost peripheral electrode 2a. FIG. 3A is an enlarged cross-sectional view of the outermost peripheral electrode 2a at this time. FIG. 3A is a top view of FIG.
(B). As shown in FIGS. 3A and 3B, the solder resist 10 is covered so as to cover the entire outer peripheral portion of the outermost peripheral electrode 2a, ie, so that the outer peripheral portion of the outermost peripheral electrode 2a and the solder resist 10 overlap. Has formed. A part of the solder resist 10 is opened in a circular shape so that the inner peripheral portion (other than the outer peripheral portion) of the outermost peripheral electrode 2 a is not covered with the solder resist 10.
a and the solder bump 7 can be joined.
【0021】このソルダレジスト10を印刷形成するに
際して印刷ズレが発生するため、ソルダレジスト10と
最外周電極2aのオーバラップ量を考慮して、印刷ズレ
が発生しても最外周電極2aの外周部全てがソルダレジ
スト10で覆われるようにしている。なお、この後、必
要に応じて無電解メッキ法により、電極2上にニッケル
−金(Ni−Au)メッキを施したり、錫(Sn)メッ
キやパラジウム(Pd)メッキを施す等して、複数の配
線層8を備えた多層プリント配線基板3が完成する。Since a printing shift occurs when the solder resist 10 is formed by printing, even if a printing shift occurs, the outer peripheral portion of the outermost peripheral electrode 2a is considered in consideration of the amount of overlap between the solder resist 10 and the outermost peripheral electrode 2a. All are covered with the solder resist 10. After that, if necessary, the electrode 2 may be plated with nickel-gold (Ni-Au), tin (Sn), or palladium (Pd) by electroless plating to obtain a plurality of electrodes. The multilayer printed wiring board 3 including the wiring layer 8 is completed.
【0022】このようにして完成した多層プリント配線
基板3上にBGAパッケージ1を位置決め搭載したの
ち、はんだバンプ7を溶融することでBGAパッケージ
1が多層プリント配線基板3に実装される。ここで、本
実施形態における最外周電極2a近傍における拡大断面
図を図4に示す。この図4に示されるはんだバンプ7の
接合部を見てみると、本実施形態では最外周電極2aの
外周部をソルダレジスト10で覆っているため、はんだ
バンプ7の接合部が最外周電極2aとコア材の界面の端
部Aにまで回り込まず、はんだバンプ7と最外周電極2
aとの接合の終端部が全て最外周電極2aの内周部分で
終端していることが判る。After the BGA package 1 is positioned and mounted on the multilayer printed wiring board 3 completed in this way, the BGA package 1 is mounted on the multilayer printed wiring board 3 by melting the solder bumps 7. Here, FIG. 4 shows an enlarged cross-sectional view in the vicinity of the outermost peripheral electrode 2a in the present embodiment. Looking at the joints of the solder bumps 7 shown in FIG. 4, since the outer periphery of the outermost electrode 2a is covered with the solder resist 10 in the present embodiment, the joint of the solder bump 7 is the outermost electrode 2a. The solder bump 7 and the outermost peripheral electrode 2
It can be seen that all of the ends of the connection with a are terminated at the inner periphery of the outermost electrode 2a.
【0023】従って、外部衝撃による応力集中点となる
はんだバンプ7の接合部と、コア材の亀裂が最も発生し
易い最外周電極2aとコア材の界面の端部Aとが一致し
ないため、外部衝撃による応力集中によってもコア材に
亀裂が発生することを防止することができる。これによ
り、上記コア材の亀裂による引き出し配線の断線を防止
することができる、BGAパッケージ1と多層プリント
配線基板3との接触不良を防止することができる。Therefore, the joint portion of the solder bump 7, which is a stress concentration point due to an external impact, does not coincide with the edge A of the interface between the outermost peripheral electrode 2 a where the core material is most likely to crack and the core material. It is possible to prevent the core material from cracking due to stress concentration due to impact. Thereby, disconnection of the lead-out wiring due to the crack of the core material can be prevented, and poor contact between the BGA package 1 and the multilayer printed wiring board 3 can be prevented.
【0024】なお、本実施形態においては、最外周電極
2aの引き出し配線がコア材の表面に形成されているも
のを示したが、最外周電極2aの引き出し配線が最外周
電極2aの下層に内蔵されているものにおいて最外周電
極2aの外周部をソルダレジスト10で覆うようにして
も上記と同様の効果を得ることができる。また、最外周
電極2aが引き出し配線を備えないダミー電極である場
合においても最外周電極2aの外周部をソルダレジスト
10で覆うことにより、結果的に上記と同様の効果を得
ることができる。すなわち、最外周電極2aにおいてコ
ア部材に亀裂が発生しないような実装構造であれば、内
周電極2bに応力集中することがないため、内周電極2
bにおいてコア部材に亀裂が発生するということを防止
することができるからである。但し、この場合には、ダ
ミー電極を形成するスペースが必要になるためBGAパ
ッケージ1及び多層プリント配線基板3が全体的に大き
くなるため、上記実施形態の方法が有効である。In the present embodiment, the lead wire of the outermost peripheral electrode 2a is formed on the surface of the core material. However, the lead wire of the outermost peripheral electrode 2a is built in the lower layer of the outermost peripheral electrode 2a. The same effect as described above can be obtained even when the outer peripheral portion of the outermost peripheral electrode 2a is covered with the solder resist 10. Further, even when the outermost peripheral electrode 2a is a dummy electrode having no lead-out wiring, by covering the outer peripheral portion of the outermost peripheral electrode 2a with the solder resist 10, the same effect as described above can be obtained. That is, if the mounting structure is such that the core member does not crack in the outermost peripheral electrode 2a, no stress is concentrated on the inner peripheral electrode 2b.
This is because it is possible to prevent the occurrence of cracks in the core member in b. However, in this case, a space for forming a dummy electrode is required, so that the size of the BGA package 1 and the multilayer printed wiring board 3 are increased as a whole, so that the method of the above embodiment is effective.
【0025】なお、本実施形態に示したBGAパッケー
ジ1と多層プリント配線基板3との実装構造を携帯機
器、例えば携帯電話等に用いた場合、携帯機器は落下等
による外部衝撃を受けやすく、電子部品と実装基板との
接触不良が発生し易いため、特に有効に上記接触不良を
防止することができる。When the mounting structure of the BGA package 1 and the multilayer printed wiring board 3 shown in the present embodiment is used for a portable device, for example, a portable telephone, the portable device is susceptible to an external impact due to a drop or the like. Since the contact failure between the component and the mounting board easily occurs, the contact failure can be particularly effectively prevented.
【図1】本発明を適用した一実施形態であって、BGA
パッケージ1を多層プリント配線基板3に実装したとき
の断面模式図である。FIG. 1 shows an embodiment to which the present invention is applied, and a BGA
FIG. 2 is a schematic cross-sectional view when a package 1 is mounted on a multilayer printed wiring board 3.
【図2】多層プリント配線基板3に備えられた電極2の
配列パターンを示す模式図である。FIG. 2 is a schematic diagram showing an arrangement pattern of electrodes 2 provided on a multilayer printed wiring board 3;
【図3】(a)は最外周電極2aの部分拡大図であり、
(b)は(a)の上面図である。FIG. 3A is a partially enlarged view of an outermost peripheral electrode 2a,
(B) is a top view of (a).
【図4】最外周電極2aにおけるはんだバンプ7の接合
部を示す説明図である。FIG. 4 is an explanatory diagram showing a bonding portion of a solder bump 7 at an outermost peripheral electrode 2a.
【図5】従来におけるBGAパッケージ101を多層プ
リント基板103に実装したときの断面模式図である。FIG. 5 is a schematic cross-sectional view when a conventional BGA package 101 is mounted on a multilayer printed circuit board 103.
【図6】(a)は最外周電極104aの部分断面図であ
り、(b)は(a)の上面図である。6A is a partial cross-sectional view of the outermost peripheral electrode 104a, and FIG. 6B is a top view of FIG.
【図7】最外周電極104aにおけるはんだバンプ10
2の接合部を示す説明図である。FIG. 7 shows a solder bump 10 on the outermost peripheral electrode 104a.
It is explanatory drawing which shows the 2nd junction.
1…BGAパッケージ、2…電極、2a…最外周電極、
2b…内周電極、3…多層プリント配線基板、4…イン
ターポーザ、7…はんだバンプ、10…ソルダレジス
ト。1 BGA package, 2 electrodes, 2a outermost electrode,
2b: inner peripheral electrode, 3: multilayer printed wiring board, 4: interposer, 7: solder bump, 10: solder resist.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 近藤 宏司 愛知県刈谷市昭和町1丁目1番地 株式会 社デンソー内 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Koji Kondo, Inventor 1-1-1, Showa-cho, Kariya-shi, Aichi, Japan
Claims (3)
を成す複数のはんだバンプ(7)を形成したのち、前記
はんだバンプ(7)の配列に対応するようにアレイ状に
配列された複数の電極(2)を有する実装基板(3)上
に前記電子部品(1)を位置決め搭載し、前記複数のは
んだバンプ(7)を溶融させて前記電極(2)と接合さ
せることにより前記電子部品(1)と前記実装基板
(3)とが電気的に接合されてなる電子部品の実装構造
において、 前記アレイ状に配列された複数の電極(2)のうち、該
配列の外周に位置する最外周電極(2a)においては、
前記はんだバンプ(7)と前記最外周電極(2a)との
接合の終端部全てが該最外周電極(2a)の内周部分に
あることを特徴とする電子部品の実装構造。After a plurality of solder bumps (7) in an array are formed on the back surface of an electronic component (1), the solder bumps (7) are arranged in an array corresponding to the arrangement of the solder bumps (7). The electronic component (1) is positioned and mounted on a mounting substrate (3) having a plurality of electrodes (2), and the plurality of solder bumps (7) are melted and joined to the electrodes (2) to thereby form the electronic component. In a mounting structure of an electronic component in which a component (1) and the mounting board (3) are electrically joined, the plurality of electrodes (2) arranged in an array are located on an outer periphery of the array. In the outermost peripheral electrode (2a),
A mounting structure for an electronic component, wherein the entire end portion of the joint between the solder bump (7) and the outermost electrode (2a) is located on the inner peripheral portion of the outermost electrode (2a).
保護膜(10)で覆われていることを特徴とする電子部
品の実装構造。2. An outer peripheral portion of the outermost peripheral electrode (2a)
An electronic component mounting structure, which is covered with a protective film (10).
(1)を搭載されてなることを特徴とする携帯機器。3. A portable device comprising the electronic component (1) according to claim 1 or 2.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9198829A JPH1146053A (en) | 1997-07-24 | 1997-07-24 | Package structure of electronic component |
US09/121,303 US6303878B1 (en) | 1997-07-24 | 1998-07-23 | Mounting structure of electronic component on substrate board |
US09/858,500 US6548765B2 (en) | 1997-07-24 | 2001-05-17 | Mounting structure of electronic component on substrate board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9198829A JPH1146053A (en) | 1997-07-24 | 1997-07-24 | Package structure of electronic component |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH1146053A true JPH1146053A (en) | 1999-02-16 |
Family
ID=16397619
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9198829A Pending JPH1146053A (en) | 1997-07-24 | 1997-07-24 | Package structure of electronic component |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH1146053A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10114897A1 (en) * | 2001-03-26 | 2002-10-24 | Infineon Technologies Ag | Electronic component |
JP2008028406A (en) * | 2007-08-10 | 2008-02-07 | Sanyo Electric Co Ltd | Multilayer board for mounting semiconductor chip and semiconductor-chip mounted multilayer board |
JP2011103398A (en) * | 2009-11-11 | 2011-05-26 | Canon Inc | Semiconductor device |
-
1997
- 1997-07-24 JP JP9198829A patent/JPH1146053A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10114897A1 (en) * | 2001-03-26 | 2002-10-24 | Infineon Technologies Ag | Electronic component |
US6852931B2 (en) | 2001-03-26 | 2005-02-08 | Infineon Technologies Ag | Configuration having an electronic device electrically connected to a printed circuit board |
US7340826B2 (en) | 2001-03-26 | 2008-03-11 | Infineon Technologies Ag | Method for producing an electronic device connected to a printed circuit board |
JP2008028406A (en) * | 2007-08-10 | 2008-02-07 | Sanyo Electric Co Ltd | Multilayer board for mounting semiconductor chip and semiconductor-chip mounted multilayer board |
JP2011103398A (en) * | 2009-11-11 | 2011-05-26 | Canon Inc | Semiconductor device |
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