JP2008028406A - Multilayer board for mounting semiconductor chip and semiconductor-chip mounted multilayer board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer board for mounting semiconductor chips in which internal stresses caused by the difference in thermal expansion coefficients between sealing resin composed of a thermosetting resin and circuit elements composed of silicon and generated inside the circuit device at high temperature are suppressed, and a semiconductor-chip mounted multilayer board. <P>SOLUTION: An interlayer insulating film 11 is formed with a thermosetting resin between each conductive wiring layer 12, forming a multilayer structure. Thereby, the interlayer insulating film 11 functions as a thermal-stress buffering layer, and prevents lowering of the device reliability caused by the internal stresses. In addition, by using a liquid-crystal polymer for the thermosetting resin used herein, it is possible to prevent invasion of moisture into the device. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a multilayer substrate and a semiconductor element for mounting a semiconductor element in which the interlayer insulating layer that insulates each conductive wiring layer is formed of a thermoplastic resin so that the interlayer insulating layer functions as a stress relaxation / buffer material at high temperatures. The present invention relates to a mounting multilayer board.

  In recent years, IC packages are increasingly used in portable devices and small / high-density mounting devices, and conventional IC packages and their mounting concepts are about to change drastically. As an example of the insulating resin sheet, there is a technique related to a semiconductor device that employs a polyimide resin sheet that is a flexible sheet (see, for example, Patent Document 1).

  FIG. 12 shows a semiconductor device that employs the flexible sheet 50 as an interposer substrate. FIG. 12A is a plan view of the semiconductor device, and FIG. 12B is a cross-sectional view taken along the line AA in FIG. A method for manufacturing this semiconductor device will be described below.

  First, on the flexible sheet 50, a copper foil pattern 51 is prepared by being bonded via an adhesive. The copper foil pattern 51 differs in pattern depending on the semiconductor element to be mounted depending on the transistor and IC, but generally, a bonding pad 51A and an island 51B are formed. Reference numeral 52 denotes an opening for taking out an electrode from the back surface of the flexible sheet 50, and the copper foil pattern 51 is exposed. Subsequently, the flexible sheet 50 is conveyed to a die bonder, and the semiconductor element 53 is mounted thereon. Thereafter, the flexible sheet 50 is conveyed to a wire bonder, and the bonding pads 51A and the pads of the semiconductor element 53 are electrically connected by the fine metal wires 54.

  Finally, as shown in FIG. 12A, a sealing resin 55 is provided on the surface of the flexible sheet 50 and sealed. Here, transfer molding is performed so as to cover the bonding pad 51A, the island 51B, the semiconductor element 53, and the fine metal wire 54. Thereafter, as shown in FIG. 12B, connecting means 56 such as solder or solder balls is provided, and the spherical solder 56 fused to the bonding pad 51A through the opening 52 by passing through a solder reflow furnace. Is formed. Thereafter, since the semiconductor elements 53 are formed in a matrix on the flexible sheet 50, it is diced and individually separated.

  However, the method for manufacturing a semiconductor device described with reference to FIG. 12 has various problems because the flexible sheet 50 is employed. That is, since the flexible sheet 50 itself has a certain thickness, there is a limit to reducing the thickness of the apparatus, and the flexible sheet 50 is cracked or warped in the manufacturing process. It had a number of problems.

  In order to solve the above problems, a thin circuit device that eliminates the need for an interposer substrate such as the flexible sheet 50 and a manufacturing method thereof have been proposed (see, for example, Patent Document 2).

  The outline of the circuit device 60 will be described with reference to FIG. The circuit device 60 is configured without an interposer such as a flexible sheet. Then, by etching the conductive film adhered in sheet form on the front and back of the insulating resin 62, a multilayer wiring structure including the first conductive wiring layer 63 and the second conductive wiring layer 64 is realized. The first conductive wiring layer 63 and the second conductive wiring layer 64 are insulated by an interlayer insulating layer 62 and electrically connected at a desired location by a multilayer connection means 72. Further, an external electrode 74 is formed at a desired location of the second conductive wiring layer 64, and this serves as a connection electrode to a mounting substrate or the like. A semiconductor element 67 is fixed on the first conductive wiring layer 63 via an insulating adhesive 68, and the electrode of the semiconductor element 67 and the first conductive wiring layer 63 are electrically connected by a thin metal wire 71. It is connected. The sealing resin 73 has a function of sealing the semiconductor element 67 and the fine metal wire 71 and mechanically supporting the whole.

The above-described circuit device 60 is configured without an interposer such as a flexible sheet, and thus has an advantage that the entire device is thinned.
JP 2000-133678 A (page 5, FIG. 2) Japanese Patent Application No. 2001-185420 (FIG. 1)

  In the circuit device 60 described above, the thermal expansion coefficients of the semiconductor element 67, which is a constituent element, the conductive wiring layer, and the sealing resin 73 formed of a thermosetting resin are different. In particular, the semiconductor element 67 and the sealing resin 73, which is an organic material, have a large difference in thermal expansion coefficient. Therefore, a thermal stress is generated due to a temperature change under use conditions, which causes a problem in connection reliability.

  Furthermore, when a large-sized circuit device in which a plurality of semiconductor elements and other circuit elements are mounted has the same configuration as the circuit device 60, a larger thermal stress acts on the connection for the same reason as described above. There is a problem with reliability.

  The present invention has been made in view of the above-described problems, and a main object of the present invention is to internally generate thermal stress generated due to differences in thermal expansion coefficients between components of a circuit device. An object of the present invention is to provide a circuit device having a configuration capable of buffering.

The present invention is a multilayer substrate for mounting a semiconductor element made in view of the above problems,
The conductive wiring laminated in multiple layers via a plurality of interlayer insulating layers, and a multilayer connection means for connecting the conductive wirings through the interlayer insulating layer at a desired location,
Of the plurality of interlayer insulation layers, the uppermost interlayer insulation layer is made of a thermoplastic resin,
The above-described interlayer insulating layer below the uppermost interlayer insulating layer is solved by being made of a thermosetting resin.
Furthermore, the problem is solved by a semiconductor mounting multilayer substrate including semiconductor elements mounted face-down.

According to the present invention, by forming an interlayer insulating layer that insulates each conductive wiring layer from a thermoplastic resin, the interlayer insulating layer functions as a stress relieving / buffering material at high temperatures, thereby improving the reliability of the circuit device. Can be improved.

(First embodiment illustrating the configuration of the circuit device 10)
With reference to FIG. 1, the structure of the circuit apparatus 10 of this invention is demonstrated. The circuit device 10 includes a first conductive wiring layer 12A and a second conductive wiring layer 12B stacked via an interlayer insulating layer 11, a circuit element 13 fixed on the first conductive wiring layer 12A, Sealing resin layer 17 covering one conductive wiring layer 12A and circuit element 13, multi-layer connecting means 14 for connecting both conductive wiring layers 12 to each other through interlayer insulating layer 11 at a desired location, and a second And the external electrode 16 provided at a desired location of the conductive wiring layer 12B, and the interlayer insulating layer 11 is made of a thermoplastic resin. Such components are described below.

  Referring to FIG. 1A, first conductive wiring layer 12A and second conductive wiring layer 12B are formed by etching conductive films formed on the front and back of interlayer insulating layer 11. The material of the conductive film is preferably a material mainly made of Cu, or a known lead frame material, and is coated on the interlayer insulating layer 11 by a plating method, a vapor deposition method or a sputtering method, or a rolling method or a plating method. The metal foil formed by may be stuck. Further, the first conductive wiring layer 12 </ b> A and the second conductive wiring layer 12 </ b> B are covered with an overcoat resin 18.

The interlayer insulating layer 11 has a function of insulating the first conductive wiring layer 12 </ b> A and the second conductive wiring layer 12 </ b> B, and is provided as a layer between the two conductive wiring layers 12. As a material of the interlayer insulating layer 11, a thermoplastic resin having a characteristic of being softened at a high temperature is employed. Examples of the thermoplastic resin applicable to the present invention include ABS resin, polypropylene, polyethylene, polystyrene, acrylic, polyethylene terephthalate, polyphenylene ether, nylon, polyamide, polycarbonate, polyacetal, polybutylene terephthalate, polyphenylene sulfide, and polyether ether ketone. , Liquid crystal polymers, fluororesins, urethane resins and elastomers. In particular, the liquid crystal polymer is a material suitable as a thermoplastic resin employed for the interlayer insulating layer because it has a thermal expansion coefficient close to that of the circuit element 13 made of silicon and has high gas barrier properties.

  The circuit element 13 is fixed on the first conductive wiring layer 12 </ b> A via an insulating adhesive or the like, and is electrically connected to the first conductive wiring layer 12 </ b> A via a fine metal wire 15. In the present embodiment, two semiconductor elements are fixed as the circuit element 13. Further, as the circuit element 13, a circuit element other than a semiconductor element can be employed, and a chip capacitor, a chip resistor, a transistor chip, or the like can also be employed as the circuit element 13.

  The multilayer connection means 14 connects the first conductive wiring layer 12A and the second conductive wiring layer 12B through the interlayer insulating layer 11 at a desired location. Specifically, a copper plating film is suitable as the multilayer wiring means 14. Further, a plating film of gold, silver, palladium or the like may be used.

  The sealing resin layer 17 covers the first conductive wiring layer 12 </ b> A and the circuit element 13. The sealing resin layer 17 also serves as a mechanical support for the entire completed circuit device. Moreover, the sealing resin layer 17 is formed from a thermosetting resin formed by transfer molding. Examples of the thermosetting resin applicable to the present invention include urea, phenol, melamine, furan, alkyd, unsaturated polyester, diallyl phthalate, epoxy, silicon resin, and polyurethane.

  The external electrode 16 is provided at a desired location on the second conductive wiring layer 12B. That is, most of the second conductive wiring layer 12B is covered with the overcoat resin 18, and the external electrode 16 formed of a brazing material such as solder is provided on the exposed second conductive wiring layer 12B.

  With reference to FIG. 1 (B), the structure of the circuit device 10 of another form is demonstrated. The basic configuration of the circuit device 10 shown in FIG. 1 is the same as that shown in FIG. 1A, and the circuit element 13A is mounted on the first conductive wiring layer 12A. That is, the circuit element 13 which is a semiconductor element is fixed to the center portion of the circuit device 10, and the circuit element 13A is mounted on the first conductive wiring layer 12A in the outermost peripheral portion. As the circuit element 13A, a passive component such as a chip resistor or a chip capacitor, or an active component such as a bare transistor chip or a diode can be employed. Thus, by mounting the circuit element 13A on the outermost peripheral portion, the mounting density of the entire apparatus can be improved.

  With reference to FIG. 1C, the configuration of still another form of the circuit device 10 will be described. The basic configuration of the circuit device 10 shown in FIG. 1 is the same as that shown in FIG. 1A. Here, the circuit element 13 is mounted face-down, and the first device is connected via the bump electrode 15A. It is electrically connected to the conductive wiring layer 12A.

An advantage of using the interlayer insulating layer 11 made of a thermoplastic resin when the circuit element 13A is mounted face down as described above will be described. When the circuit element 13A, which is a semiconductor element having an electric circuit formed on the surface, is mounted on the conductive wiring layer 12 face down, the electric circuit and the circuit element 13 are compared with the case where the circuit element 13 is mounted face up. The distance from the conductive wiring layer 12 is reduced. In addition, since a resin layer is interposed between the circuit element 13A and the conductive wiring layer, if an electric signal flows through both the circuit element 13A and the conductive wiring layer 12, wiring capacitance is generated, which has an adverse effect. Effect. Further, since the size of the wiring capacitance is inversely proportional to the distance between the electric circuit of the circuit element 13A and the conductive wiring layer 12, when the circuit element 13A is mounted face down, the problem of wiring capacitance becomes large. In the present invention, an interlayer insulating layer 11 made of a thermoplastic resin such as a liquid crystal polymer having a low dielectric constant is provided between the conductive wiring layers 12. Therefore, even when the circuit element 13A is mounted face-down, the generation of wiring capacitance can be suppressed. Here, the dielectric constant of the liquid crystal polymer is about 3.

  An example of a planar structure of the circuit device 10 of the present invention will be described with reference to FIG. First, the pattern indicated by the solid line is the first conductive wiring layer 12A, and the pattern indicated by the dotted line is the second conductive wiring layer 12B. The first conductive wiring layer 12A forms bonding pads so as to surround the circuit element 13, and a part of the first conductive wiring layer 12A is arranged in two stages and corresponds to the circuit element 13 having multiple pads. The first conductive wiring layer 12A is connected to the corresponding electrode pad of the circuit element 13 by the metal thin wire 15, and a large number of first conductive wiring layers 12A formed in a fine pattern are extended under the circuit element 13, It is connected to the second conductive wiring layer 12B by the multilayer connection means 14 indicated by a black circle.

  With such a structure, even a semiconductor element having 200 or more pads can be extended in a multilayer wiring structure to a desired second conductive wiring layer 12B using the fine pattern of the first conductive wiring layer 12A. The external electrode provided on the conductive wiring layer 12B can be connected to an external circuit.

  A feature of the present invention resides in that a thermoplastic resin is employed as the material of the interlayer insulating layer 11. The entire circuit device 10 of the present invention is supported by a sealing resin 17 made of a thermosetting resin. Further, since the thermal expansion coefficient is greatly different between the sealing resin 17 made of an organic material and the circuit element 13 made of silicon, both of them exhibit different expansion amounts due to temperature changes under use conditions. Specifically, the thermal expansion coefficient of the sealing resin 17 is 20 to 60 ppm / ° C., whereas the thermal expansion coefficient of the circuit element 13 is 4 ppm / ° C. Therefore, in the present embodiment, by forming the interlayer insulating layer 11 formed between the first conductive wiring layer 12A and the second conductive wiring layer 12B with a thermoplastic resin having flexibility at high temperatures, Generation of internal stress in the circuit device 10 is suppressed. Specifically, the interlayer insulating layer 11 positioned below the circuit element 13 expands in accordance with the expansion amount of the circuit device 13, and the interlayer insulating layer 11 positioned below the sealing resin 17 includes the sealing resin 19. It expands according to the amount of expansion. Therefore, it is possible to prevent a decrease in the reliability of the circuit device 10 due to thermal stress.

  Further, the present invention is characterized in that a liquid crystal polymer is employed as a thermoplastic resin that is a material of the interlayer insulating layer 11. The thermal expansion coefficient of the liquid crystal polymer can be formed at 4 ppm / ° C., and is equivalent to silicon forming the semiconductor element as the circuit element 13, so that the interlayer insulating layer 11 and the circuit element 13 are formed even at high temperatures. Shows the same amount of expansion. Therefore, the thermal stress generated between the circuit element 13 and other components can be further relaxed. In addition, since the liquid crystal polymer is a material having excellent gas barrier properties, it is possible to prevent moisture and the like from entering the inside from the outside of the apparatus.

  With reference to FIG. 3, the configuration of another form of circuit device will be described. The circuit device 10 shown in FIG. 1 includes a conductive wiring layer 12 stacked in multiple layers via a plurality of interlayer insulating layers 11, a circuit element 13 fixed on the uppermost conductive wiring layer 12, and an uppermost conductive layer. A sealing resin layer 17 that covers the wiring layer 12 and the circuit element 13, a multilayer connection means 14 that connects the conductive wiring layers 12 through the interlayer insulating layer 11 at desired locations, and a lowermost conductive wiring layer 12 And an external electrode 16 provided at a desired location, and at least the uppermost interlayer insulating layer 11 is made of a thermoplastic resin. Here, as an example, a circuit device having a three-layer structure including the first conductive wiring layer 12A to the third conductive wiring layer 12C will be described. Since the structure other than the wiring structure of the conductive wiring layer 12 is the same as that of the circuit device shown in FIG. 1, the description thereof will be omitted.

  The first conductive wiring layer 12A, the second conductive wiring layer 12B, and the third conductive wiring layer 12C forming the multilayer wiring structure include the first interlayer insulating layer 11A and the second interlayer insulating layer 11B. Have. The first interlayer insulating layer 11A, which is the uppermost interlayer insulating layer, is formed of a thermoplastic resin. From this, the first interlayer insulating layer is flexible at high temperatures even if both show different expansion coefficients at high temperatures due to the difference in thermal expansion coefficient between the circuit element 13 and the sealing resin layer 17. , Thermal stress can be relaxed. The thermoplastic resin used here is preferably a liquid crystal polymer.

  Moreover, the effect of alleviating thermal stress can be increased by forming all of the interlayer insulating layer 11 formed between the multilayer wiring layers with a thermoplastic resin. Specifically, by forming the first interlayer insulating layer 12A and the second interlayer insulating layer 12B with thermoplasticity, the internal stress caused by the difference in thermal expansion coefficient between the sealing resin 17 and the circuit element 13 is reduced. In addition to being able to be suppressed, the generation of internal stress due to the difference in thermal expansion coefficient between the conductive wiring layer 12 and the interlayer insulating layer 11 can also be suppressed.

  Furthermore, the second interlayer insulating layer 11B, which is the lowermost interlayer insulating layer, can be formed of a thermosetting resin. Here, the first interlayer insulating layer 11A is formed of a thermoplastic resin, and the second interlayer insulating layer 12B, which is the lowermost insulating layer, is formed of a thermosetting resin. In this manner, by forming the second interlayer insulating layer 12B with a thermosetting resin, the thermosetting resin does not soften even at high temperatures, so that the rigidity of the entire apparatus can be ensured.

(Second Embodiment Explaining Circuit Device Manufacturing Method)
A method for manufacturing a circuit device according to the present invention will be described with reference to FIGS. In this embodiment, a method for manufacturing the circuit device shown in FIG. 1 will be described. Further, the method for manufacturing the circuit device shown in FIG. 3 is similar to the steps other than the step of forming the multilayer wiring.

  The method of manufacturing a circuit device according to the present invention includes a step of preparing an insulating resin sheet 21 in which a first conductive film 23 and a second conductive film 24 are bonded with an interlayer insulating layer 22, and a desired portion of the insulating resin sheet 21. A step of forming a through hole 31 in the first conductive film 23 and the interlayer insulating layer 22; and a multilayer connection means 14 is formed in the through hole 31 to electrically connect the first conductive film 23 and the second conductive film 24. A step of connecting, a step of forming the first conductive wiring layer 12A by etching the first conductive film 23 into a desired pattern, and a circuit element 13 which is electrically insulated on the first conductive wiring layer 12A. , The step of covering the first conductive wiring layer 12A and the circuit element 13 with the sealing resin layer 17, and the second conductive wiring layer 12B by etching the second conductive film 24 into a desired pattern. The process of forming. Each step will be described below.

  The first step of the present invention is to prepare an insulating resin sheet 21 in which a first conductive film 23 and a second conductive film 24 are bonded with an interlayer insulating layer 22 as shown in FIG.

  The surface of the insulating sheet 21 is formed with the first conductive film 23 over substantially the entire area, and the second conductive film 24 is formed over the entire area of the back surface. The material of the interlayer insulating layer 22 is made of an insulating material made of a thermoplastic resin such as a liquid crystal polymer. Further, the first conductive film 23 and the second conductive film 24 are preferably made of Cu as a main material or a known lead frame material, and an interlayer insulating layer is formed by a plating method, a vapor deposition method or a sputtering method. A metal foil covered with 22 or formed by a rolling method or a plating method may be attached. The insulating sheet 21 may be formed by a casting method. The manufacturing method will be briefly described below. First, a paste-like thermoplastic resin is applied on the flat film-like first conductive film 23, and a paste-like thermoplastic resin is also applied on the flat film-like second conductive film 24. When the two thermoplastic resins are semi-cured and then bonded together, the insulating sheet 21 is completed.

  In the case of a casting method in which a paste is applied to form a sheet, the film thickness is about 10 μm to 100 μm. When formed as a sheet, a commercially available product has a minimum film thickness of 25 μm. In consideration of thermal conductivity, a filler may be mixed therein. As the material, glass, Si oxide, aluminum oxide, Al nitride, Si carbide, boron nitride or the like can be considered.

  In the second step of the present invention, as shown in FIG. 5, through holes 31 are formed in the first conductive film 23 and the interlayer insulating layer 22 at desired locations on the insulating sheet 21, and the second conductive film 24 is selectively formed. To be exposed to.

  Only the portion of the first conductive film 23 where the through hole 31 is formed is exposed and the entire surface is covered with a photoresist. Then, the first conductive film 23 is etched through this photoresist. Since the first conductive film 23 is mainly composed of Cu, the etching solution is chemically etched using ferric chloride or cupric chloride. The opening diameter of the through hole 31 varies depending on the resolution of photolithography, but is about 50 to 100 μm here. In this etching, the second conductive film 24 is covered with an adhesive sheet or the like to be protected from the etching solution. However, as long as the second conductive film 24 itself is sufficiently thick and can maintain flatness even after etching, it may be slightly etched.

  Subsequently, after removing the photoresist, using the first conductive film 23 as a mask, the interlayer insulating layer 22 immediately below the through hole 31 is removed by a laser to expose the second conductive film 24 at the bottom of the through hole 31. . As the laser, a carbon dioxide laser is preferable. In addition, after the insulating resin is evaporated by the laser, if there is a residue at the bottom of the opening, the residue is removed by wet etching with sodium permanganate or ammonium persulfate.

  The third step of the present invention is to form the multilayer connection means 14 in the through hole 31 and electrically connect the first conductive film 23 and the second conductive film 24 as shown in FIG.

  A plating film, which is a multilayer connection means 14 for electrically connecting the second conductive film 24 and the first conductive film 23, is formed on the entire surface of the first conductive film 23 including the through hole 31. This plated film is formed by both electroless plating and electrolytic plating. Here, Cu of about 2 μm is formed on the entire surface of the first conductive film 23 including at least the through holes 31 by electroless plating. As a result, the first conductive film 23 and the second conductive film 24 are electrically connected. Therefore, electrolytic plating is performed again using the first and second conductive films 3 and 4 as electrodes, and approximately 20 μm of Cu is plated. To do. Thereby, the through-hole 31 is embedded with Cu, and the multilayer connection means 14 is formed. The plating film is Cu here, but Au, Ag, Pd or the like may be used. Alternatively, partial plating may be performed using a mask.

  Next, referring to FIG. 2, the first conductive film 23 is etched into a desired pattern to form the first conductive wiring layer 12A. When the first conductive film 23 is covered with a photoresist having a desired pattern and a wiring as shown in FIG. 2 is formed, the bonding pad portion and the first conductive wiring layer 12A extending from the center to the bonding pad portion are formed. It is formed by chemical etching. Since the first conductive film 23 is mainly composed of Cu, ferric chloride or cupric chloride may be used as the etching solution.

  Subsequently, referring to FIG. 7, a portion to be a bonding pad of first conductive wiring layer 12 </ b> A is exposed and the other portion is covered with overcoat resin 18. As the overcoat resin 18, an epoxy resin or the like dissolved in a solvent is attached by screen printing and cured. Alternatively, a dry film made of resin is attached. As the resin used here, a thermosetting resin or a thermoplastic resin can be used. Further, as the material of the overcoat resin 18, a photosensitive resin or a non-photosensitive resin can be used. Further, in order to expose the conductive wiring layer at the location to be the bonding pad, the overcoat resin on the upper portion is partially removed.

  Next, as shown in FIG. 8, a plating film of Au, Ag, or the like is formed on the bonding pad in consideration of bonding properties. This plating film is selectively deposited on the bonding pad by electroless plating using the overcoat resin 18 as a mask, or is deposited by electroplating using the second conductive film 24 as an electrode.

  The fourth step of the present invention is to electrically insulate the circuit element 13 on the first conductive wiring layer 12A as shown in FIG.

  The circuit element 13 is a semiconductor element here, and is die-bonded on the overcoat resin 18 via an insulating adhesive resin or the like as a bare chip. Since the circuit element 13 and the first conductive wiring layer 12A below the circuit element 13 are electrically insulated by the overcoat resin 18, the first conductive wiring layer 12A can be freely wired under the circuit element 13, and the multilayer wiring The structure can be realized.

  In addition, each electrode pad of the circuit element 13 is connected to the bonding pad 10 which is a part of the first conductive wiring layer 12A provided in the periphery by a thin metal wire 15. The circuit element 13 may be mounted face down. In this case, solder balls and bumps are provided on the surface of each electrode pad of the circuit element 13, and electrodes similar to the bonding pads are provided on the surface of the first conductive wiring layer 12A corresponding to the position of the solder balls.

  The fifth step of the present invention is to cover the first conductive wiring layer 12A and the circuit element 13 with a sealing resin layer 17 as shown in FIG.

  The insulating sheet 21 is set in a molding apparatus and performs resin molding. As a molding method, transfer molding, injection molding, coating, dipping and the like are also possible. In the present invention, resin sealing is performed by transfer molding using a thermoplastic resin.

  Referring to FIG. 10A, in this step, the insulating sheet 21 needs to be in flat contact with the lower mold of the mold cavity, but the thick second conductive film 24 performs this function. In addition, even after removal from the mold cavity, the flatness of the package is maintained by the second conductive film 24 until the shrinkage of the sealing resin layer 17 is completely completed. That is, the role of mechanical support of the insulating sheet 21 up to this step is played by the second conductive film 24.

  Referring to FIG. 10B, in this step, a block in which a large number of circuit elements 13 are fixed in a matrix is formed on the insulating sheet 21, and this block is shared by a single mold. Molded. In the figure, a plurality of (four in this case) blocks are provided separately on one insulating sheet 21, and each block is resin-sealed with one sealing resin layer 17. Therefore, it is possible to mold a large number of circuit devices using one mold, and it is possible to save the cost of newly creating a mold according to the size and shape of the circuit device to be manufactured. The amount of resin used can be reduced.

  The sixth step of the present invention is to form the second conductive wiring layer 12B by etching the second conductive film 24 into a desired pattern, as shown in FIG.

  The second conductive film 24 is covered with a photoresist having a desired pattern, and the second conductive wiring layer 12B is formed by chemical etching. For example, the second conductive wiring layer 12B is arranged at a constant interval as shown in FIG. 2, and each is electrically connected to the first conductive wiring layer 12A via the multilayer connection means 14 to form a multilayer wiring structure. Realized.

  Next, the second conductive wiring layer 15 exposes a portion where the external electrode 16 is to be formed and is screen-printed with an epoxy resin or the like dissolved in a solvent, and is covered with the overcoat resin 18 for the most part. Next, the external electrode 16 is simultaneously formed on the exposed portion by reflow of solder. Finally, since many circuit devices are formed in the insulating sheet 21 in a matrix, the sealing resin layer 17 and the insulating sheet 21 are diced to separate them into individual circuit devices. The circuit device shown in FIG. 1 is manufactured through the above steps.

  According to the present invention, the following effects can be achieved.

First, by forming the interlayer insulating layer 11 forming the multilayer wiring with a thermoplastic resin, the sealing resin layer 17 made of a thermosetting resin and the circuit element 13 caused by the temperature rise under the usage conditions. Due to the difference in thermal expansion coefficient, it is possible to prevent internal stress from occurring at high temperatures.

  Second, by forming the interlayer insulating layer 11 made of a thermoplastic resin from a liquid crystal polymer, it is possible to prevent moisture and the like from entering the circuit device.

  Third, when two or more interlayer insulating layers 11 are used, the uppermost interlayer insulating layer 11 is formed of a thermoplastic resin, and the lowermost interlayer insulating layer 11 is formed of a thermosetting resin. As a result, internal stress at high temperatures can be suppressed, and the rigidity of the entire apparatus can be secured.

  According to the present invention, by forming an interlayer insulating layer that insulates each conductive wiring layer from a thermoplastic resin, the interlayer insulating layer functions as a stress relieving / buffering material at high temperatures, thereby improving the reliability of the circuit device. Can be improved.

FIG. 3 is a cross-sectional view (A), a cross-sectional view (B), and a cross-sectional view (C) illustrating a circuit device of the present invention. It is a top view explaining the circuit device of the present invention. It is sectional drawing explaining the circuit apparatus of this invention. It is sectional drawing explaining the manufacturing method of the circuit apparatus of this invention. It is sectional drawing explaining the manufacturing method of the circuit apparatus of this invention. It is sectional drawing explaining the manufacturing method of the circuit apparatus of this invention. It is sectional drawing explaining the manufacturing method of the circuit apparatus of this invention. It is sectional drawing explaining the manufacturing method of the circuit apparatus of this invention. It is sectional drawing explaining the manufacturing method of the circuit apparatus of this invention. It is sectional drawing (A) and a top view (B) explaining the manufacturing method of the circuit apparatus of this invention. It is sectional drawing explaining the manufacturing method of the circuit apparatus of this invention. It is a figure explaining the conventional semiconductor device. It is a figure explaining the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Circuit apparatus 11 Interlayer insulation layer 11A 1st interlayer insulation layer 11B 2nd interlayer insulation layer 12A 1st conductive wiring layer 12B 2nd conductive wiring layer 12C 3rd conductive wiring layer 13 Circuit element 14 Multilayer connection means 15 Metal thin wire 16 External electrode 17 Sealing resin layer 18 Overcoat resin

Claims (5)

A multilayer substrate for mounting a semiconductor element provided with multilayer conductive wiring,
The conductive wiring is laminated in multiple layers via a plurality of interlayer insulating layers,
Multi-layer connection means for connecting the conductive wirings through the interlayer insulating layer at desired locations;
Of the plurality of interlayer insulation layers, the uppermost interlayer insulation layer is made of a thermoplastic resin,
A multilayer substrate for mounting a semiconductor element, wherein the interlayer insulating layer below the uppermost interlayer insulating layer is made of a thermosetting resin. The thermoplastic resin is ABS resin, polypropylene, polyethylene, polystyrene, acrylic, polyethylene terephthalate, polyphenylene ether, nylon, polyamide, polycarbonate, polyacetal, polybutylene terephthalate, polyphenylene sulfide, polyether ether ketone, liquid crystal polymer, fluororesin, urethane The multilayer substrate for mounting a semiconductor element according to claim 1, which is selected from a resin and an elastomer. A semiconductor element mounting board provided with a multilayer conductive wiring to which the semiconductor element is electrically connected,
The conductive wiring is laminated in multiple layers via a plurality of interlayer insulating layers,
Multi-layer connection means for connecting the conductive wirings through the interlayer insulating layer at desired locations;
Of the plurality of interlayer insulation layers, the uppermost interlayer insulation layer is made of a thermoplastic resin,
The interlayer insulating layer below the uppermost interlayer insulating layer is made of a thermosetting resin,
A semiconductor element mounting multilayer substrate, wherein the semiconductor element is mounted face-down. The thermoplastic resin is ABS resin, polypropylene, polyethylene, polystyrene, acrylic, polyethylene terephthalate, polyphenylene ether, nylon, polyamide, polycarbonate, polyacetal, polybutylene terephthalate, polyphenylene sulfide, polyether ether ketone, liquid crystal polymer, fluororesin, urethane 4. The semiconductor element mounting multilayer substrate according to claim 3, which is selected from a resin and an elastomer. 4. The semiconductor element mounting multilayer substrate according to claim 3, wherein the uppermost interlayer insulating layer is softened by heat generation of the semiconductor element, so that thermal stress generated between the semiconductor element and the semiconductor element for mounting is absorbed.

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