JP2841459B2 - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JP2841459B2 JP2841459B2 JP1100425A JP10042589A JP2841459B2 JP 2841459 B2 JP2841459 B2 JP 2841459B2 JP 1100425 A JP1100425 A JP 1100425A JP 10042589 A JP10042589 A JP 10042589A JP 2841459 B2 JP2841459 B2 JP 2841459B2
- Authority
- JP
- Japan
- Prior art keywords
- opening
- island
- integrated circuit
- hybrid integrated
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Structure Of Printed Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は混成集積回路に関する。Description: FIELD OF THE INVENTION The present invention relates to a hybrid integrated circuit.
〔従来の技術〕 従来の混成集積回路は、第２図（ａ），（ｂ）に示す
ように、選択的に開孔部を設けたアイランド２の外周に
リード３を配列して設け、前記開孔部に対応する開孔部
を有する絶縁基板の表面にパターニングした配線６を設
けた回路基板をアイランド２及びリード３の先端部を含
み前記開孔部を互に整合して上下より挟みつけ接着剤に
より固着する。次に、前記回路基板及びアイランド２を
貫通する前記開孔部の内壁に金属層８を設けて配線６と
リード３を電気的に接続し且つ上面及び下面の回路基板
の配線６を接続する。次に、回路基板上に半導体チップ
９及び受動素子10を搭載して配線６に電気的に接続し、
上面及び下面の回路基板を含んで樹脂体11により封止
し、混成集積回路を構成していた。[Prior Art] As shown in FIGS. 2 (a) and 2 (b), a conventional hybrid integrated circuit is arranged such that leads 3 are arranged and arranged on the outer periphery of an island 2 in which openings are selectively provided. A circuit board provided with patterned wiring 6 on the surface of an insulating substrate having an opening corresponding to the opening is sandwiched from above and below with the openings including the tip of the island 2 and the lead 3 aligned with each other. Fix with an adhesive. Next, a metal layer 8 is provided on the inner wall of the opening that penetrates the circuit board and the island 2 to electrically connect the wiring 6 to the lead 3 and to connect the wiring 6 of the upper and lower circuit boards. Next, the semiconductor chip 9 and the passive element 10 are mounted on the circuit board and are electrically connected to the wiring 6,
The hybrid integrated circuit is formed by sealing the upper and lower circuit boards including the circuit board with the resin body 11.
上述した従来の混成集積回路は回路基板及びアイラン
ドを整合して貫通する開孔部を各品種に対応した配線パ
ターンに従って設けているため各品種のそれぞれが異な
った位置に開孔部を設ける必要があり、従って汎用性が
ないという欠点がある。In the above-described conventional hybrid integrated circuit, openings are provided in accordance with a wiring pattern corresponding to each type because the openings penetrating the circuit board and the island in alignment with each other need to be provided at different positions for each type. And therefore lacks versatility.
本発明の混成集積回路は、行列状に第１の開孔部を有
するアイランドと、前記アイランドの外周に設けたリー
ドと、絶縁基板に前記第１の開孔部に対応する第２の開
孔部を設け且つ表面にパターニングした配線を有し前記
アイランド及び前記リードの先端部の上面及び下面に前
記第１の開孔部と第２の開孔部のそれぞれを整合させて
固着した回路基板と、所定の前記第１及び第２の開孔部
の内側に設けて前記配線と前記リードを接続し且つ上面
及び下面の回路基板の配線間を接続する金属層とを有す
る。A hybrid integrated circuit according to the present invention includes an island having a first opening in a matrix, a lead provided on an outer periphery of the island, and a second opening corresponding to the first opening in an insulating substrate. A circuit board provided with a portion and having patterned wiring on the surface and having the first opening and the second opening aligned and fixed to the upper and lower surfaces of the tip of the island and the lead, respectively; A metal layer provided inside the predetermined first and second openings to connect the wiring to the leads and to connect wirings on the upper and lower circuit boards.
次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図（ａ），（ｂ）は本発明の一実施例を示す一部
切欠平面図及び断面模式図である。1 (a) and 1 (b) are a partially cutaway plan view and a schematic sectional view showing an embodiment of the present invention.
第１図（ａ），（ｂ）に示すように、行列状に開孔部
１を配列して設けたアイランド２の外周にリード３を配
列して設ける。次に、絶縁基板４に開孔部１と対応する
開孔部５を設け、且つ、一方の面にパターニングした配
線６を有する回路基板をアイランド２及びリード３の先
端部の上下の面にそれぞれ開孔部１と開孔部５を整合さ
せて接着剤７で固着する。次に、所定の開孔部1,5の内
側に金属層８を設けて配線６とリード３を電気的に接続
し、且つ、上面と下面の回路基板の配線６を電気的に接
続し、上面には半導体チップ９を搭載し、下面には受動
素子10を搭載して配線６とそれぞれ接続する。次に、上
面及び下面の回路基板を含んで樹脂体11により封止し混
成集積回路を構成する。As shown in FIGS. 1 (a) and 1 (b), leads 3 are arranged and provided on the outer periphery of an island 2 in which openings 1 are arranged in a matrix. Next, an opening 5 corresponding to the opening 1 is provided in the insulating substrate 4, and a circuit board having a patterned wiring 6 on one surface is placed on the upper and lower surfaces of the tip of the island 2 and the lead 3, respectively. The opening 1 and the opening 5 are aligned and fixed with an adhesive 7. Next, a metal layer 8 is provided inside the predetermined openings 1 and 5 to electrically connect the wiring 6 to the leads 3 and electrically connect the wiring 6 on the upper and lower circuit boards. A semiconductor chip 9 is mounted on the upper surface, and a passive element 10 is mounted on the lower surface and connected to the wiring 6 respectively. Next, the circuit board including the upper and lower circuit boards is sealed with the resin body 11 to form a hybrid integrated circuit.
ここで、アイランド２及び絶縁基板４に行列状に設け
た開孔部1,5により回路基板は配線パターンの変更のみ
で多機種の混成集積回路が構成可能となり、汎用性の向
上と製造工程の簡略化が実できる。Here, the openings 1 and 5 provided in the island 2 and the insulating substrate 4 in a matrix form enable the circuit board to constitute a multi-type hybrid integrated circuit only by changing the wiring pattern, thereby improving the versatility and improving the manufacturing process. Simplification can be achieved.
以上説明したように本発明は、回路基板とアイランド
部の双方に互に整合した位置関係を有する開孔部をあら
かじめ設けることにより、回路パターンの変更のみによ
り多品種対応が可能となる。従って汎用性を持たせられ
ることにより製造工程の簡略化が実現できるという効果
がある。As described above, according to the present invention, by providing in advance the opening portions having a positional relationship aligned with each other on both the circuit board and the island portion, it is possible to cope with a variety of products only by changing the circuit pattern. Therefore, there is an effect that simplification of the manufacturing process can be realized by giving versatility.
第１図（ａ），（ｂ）は本発明の一実施例を示す一部切
欠平面図及び断面模式図、第２図（ａ），（ｂ）は従来
の混成集積回路の一部切欠平面図及び断面模式図であ
る。 １……開孔部、２……アイランド、３……リード、４…
…絶縁基板、５……開孔部、６……配線、７……接着
剤、８……金属層、９……半導体チップ、10……受動素
子、11……樹脂体。1 (a) and 1 (b) are a partially cutaway plan view and a schematic sectional view showing an embodiment of the present invention, and FIGS. 2 (a) and (b) are partially cutaway planes of a conventional hybrid integrated circuit. It is a figure and a schematic cross section. 1 ... opening, 2 ... island, 3 ... lead, 4 ...
... Insulating substrate, 5 ... opening, 6 ... wiring, 7 ... adhesive, 8 ... metal layer, 9 ... semiconductor chip, 10 ... passive element, 11 ... resin body.
Claims (1)
と、前記アイランドの外周に設けたリードと、絶縁基板
に前記第１の開孔部に対応する第２の開孔部を設け且つ
表面にパターニングした配線を有し前記アイランド及び
前記リードの先端部の上面及び下面に前記第１の開孔部
と第２の開孔部のそれぞれを整合させて固着した回路基
板と、所定の前記第１及び第２の開孔部の内側に設けて
前記配線と前記リードを接続し且つ上面及び下面の回路
基板の配線間を接続する金属層とを有することを特徴と
する混成集積回路。An island having a first opening in a matrix, a lead provided on an outer periphery of the island, and a second opening corresponding to the first opening are provided on an insulating substrate. A circuit board having patterned wiring on the surface and fixed to the upper surface and the lower surface of the tip of the island and the lead by aligning the first opening and the second opening, respectively; A hybrid integrated circuit, comprising: a metal layer provided inside the first and second openings to connect the wiring to the leads and to connect between wirings on a circuit board on upper and lower surfaces.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1100425A JP2841459B2 (en) | 1989-04-19 | 1989-04-19 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1100425A JP2841459B2 (en) | 1989-04-19 | 1989-04-19 | Hybrid integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02278756A JPH02278756A (en) | 1990-11-15 |
| JP2841459B2 true JP2841459B2 (en) | 1998-12-24 |
Family
ID=14273611
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1100425A Expired - Lifetime JP2841459B2 (en) | 1989-04-19 | 1989-04-19 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2841459B2 (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52136144U (en) * | 1976-04-12 | 1977-10-15 | ||
| JPS5629975U (en) * | 1979-08-15 | 1981-03-23 | ||
| JPS62214688A (en) * | 1986-03-14 | 1987-09-21 | 三菱電機株式会社 | Ceramic substrate for double-sided printed wiring board |
-
1989
- 1989-04-19 JP JP1100425A patent/JP2841459B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02278756A (en) | 1990-11-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9633968B2 (en) | Microelectronic packages having cavities for receiving microelectronic elements | |
| KR970003913B1 (en) | Surface mounting method of semiconductor integrated device | |
| KR100386995B1 (en) | Semiconductor device and its wiring method | |
| US3374533A (en) | Semiconductor mounting and assembly method | |
| JPS6290953A (en) | Resin-sealed semiconductor device | |
| US6201298B1 (en) | Semiconductor device using wiring tape | |
| JP2841459B2 (en) | Hybrid integrated circuit | |
| JPS58178544A (en) | Lead frame | |
| JPS5840614Y2 (en) | semiconductor equipment | |
| JP3692353B2 (en) | Assembling method of semiconductor device | |
| JP2559891Y2 (en) | Composite semiconductor device | |
| KR900002354Y1 (en) | Hybrid ic device | |
| JPH0142344Y2 (en) | ||
| JPH0249731Y2 (en) | ||
| JPH02125653A (en) | Hybrid integrated circuit device | |
| JP3405718B2 (en) | Semiconductor device | |
| JP2697345B2 (en) | Hybrid integrated circuit | |
| JPH0220864Y2 (en) | ||
| JPS6025909Y2 (en) | semiconductor equipment | |
| JPH03141666A (en) | Hybrid integrated circuit | |
| JPH0365251U (en) | ||
| JPS60110128A (en) | Multilayered substrate and wire bonding method thereof | |
| JPH01248533A (en) | Semiconductor integrated circuit | |
| JPH1074861A (en) | Semiconductor device | |
| JPH04106857U (en) | Jumper Chip |