JPH1074861A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH1074861A JPH1074861A JP23157896A JP23157896A JPH1074861A JP H1074861 A JPH1074861 A JP H1074861A JP 23157896 A JP23157896 A JP 23157896A JP 23157896 A JP23157896 A JP 23157896A JP H1074861 A JPH1074861 A JP H1074861A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- circuit board
- external connection
- bonding
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、回路基板の外部接
続端子が形成された面の裏面に半導体素子を搭載して成
る半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a semiconductor element mounted on a back surface of a circuit board on which external connection terminals are formed.
【０００２】[0002]
【従来の技術】従来、回路基板の外部接続端子が形成さ
れた面の裏面に半導体素子を搭載し、樹脂封止して成る
半導体装置は、図６に示す構成のものが知られている。
この半導体装置１００は一般にＢＧＡ（ball grid arra
y ）型半導体装置と呼ばれるものである。その構造は、
電極端子形成面１０４（図６の上面）の縁部に沿って複
数の電極端子１０２が形成された半導体素子１０６を、
例えばガラスエポキシ樹脂やＢＴレジン（ビスマレイミ
ド系樹脂）材等の剛性を有する回路基板１０８の配線パ
ターン形成面１１０（図６の上面）上に、電極端子形成
面１０４の裏面側をエポキシ系銀ベーストを用いて接着
して搭載する。そして、半導体素子１０６の各電極端子
１０２と回路基板１０８の配線パターン形成面１１０に
銅箔をエッチングして設けられた配線パターンのボンデ
ィング部１１２とを金線等のボンディングワイヤ１１４
を用いて接続した後に、半導体素子１０６、ボンディン
グワイヤ１１４、ボンディング部１１２を含めた回路基
板の半導体素子搭載面側を合成樹脂材料等の封止材１１
６を用いて封止する。なお、回路基板１０８の配線パタ
ーン形成面（半導体素子１０６の搭載面でもある）の裏
面には、スルーホールビア１１８を介してボンディング
部と電気的に接続されたランド部がアレイ状に配され、
そのランド部上に外部接続端子としてのはんだボール１
２０が取り付けられて、当該はんだボール１２０により
プリント基板（実装基板）にはんだボールを溶融して接
合する。配線パターンの表面及びランド部を除く回路基
板の裏面はソルダーレジスト１１１で被覆されている。
ＢＧＡ型半導体装置は、低容量、低インダクタンスとい
う電気的特性を有し、セラミック基板を用いた多層セラ
ミックＰＧＡ（Pin Grid Array）パッケージ等と比較し
て低コストであることが特徴となっている。なお、本例
では回路基板１０８の半導体素子１０６の搭載領域には
半導体素子１０６の熱を放散させるためのサーマルビア
１２２が形成されている。2. Description of the Related Art Conventionally, a semiconductor device having a structure shown in FIG. 6 is known in which a semiconductor element is mounted on a back surface of a surface of a circuit board on which external connection terminals are formed and sealed with a resin.
The semiconductor device 100 generally has a BGA (ball grid arra).
y) type semiconductor device. Its structure is
A semiconductor element 106 having a plurality of electrode terminals 102 formed along an edge of an electrode terminal formation surface 104 (the upper surface in FIG. 6)
For example, on the wiring pattern forming surface 110 (upper surface in FIG. 6) of the rigid circuit board 108 such as a glass epoxy resin or a BT resin (bismaleimide resin) material, the back surface side of the electrode terminal forming surface 104 is epoxy-based silver-based. It is mounted by bonding using. Then, each of the electrode terminals 102 of the semiconductor element 106 and the bonding portion 112 of the wiring pattern formed by etching the copper foil on the wiring pattern forming surface 110 of the circuit board 108 are bonded to bonding wires 114 such as gold wires.
Then, the semiconductor element mounting surface side of the circuit board including the semiconductor element 106, the bonding wire 114, and the bonding portion 112 is sealed with a sealing material 11 such as a synthetic resin material.
6 and sealing is performed. On the back surface of the wiring pattern forming surface of the circuit board 108 (which is also the mounting surface of the semiconductor element 106), land portions electrically connected to the bonding portions via through-hole vias 118 are arranged in an array.
Solder ball 1 as an external connection terminal on the land
20 is attached, and the solder ball 120 melts and joins the solder ball to a printed board (mounting board). The front surface of the wiring pattern and the back surface of the circuit board excluding the lands are covered with a solder resist 111.
The BGA type semiconductor device has electrical characteristics such as low capacitance and low inductance, and is characterized by a lower cost as compared with a multilayer ceramic PGA (Pin Grid Array) package using a ceramic substrate. In this example, a thermal via 122 for dissipating the heat of the semiconductor element 106 is formed in the mounting area of the semiconductor element 106 on the circuit board 108.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、上記の
従来の半導体装置には次の様な課題が有る。半導体装置
１００においてボンディング部１１２と電極端子１０２
とを接続するボンディングワイヤ１１４は、温度の変化
による伸縮等のストレスによって切断されないようにす
るため、ループ状に張る必要がある。このため、ループ
状に形成されたボンディングワイヤ１１４の上端は半導
体素子１０６の上面を越えて突出し、よってボンディン
グワイヤ１１４を覆う封止材１１６を厚くせざるを得
ず、半導体装置１００全体が厚くなってしまうという課
題がある。また、回路基板１０８はボンディング部１１
２の形成面とはんだボール（ランドに接合されたはんだ
ボール）１２０の形成面が同一面ではないため、回路基
板１０８にスルーホールビア１１８を形成し、ボンディ
ング部１１２とはんだボール１２０とを電気的に接続す
る必要がある。このため、回路基板などの製造工程が複
雑になり、製品コストが高くなるという課題がある。ま
た、半導体素子１０６が全体に封止されてしまうため、
半導体素子１０６の熱放散性が低下するという課題もあ
る。However, the above-mentioned conventional semiconductor device has the following problems. In the semiconductor device 100, the bonding portion 112 and the electrode terminal 102
The bonding wire 114 that connects the wires needs to be formed in a loop shape so as not to be cut by stress such as expansion and contraction due to a change in temperature. For this reason, the upper end of the bonding wire 114 formed in a loop shape protrudes beyond the upper surface of the semiconductor element 106, so that the encapsulant 116 covering the bonding wire 114 must be thickened, and the entire semiconductor device 100 becomes thicker. Problem. The circuit board 108 is connected to the bonding portion 11.
2 and the formation surface of the solder ball (solder ball joined to the land) 120 are not the same surface, a through-hole via 118 is formed in the circuit board 108, and the bonding portion 112 and the solder ball 120 are electrically connected. Need to be connected to For this reason, there is a problem that a manufacturing process of a circuit board or the like is complicated and a product cost is increased. In addition, since the semiconductor element 106 is completely sealed,
There is also a problem that the heat dissipation of the semiconductor element 106 is reduced.
【０００４】従って、本発明は上記課題を解決すべくな
され、その目的とするところは、厚さを薄くすることが
でき、製造が容易であり、かつ放熱性に優れた半導体装
置を提供することにある。SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a semiconductor device which can be reduced in thickness, is easy to manufacture, and has excellent heat dissipation. It is in.
【０００５】[0005]
【課題を解決するための手段】本発明は上記課題を解決
するために、電極端子が形成された半導体素子を一方の
面に外部接続端子を備えた回路基板の他方の面に搭載
し、該外部接続端子と前記電極端子とが電気的に接続さ
れて成る半導体装置において、前記半導体素子は、前記
電極端子が形成された面を前記回路基板に対向させて搭
載され、前記回路基板は、前記外部接続端子が形成され
た面に一端が前記外部接続端子と電気的に接続され、他
端にボンディング部が設けられた配線パターンが形成さ
れていると共に、前記半導体素子の前記電極端子の配列
に沿って複数の電極端子を一連に露出させる長孔が形成
され、かつ該長孔の開口周縁部に前記ボンディング部が
形成されて長孔の底部に露出する前記各電極端子とボン
ディング部とがボンディングワイヤにより電気的に接続
され、前記長孔内部および前記ボンディングが樹脂封止
されていることを特徴とする。この構成によれば、電極
端子とボンディング部を接続するボンディングワイヤを
長孔内において配線することができるので、ボンディン
グワイヤがループ状に形成されても外部接続端子の高さ
以下に押さえることができる。また半導体素子は全体が
樹脂封止される構造ではない。よって、半導体装置の薄
型化が図れる。また、配線パターンとボンディング部は
全て外部接続端子形成面側に形成されるため、表裏を連
絡するスルーホールビアを回路基板に形成する必要がな
い。このため、製造工程が簡略化できる。また、前記半
導体素子の側面も併せて樹脂封止するようにして、耐湿
性等を向上させるようにしてもよい。According to the present invention, in order to solve the above-mentioned problems, a semiconductor device having an electrode terminal formed thereon is mounted on the other surface of a circuit board provided with external connection terminals on one surface. In a semiconductor device in which an external connection terminal and the electrode terminal are electrically connected, the semiconductor element is mounted with a surface on which the electrode terminal is formed facing the circuit board, and the circuit board is One end is electrically connected to the external connection terminal on the surface on which the external connection terminal is formed, and a wiring pattern having a bonding portion provided on the other end is formed, and an arrangement of the electrode terminals of the semiconductor element is formed. A long hole for continuously exposing a plurality of electrode terminals is formed along the hole, and the bonding portion is formed at the periphery of the opening of the long hole, and the electrode terminal and the bonding portion exposed at the bottom of the long hole are bonded to each other. Are electrically connected by Inguwaiya, the long hole inside and the bonding is characterized in that it is sealed with a resin. According to this configuration, since the bonding wire for connecting the electrode terminal and the bonding portion can be wired in the elongated hole, even if the bonding wire is formed in a loop shape, the bonding wire can be suppressed to the height of the external connection terminal or less. . Further, the semiconductor element is not entirely structured by resin sealing. Therefore, the thickness of the semiconductor device can be reduced. Further, since the wiring pattern and the bonding portion are all formed on the external connection terminal forming surface side, it is not necessary to form a through-hole via connecting the front and back on the circuit board. Therefore, the manufacturing process can be simplified. Further, the side surfaces of the semiconductor element may be resin-sealed together to improve moisture resistance and the like.
【０００６】[0006]
【発明の実施の形態】以下、本発明に係る半導体装置の
好適な実施の形態を添付図面に基づいて詳細に説明す
る。半導体装置１０の概要構造は図１に示すように、電
極端子２６が図２のように周縁に形成された半導体素子
１６の面（電極端子形成面とも言う）３８を図３に示す
回路基板１８の外部接続端子２０が形成される面（外部
接続端子形成面とも言う）３２の裏面（半導体素子搭載
面とも言う）に接着して搭載し、外部接続端子２０に接
続された配線パターン２２のボンディング部２４と電極
端子２６とをボンディングワイヤ２８で接続して成るも
のである。Preferred embodiments of a semiconductor device according to the present invention will be described below in detail with reference to the accompanying drawings. As shown in FIG. 1, the schematic structure of the semiconductor device 10 is such that the surface (also referred to as an electrode terminal formation surface) 38 of the semiconductor element 16 in which the electrode terminals 26 are formed on the periphery as shown in FIG. The bonding is performed by bonding the wiring pattern 22 connected to the external connection terminal 20 by mounting it on the back surface (also referred to as a semiconductor element mounting surface) of the surface 32 (where the external connection terminal is formed) 32 on which the external connection terminal 20 is formed. The part 24 and the electrode terminal 26 are connected by a bonding wire 28.
【０００７】ここで本実施の形態では、半導体素子１６
は一例として図２に示すように外形が方形に形成され
て、電極端子２６は電極端子形成面３８上の４つの各縁
部に２列に配列されて形成されている。以下、説明のた
めに、半導体素子１６の各縁部に配列された複数の電極
端子２６をそれぞれ電極端子群１２と言う。本実施の形
態の半導体素子１６には電極端子群１２が４群形成され
ている。なお、電極端子群１２は１列に配列された電極
端子２６で形成されるものでも良いし、また半導体素子
１６の対向する１組の縁部に２群形成されているもので
も良い。また、後述するように電極端子形成面３８上の
中央部分に１群形成されているものでも良い。In this embodiment, the semiconductor device 16
As an example, as shown in FIG. 2, the outer shape is formed in a square shape, and the electrode terminals 26 are formed in two rows at each of four edges on the electrode terminal formation surface 38. Hereinafter, for the sake of explanation, the plurality of electrode terminals 26 arranged on each edge of the semiconductor element 16 will be referred to as an electrode terminal group 12 respectively. Four electrode terminal groups 12 are formed in the semiconductor element 16 of the present embodiment. The electrode terminal group 12 may be formed by the electrode terminals 26 arranged in one row, or may be formed by two groups at one set of opposing edges of the semiconductor element 16. Further, as will be described later, one group may be formed in a central portion on the electrode terminal forming surface 38.
【０００８】そして本発明の特徴点の概要は、まず第１
に、回路基板１８の外部接続端子形成面３２に一端が外
部接続端子２０に電気的に接続され、他端にボンディン
グ部２４が設けられた配線パターン２２を形成すると共
に、半導体素子１６の各電極端子群１２に沿って、各電
極端子群１２を構成する複数の電極端子２６を一連に露
出させる長孔３０を回路基板１８に設けて、搭載された
半導体素子１６の電極端子２６が長孔３０部分から外部
接続端子形成面３２側に露出する構成とする。そしてこ
の長孔３０内でボンディングワイヤ２８を配線する点で
ある。第２に、長孔３０内にのみポッティング剤３６を
塗布して半導体素子１６の外面全体を封止しないように
する点である。そしてこの２つの特徴点を有することに
よって、半導体装置１０の薄型化及び熱放散性（放熱
性）の向上を達成したことにある。なお、半導体装置１
０の薄型化を図りながら、併せて半導体素子１６と回路
基板１８との間の耐湿性を向上させるべく、さらに半導
体素子１６の側面と回路基板１８の半導体素子搭載面３
４との境界部分（図１の点線で示される部分）にポッテ
ィング剤３６を塗布し、当該境界部分の封止を行う構成
を採用してもよい。[0008] An outline of the features of the present invention is as follows.
The wiring pattern 22 having one end electrically connected to the external connection terminal 20 on the external connection terminal forming surface 32 of the circuit board 18 and the other end provided with the bonding portion 24 is formed. Along the terminal group 12, a long hole 30 for exposing a plurality of electrode terminals 26 constituting each electrode terminal group 12 in series is provided on the circuit board 18, and the electrode terminal 26 of the semiconductor element 16 mounted is formed with the long hole 30. A portion is exposed to the external connection terminal forming surface 32 side. The point is that the bonding wire 28 is wired in the elongated hole 30. Second, the potting agent 36 is applied only to the long holes 30 so as not to seal the entire outer surface of the semiconductor element 16. By having these two features, the semiconductor device 10 is made thinner and improved in heat dissipation (heat dissipation). The semiconductor device 1
In order to improve the moisture resistance between the semiconductor element 16 and the circuit board 18 while reducing the thickness of the semiconductor element 16 and the semiconductor element mounting surface 3 of the circuit board 18,
A configuration may be adopted in which a potting agent 36 is applied to a boundary portion (portion indicated by a dotted line in FIG. 1) with the fourth portion 4 to seal the boundary portion.
【０００９】各構成要素の詳細な構造と製法について説
明する。半導体素子１６はその外形が方形に形成され
て、電極端子形成面３８上の各縁部に電極端子群１２が
４群形成されている。また、回路基板１８は図１や図４
に示す構成を有し、その製造工程は、合成樹脂材料、例
えばガラスエポキシ樹脂やＢＴレジン材等を用いて形成
された剛性を有する絶縁基板４０の一方の面（外部接続
端子形成面３２となる面）に銅箔を貼着し、半導体素子
１６の各電極端子群１２に対応させて長孔３０を、ドリ
ル加工、ルータ加工又はプレス加工により明ける。長孔
３０は図３に示すように各電極端子群１２毎に独立した
孔に形成される。次に、銅箔をエッチングして配線パタ
ーン２２を形成し、さらにその上面に外部接続端子２０
を取り付けるためのランド部４１とボンディングワイヤ
２８を接続するボンディング部２４のみが露出するよう
にソルダレジスト層４２を塗布形成し、当該露出部分に
下地ニッケルと金めっきを施して形成される。The detailed structure and manufacturing method of each component will be described. The semiconductor element 16 has a rectangular outer shape, and four electrode terminal groups 12 are formed at each edge on the electrode terminal formation surface 38. Also, the circuit board 18 is provided in FIG.
In the manufacturing process, one surface (the external connection terminal forming surface 32) of a rigid insulating substrate 40 formed using a synthetic resin material, for example, a glass epoxy resin or a BT resin material is used. A copper foil is adhered to the surface (surface), and a long hole 30 is formed by drilling, routering or pressing in correspondence with each electrode terminal group 12 of the semiconductor element 16. The long holes 30 are formed as independent holes for each electrode terminal group 12 as shown in FIG. Next, the wiring pattern 22 is formed by etching the copper foil, and the external connection terminals 20 are further formed on the upper surface thereof.
The solder resist layer 42 is applied and formed so that only the bonding portion 24 connecting the bonding wire 28 and the land portion 41 for attaching the solder wire is exposed, and the exposed portion is formed by applying nickel base and gold plating.
【００１０】この配線パターン２２は各ランド部４１か
ら長孔３０の開口周縁部に向けて延びるように形成さ
れ、長孔３０の開口周縁部に至る各先端にはボンディン
グ部２４が開口周縁部に沿って形成されている。具体的
にはボンディング部２４は各長孔３０の対向する口縁部
分に１列に配列されている。また、各ランド部４１は外
部接続端子形成面３２上に全領域にわたり配置されてい
る。これら配線パターン２２とランド部４１は外部接続
端子形成面３２にのみ形成されており、半導体素子搭載
面３４上には形成されていない。なお、ランド部４１は
外部接続端子形成面３２上に全領域にわたり配置されて
おり、本実施の形態では外部接続端子２０として、一例
としてはんだボールがランド部４１に接合されている
が、その他外部接続端子２０としてランド部４１をその
まま使用したり、またピンを立設して接合する構造も採
用し得る。また、上述した製造工程に代えて、半導体素
子１６を搭載する前に予めランド部４１に外部接続端子
２０を接合しておく場合もあるので、回路基板１８とは
外部接続端子２０が未だ接合されていないものと、既に
接合されたものの両方を含むものとする。The wiring pattern 22 is formed so as to extend from each land portion 41 toward the peripheral edge of the opening of the elongated hole 30. At each end reaching the peripheral edge of the opening of the elongated hole 30, a bonding portion 24 is provided at the peripheral edge of the opening. It is formed along. Specifically, the bonding portions 24 are arranged in a row at the edge portions of the long holes 30 facing each other. Each land portion 41 is arranged over the entire area on the external connection terminal forming surface 32. These wiring patterns 22 and land portions 41 are formed only on the external connection terminal forming surface 32, and are not formed on the semiconductor element mounting surface 34. The land portion 41 is arranged over the entire area of the external connection terminal forming surface 32. In the present embodiment, as the external connection terminal 20, a solder ball is joined to the land portion 41 as an example. The land portion 41 may be used as the connection terminal 20 as it is, or a structure in which pins are erected and joined may be employed. In addition, instead of the above-described manufacturing process, the external connection terminals 20 may be bonded to the lands 41 in advance before the semiconductor element 16 is mounted. Therefore, the external connection terminals 20 are still bonded to the circuit board 18. Not included and those already joined.
【００１１】半導体装置１０の製造工程について説明す
る。第１に、上記回路基板１８の半導体素子搭載面３４
にエポキシ系の接着剤４４を塗布し、その後に長孔３０
と電極端子群１２が対応するように半導体素子１６を位
置決めしてその電極端子形成面３８を半導体素子搭載面
３４に接着し、半導体素子１６を回路基板１８上に固定
する。位置決めされて搭載された半導体素子１６の各電
極端子群１２は長孔３０内に位置して露出した状態とな
る。第２に、電極端子群１２の各電極端子２６とボンデ
ィング部２４とを金やアルミニウム製のボンディングワ
イヤ２８を用いてワイヤボンディングを行う。ボンディ
ングされたボンディングワイヤ２８は温度環境の変化に
よる伸縮を考慮してループ状に形成されるが、従来例と
比べて回路基板１８に設けられた長孔３０内に形成され
るため、長孔３０から突出するループ状の上端部分の高
さを、外部接続端子２０の高さより低く抑えることがで
きる。The manufacturing process of the semiconductor device 10 will be described. First, the semiconductor element mounting surface 34 of the circuit board 18
An epoxy adhesive 44 is applied to the
The semiconductor element 16 is positioned so that the electrode terminals 12 correspond to the semiconductor element 16, and the electrode terminal forming surface 38 is bonded to the semiconductor element mounting surface 34, and the semiconductor element 16 is fixed on the circuit board 18. Each electrode terminal group 12 of the semiconductor element 16 positioned and mounted is located in the elongated hole 30 and is exposed. Second, wire bonding is performed between each electrode terminal 26 of the electrode terminal group 12 and the bonding portion 24 using a bonding wire 28 made of gold or aluminum. The bonded bonding wire 28 is formed in a loop shape in consideration of expansion and contraction due to a change in temperature environment. However, since the bonding wire 28 is formed in the elongated hole 30 provided in the circuit board 18 as compared with the conventional example, the elongated hole 30 The height of the loop-shaped upper end portion protruding from the external connection terminal 20 can be suppressed to be lower than the height of the external connection terminal 20.
【００１２】第３に、半導体素子１６の電極端子形成面
３８を、湿気や汚染物質の付着等から防止するため、長
孔３０内にのみポッティング剤（一般には熱硬化性樹
脂）３６を塗布する。この工程により、長孔３０内に配
されたボンディングワイヤ２８もポッティング剤３６に
より同時に封止される。以上の工程により、半導体素子
１６の電極端子形成面３８の裏面が露出した半導体装置
１０が製造される。なお、回路基板１８と半導体素子１
６の接着部分の耐湿性をより向上させるため、同時に半
導体素子１６の側面、つまり半導体素子１６の側面と回
路基板１８の半導体素子搭載面３４との境界部分（図１
の点線部分）にポッティング剤３６を塗布して樹脂封止
するようにしても良い。Third, a potting agent (generally, a thermosetting resin) 36 is applied only to the long holes 30 in order to prevent the electrode terminal forming surface 38 of the semiconductor element 16 from adhering moisture and contaminants. . By this step, the bonding wires 28 arranged in the long holes 30 are simultaneously sealed by the potting agent 36. Through the above steps, the semiconductor device 10 in which the back surface of the electrode terminal forming surface 38 of the semiconductor element 16 is exposed is manufactured. The circuit board 18 and the semiconductor element 1
In order to further improve the moisture resistance of the adhesive portion 6, the side surface of the semiconductor element 16, that is, the boundary portion between the side surface of the semiconductor element 16 and the semiconductor element mounting surface 34 of the circuit board 18 (FIG.
(Dotted line portion) may be coated with a potting agent 36 and sealed with a resin.
【００１３】また、半導体素子１６の電極端子の構成は
上記の実施の形態のように、電極端子群１２が方形の電
極端子形成面３８の４つの縁部に沿って配置される場合
の他に、例えば図５に示すように一つの電極端子群１２
が電極端子形成面３８の中央部分に配置されるものでも
よい。この場合、当該半導体素子１６を搭載する回路基
板５２には、電極端子群１２に対応して開口する長孔３
０は一つだけ設けられる。この構成により、同様にして
ボンディングワイヤ２８をこの長孔３０内で配線するこ
とができ、長孔３０内にのみポッティング剤３６を塗布
することによって厚さの薄い半導体装置５０を実現でき
る。The structure of the electrode terminals of the semiconductor element 16 is the same as that of the above embodiment except that the electrode terminal group 12 is arranged along the four edges of the rectangular electrode terminal forming surface 38. For example, as shown in FIG.
May be arranged at the center of the electrode terminal forming surface 38. In this case, the circuit board 52 on which the semiconductor element 16 is mounted has a long hole 3 corresponding to the electrode terminal group 12.
Only one 0 is provided. With this configuration, the bonding wire 28 can be similarly wired in the long hole 30, and the semiconductor device 50 having a small thickness can be realized by applying the potting agent 36 only in the long hole 30.
【００１４】以上、本発明の好適な実施例について種々
述べてきたが、本発明は上述する実施例に限定されるも
のではなく、発明の精神を逸脱しない範囲で多くの改変
を施し得るのはもちろんである。Although various preferred embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and many modifications can be made without departing from the spirit of the invention. Of course.
【００１５】[0015]
【発明の効果】本発明に係る半導体装置を用いると、電
極端子とボンディング部を接続するボンディングワイヤ
を長孔内において配線することができるので、ボンディ
ングワイヤがループ状に形成されても外部接続端子の高
さ以下に押さえることができ、またさらに半導体素子は
全体がポッティング剤で封止される構造ではないため、
薄型化が図れる。また、配線パターンは全て外部接続端
子形成面に形成されるため、表裏を連絡するスルーホー
ルビアを回路基板に形成する必要がない。よって、製造
工程も簡略化されて、製造時間が短縮でき、製品コスト
の低減が可能となるという効果がある。According to the semiconductor device of the present invention, a bonding wire for connecting an electrode terminal and a bonding portion can be wired in a long hole, so that even if the bonding wire is formed in a loop shape, an external connection terminal is formed. The height of the semiconductor element can be suppressed, and the semiconductor element is not entirely sealed with a potting agent.
The thickness can be reduced. Further, since all the wiring patterns are formed on the surface on which the external connection terminals are formed, it is not necessary to form through-hole vias connecting the front and back sides on the circuit board. Therefore, the manufacturing process is simplified, the manufacturing time can be shortened, and the cost of the product can be reduced.
【図１】本発明に係る半導体装置の一実施の形態の構造
を示す断面図。FIG. 1 is a cross-sectional view illustrating a structure of an embodiment of a semiconductor device according to the present invention.
【図２】図１の半導体素子の電極端子形成面の電極端子
の配置を示す説明図。FIG. 2 is an explanatory view showing an arrangement of electrode terminals on an electrode terminal formation surface of the semiconductor element of FIG. 1;
【図３】図１の回路基板の平面図。FIG. 3 is a plan view of the circuit board of FIG. 1;
【図４】図３のＡ−Ａ断面図。FIG. 4 is a sectional view taken along line AA of FIG. 3;
【図５】本発明に係る半導体装置の他の実施の形態の構
造を示す断面図。FIG. 5 is a sectional view showing the structure of another embodiment of the semiconductor device according to the present invention.
【図６】従来の半導体装置の構造を示す断面図。FIG. 6 is a cross-sectional view illustrating a structure of a conventional semiconductor device.
１０ 半導体装置 １２ 電極端子群 １６ 半導体素子 １８ 回路基板 ２２ 配線パターン ２４ ボンディング部 ２６ 電極端子 ２８ ボンディングワイヤ ３０ 長孔 ３２ 外部接続端子形成面 ３４ 半導体素子搭載面 ３６ ポッティング剤 ３８ 電極端子形成面 DESCRIPTION OF SYMBOLS 10 Semiconductor device 12 Electrode terminal group 16 Semiconductor element 18 Circuit board 22 Wiring pattern 24 Bonding part 26 Electrode terminal 28 Bonding wire 30 Slot 32 External connection terminal formation surface 34 Semiconductor element mounting surface 36 Potting agent 38 Electrode terminal formation surface
Claims (2)
の面に外部接続端子を備えた回路基板の他方の面に搭載
し、該外部接続端子と前記電極端子とが電気的に接続さ
れて成る半導体装置において、 前記半導体素子は、前記電極端子が形成された面を前記
回路基板に対向させて搭載され、 前記回路基板は、前記外部接続端子が形成された面に一
端が前記外部接続端子と電気的に接続され、他端にボン
ディング部が設けられた配線パターンが形成されている
と共に、前記半導体素子の前記電極端子の配列に沿って
複数の電極端子を一連に露出させる長孔が形成され、か
つ該長孔の開口周縁部に前記ボンディング部が形成され
て長孔の底部に露出する前記各電極端子とボンディング
部とがボンディングワイヤにより電気的に接続され、 前記長孔内部および前記ボンディングが樹脂封止されて
いることを特徴とする半導体装置。1. A semiconductor device having an electrode terminal formed thereon is mounted on another surface of a circuit board having an external connection terminal on one surface, and the external connection terminal is electrically connected to the electrode terminal. In the semiconductor device, the semiconductor element is mounted with the surface on which the electrode terminal is formed facing the circuit board, and the circuit board has one end on the surface on which the external connection terminal is formed and the external connection terminal. And a wiring pattern having a bonding portion provided at the other end, and a long hole for exposing a plurality of electrode terminals in series along the arrangement of the electrode terminals of the semiconductor element. And the bonding portion is formed at the periphery of the opening of the elongated hole, and each of the electrode terminals exposed at the bottom of the elongated hole is electrically connected to the bonding portion by a bonding wire. A semiconductor device, wherein a part and the bonding are sealed with a resin.
いることを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein a side surface of said semiconductor element is sealed with a resin.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23157896A JP3136274B2 (en) | 1996-09-02 | 1996-09-02 | Semiconductor device |
| JP2000247777A JP3405718B2 (en) | 1996-09-02 | 2000-08-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23157896A JP3136274B2 (en) | 1996-09-02 | 1996-09-02 | Semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000247777A Division JP3405718B2 (en) | 1996-09-02 | 2000-08-17 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1074861A true JPH1074861A (en) | 1998-03-17 |
| JP3136274B2 JP3136274B2 (en) | 2001-02-19 |
Family
ID=16925724
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23157896A Expired - Fee Related JP3136274B2 (en) | 1996-09-02 | 1996-09-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3136274B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6549277B1 (en) | 1999-09-28 | 2003-04-15 | Nikon Corporation | Illuminance meter, illuminance measuring method and exposure apparatus |
| EP1367642A3 (en) * | 2002-05-30 | 2005-08-31 | Fujitsu Limited | Semiconductor device having a heat spreader exposed from a seal resin |
-
1996
- 1996-09-02 JP JP23157896A patent/JP3136274B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6549277B1 (en) | 1999-09-28 | 2003-04-15 | Nikon Corporation | Illuminance meter, illuminance measuring method and exposure apparatus |
| EP1367642A3 (en) * | 2002-05-30 | 2005-08-31 | Fujitsu Limited | Semiconductor device having a heat spreader exposed from a seal resin |
| US7193320B2 (en) | 2002-05-30 | 2007-03-20 | Fujitsu Limited | Semiconductor device having a heat spreader exposed from a seal resin |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3136274B2 (en) | 2001-02-19 |
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