JPS60110128A - Multilayered substrate and wire bonding method thereof - Google Patents

Multilayered substrate and wire bonding method thereof

Info

Publication number
JPS60110128A
JPS60110128A JP58217592A JP21759283A JPS60110128A JP S60110128 A JPS60110128 A JP S60110128A JP 58217592 A JP58217592 A JP 58217592A JP 21759283 A JP21759283 A JP 21759283A JP S60110128 A JPS60110128 A JP S60110128A
Authority
JP
Japan
Prior art keywords
wire bonding
bonding
recognition mark
bonding pad
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58217592A
Other languages
Japanese (ja)
Inventor
Hisashi Oguro
小黒　寿
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujifilm Business Innovation Corp
Original Assignee
Fuji Xerox Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Xerox Co Ltd filed Critical Fuji Xerox Co Ltd
Priority to JP58217592A priority Critical patent/JPS60110128A/en
Publication of JPS60110128A publication Critical patent/JPS60110128A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent displacement in wire bonding process and obtain a highly reliable hybrid substrate by giving pattern recognition marks to all layers having bonding pad. CONSTITUTION:A first conductive layer 2 has a first bonding pad 21 and a first recognition mark 22, while a second conductive layer 4 has a semiconductor chip placing area 41, a second bonding pad 42 and a second recognition mark 43. An interlayer insulation film 3 has a through hole 31 exposing the first bonding pad 22 and the first recognition mark 23 on the substrate surface. A semiconductor chip 5 is settled to the chip placing area 41 and position matching is then carried out with reference to the first recognition mark 22 and the wire bonding is carried out to the first bonding pad 21. In the same ways, thereafter, position matching is carried out with reference to the second recognition mark and the wire bonding is carried out to the second bonding pad 42.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、多層基板訃よびそのワイヤボンディング方法
に係り、特に、大面積デバイスの形成にあたり、ワイヤ
ボンディングの位置ずれｔ防ざ、信頼性の高いハイブリ
ッド基板を形成するための多層基板およびそのワイヤボ
ンディング方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a multilayer substrate and its wire bonding method, and in particular, to prevent wire bonding from misalignment and improve reliability when forming large area devices. The present invention relates to a multilayer substrate for forming a high-performance hybrid substrate and a wire bonding method thereof.

〔従来技術〕[Prior art]

例えば、混成集積回路（ハイブリッドＩＣ）においては
薄膜法わるいは厚膜法によって形成された集積回路基板
上に、半導体チップとして、能動素子あるいは、薄膜・
厚膜法では形成困−な受動素子が組み込まれている。こ
れらの半導体チップは当該集積回路基板上の所定位置に
固着されると共に、ワイヤボンディング法等によって心
気的接続がなされるわけである。For example, in a hybrid integrated circuit (hybrid IC), an active element or a thin film or semiconductor chip is mounted on an integrated circuit substrate formed by a thin film method or a thick film method.
Passive elements that are difficult to form using the thick film method are incorporated. These semiconductor chips are fixed at predetermined positions on the integrated circuit board, and are connected to each other by wire bonding or the like.

通常、ワイヤボンディングに際しての位置決めは、薄膜
あるいは厚膜配線層中の一層に形成された認識マークに
よって行なわれ、ポンディングパッドの位置に正しくボ
ンディングされるように工夫がなされている。ところが
、多層構造の配線層を有する基板上で、ポンディングパ
ッドが複数の層から構成されている場合、認識マークと
同一の層に形成されたボンディングツク、ドに対しては
正しい位置にワイヤボンディングが行なわれるが、他の
層に形成されたポンプイングツくラドに対しては、位置
ずれを生じるという現象が与られることがあった。Normally, positioning during wire bonding is performed by recognition marks formed in one layer of a thin film or thick film wiring layer, and devised techniques are used to ensure that bonding is performed correctly at the position of the bonding pad. However, if the bonding pad is made up of multiple layers on a board with multilayered wiring layers, the wire bonding cannot be done in the correct position for the bonding pads and pads formed on the same layer as the recognition mark. However, the pumping pads formed on other layers may be misaligned.

このようなポンディングパッドの位置ずれは、各層間の
パターンのわずかな位置ずれに起因するもので特に大面
積デバイスを構成するための大面積多層基板において発
生し易く、ワイヤボンディング工程における接着ミスの
大半を占めてお９、ハイブリッド基板の信頼性を低下さ
せる一因となっていた。Such misalignment of bonding pads is caused by slight misalignment of patterns between each layer, and is particularly likely to occur on large-area multilayer substrates for configuring large-area devices. This accounted for the majority9 and was a contributing factor to lowering the reliability of the hybrid board.

〔発明の目的〕[Purpose of the invention]

本発明は、前記実情に鑑みてなされたもので、ワイヤボ
ンディング工程における位置ずれ全防止し、信頼性の高
いノ・イブリッド基板を提供することを目的とする。The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a highly reliable hybrid board that completely prevents positional displacement during the wire bonding process.

〔発明の構成〕[Structure of the invention]

上記目的を達成するため、本発明の多層基板は、ポンデ
ィングパッドを有する層の全てに、認識マークを具備し
たことを特徴とするものである。In order to achieve the above object, the multilayer substrate of the present invention is characterized in that all layers having bonding pads are provided with recognition marks.

また、多層基板にワイヤボンディングを行なうにあたっ
ては、ポンディングパッドを有する層の全てに認識マー
クを付与しておき、夫々、当該認識マークに基づいて位
置合わせを行なった後に、ワイヤボンディングを実施す
ることを特徴とするものである。In addition, when performing wire bonding on a multilayer board, it is necessary to attach recognition marks to all layers that have bonding pads, and perform wire bonding after positioning each layer based on the recognition marks. It is characterized by:

〔実施例〕〔Example〕

以下、本発明実施例について、図面を参照しつつ説明す
る。Embodiments of the present invention will be described below with reference to the drawings.

この多層基板は、第１図に平面図、第２図にそのＡ−Ａ
断面図を示す如く、絶縁性のセラミック基板１上に厚膜
法によって形成された第１の導体層２と、さらにこの上
に眉間絶縁膜３ｔ−介して、厚膜法によって形成された
第２の導体層４とにより構成されている。そして第１の
導体層２は、その周囲に形成された４個の第１ポンデイ
ングパツド２１と、第１認識マーク２２とを有すると共
に、第２の導体層４は、半導体チップ載置ｓ４１と４個
の第２ポンデイングパツド４２と、第２認識マーク４３
とを有している。また、層間絶縁膜３は、スルーホール
３１を有しておシ前記第１ポンディングパッド２２およ
び前記第１認識マーク２３を基板表面上に露呈させるよ
うに形成されている。This multilayer board is shown in Fig. 1 as a plan view and in Fig. 2 as A-A.
As shown in the cross-sectional view, a first conductor layer 2 is formed by a thick film method on an insulating ceramic substrate 1, and a second conductor layer 2 is formed by a thick film method on top of this through an insulating film 3t between the eyebrows. The conductor layer 4 is made up of a conductor layer 4. The first conductor layer 2 has four first bonding pads 21 and a first recognition mark 22 formed around it, and the second conductor layer 4 has a semiconductor chip mounting pad s41. , four second ponding pads 42 , and a second recognition mark 43
It has Further, the interlayer insulating film 3 is formed to have a through hole 31 so as to expose the first bonding pad 22 and the first recognition mark 23 on the surface of the substrate.

次に、前記多層基板上に半導体チップを搭載し、ハイブ
リッドＩＣデバイスの実装を行なうにあたり実施される
、該多層基板のワイヤボンディング方法について説明す
る〇 まず、第１図および第２図に示す如き多層基板の半導体
チップ載置部４１に通常の方法によって所定の半導体チ
ップ５ｔ−固着する。（ダイボンディングニー程） 欠いで、フルオートワイヤーボンディングマシーンを使
用し、第１の認識マーク２２ｔ−基準として位置合わせ
を行ないボンディング座標をプログ２ム入力した後、４
個の第１ポンデイングパツド２１に対し、金！６（ワイ
ヤ）を使用し、ワイヤボンディングを施す。Next, we will explain the wire bonding method for the multilayer board, which is carried out when mounting a semiconductor chip on the multilayer board and mounting a hybrid IC device. A predetermined semiconductor chip 5t is fixed to the semiconductor chip mounting portion 41 of the substrate by a normal method. (Die bonding knee) Using a fully automatic wire bonding machine, perform alignment using the first recognition mark 22t as a reference and input the bonding coordinates into the program 2.
Gold for the first pounding pad 21! 6 (wire) and perform wire bonding.

続いて同様に、第２の認識マーク４３を基準として位置
合わせを行ない、ボンディング座標をプログ２ム入力し
た後、４個の第２ポンデイングパツド４２に対し、金ａ
６（ワイヤ）を使用し、ワイヤボンディングを施すこと
によシ、第３図に示す如く、レイヤボンディングの完了
したハイブリッド基板を得る。Subsequently, in the same manner, alignment is performed using the second recognition mark 43 as a reference, and after inputting the bonding coordinates into the program 2, gold a is applied to the four second bonding pads 42.
6 (wire) and perform wire bonding to obtain a hybrid substrate with completed layer bonding, as shown in FIG.

このようにして形成されたハイブリッド基板は、位置ず
れを生じることなく、正しい位置にワイヤボンディング
が施されているため、極めて高い信頼性を有している。The hybrid substrate thus formed has extremely high reliability because the wire bonding is performed at the correct position without any positional deviation.

なお、実施例においては、フルオートのワイヤボンディ
ングマシーンによるワイヤボンディングについて説明し
たが、手動のワイヤボンディングマシーンを使用する場
合においても同様の効果を萎効し得ることは言うまでも
ない。In the embodiment, wire bonding using a fully automatic wire bonding machine has been described, but it goes without saying that the same effect can be obtained even when a manual wire bonding machine is used.

また、３層以上の配線層を有する多層基板についても、
同様に、各層に認識マークを付与しておき、該認識マー
クを基準にして位置合わせを行なうことによル、ワイヤ
ボンディングエ＠　Ｋ　ｊ？ける接着ミスを防止し得、
信頼性の高いハイブリッド基板を得ることができる。Also, regarding multilayer boards having three or more wiring layers,
Similarly, by attaching recognition marks to each layer and performing alignment based on the recognition marks, wire bonding is possible. It can prevent adhesion errors caused by
A highly reliable hybrid substrate can be obtained.

〔発明の効果〕〔Effect of the invention〕

以上、説明してきたように、本発明によれば２層以上の
配線層を有する多層構造の基板において、ボンディング
バッドを有する配線層のすべてに少なくとも１つのパタ
ーン認識用マークが基板表面に露呈するように付与され
ているため、この多層基板の実装工程において、チップ
を搭載し、ワイヤボンディングを行なうにあたり、ボン
ディングの位置合わせが容易に猜度良くなされ得る。As described above, according to the present invention, in a multilayered board having two or more wiring layers, at least one pattern recognition mark is exposed on the board surface in all wiring layers having bonding pads. Therefore, in the mounting process of this multilayer board, when mounting a chip and performing wire bonding, bonding can be easily and precisely aligned.

また、各々のパターン認識用マークを基準にして夫々の
配線層へのワイヤボンディングを行なうことが可能とな
り、このため、ボンディングの位置ずれに起因する接着
ミスはほとんど皆無となり、信頼性の高いハイブリッド
基板を形成することが可能となる。In addition, it is now possible to perform wire bonding to each wiring layer using each pattern recognition mark as a reference, which eliminates almost all bonding errors due to bonding misalignment, resulting in highly reliable hybrid boards. It becomes possible to form.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、本発明実施例の多層基板の平面図、第２図は
、第１図のＡ−ＡＵｒ面図、第３図は、本発明実施例の
多層基板を使用し、本発明実施列のワイヤボンディング
方法によって形成されたハイフリット基板の１部を示す
図である。 １・・・セラミック基板、２・・・第１の導体層、３・
・・層間絶縁膜、４・・・第２の導体層、５・・・半導
体チップ、６・・・金ｍ（ワイヤ）、２１・・・第１ボ
ンデインクパツド、２２・・・第１認識マーク、３１・
・・スルーホール、４１・・・半導体チップ載置部、４
２・・・第２ポンデイングパツド、４３・・・第２認識
マーク。FIG. 1 is a plan view of a multilayer substrate according to an embodiment of the present invention, FIG. 2 is a plane view taken along A-AUr in FIG. 1, and FIG. 3 is a plan view of a multilayer substrate according to an embodiment of the present invention. 1 is a diagram illustrating a portion of a high-frit substrate formed by a row wire bonding method; FIG. DESCRIPTION OF SYMBOLS 1... Ceramic substrate, 2... First conductor layer, 3...
...Interlayer insulating film, 4...Second conductor layer, 5...Semiconductor chip, 6...Gold m (wire), 21...First bond ink pad, 22...First Recognition mark, 31・
...Through hole, 41...Semiconductor chip mounting part, 4
2...Second pounding pad, 43...Second recognition mark.

Claims (2)

【特許請求の範囲】[Claims] （１）　基板上に２層以上の配線層を有する多層基板に
おいて、ポンディングパッドを具えた配線層のすべてに
表板表面に露呈する少なくとも１つのパターン認識用マ
ークを付与したことを特徴とする多層基板・(1) A multilayer board having two or more wiring layers on the board, characterized in that at least one pattern recognition mark exposed on the surface of the top board is provided on all of the wiring layers provided with bonding pads. Multilayer board/ （２）基板上に２層以上の配線層、を有する多層基板に
対してワイヤボンディングを行なうにあたシ、各）ｄ　
ＶＣおけるワイヤボンディング工程は当該ポンディング
パッドの形成された配線層内に設けられたパターン認識
用マークに基づいて位置合わせを行なった後に実行され
ることを特徴とする多層基板のワイヤボンデインク方法
。(2) When performing wire bonding on a multilayer board that has two or more wiring layers on the board, each) d
A wire bonding method for a multilayer board, characterized in that the wire bonding step in a VC is performed after positioning is performed based on pattern recognition marks provided in the wiring layer in which the bonding pad is formed.
JP58217592A 1983-11-18 1983-11-18 Multilayered substrate and wire bonding method thereof Pending JPS60110128A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58217592A JPS60110128A (en) 1983-11-18 1983-11-18 Multilayered substrate and wire bonding method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58217592A JPS60110128A (en) 1983-11-18 1983-11-18 Multilayered substrate and wire bonding method thereof

Publications (1)

Publication Number Publication Date
JPS60110128A true JPS60110128A (en) 1985-06-15

Family

ID=16706705

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58217592A Pending JPS60110128A (en) 1983-11-18 1983-11-18 Multilayered substrate and wire bonding method thereof

Country Status (1)

Country Link
JP (1) JPS60110128A (en)

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