JPH0142344Y2 - - Google Patents
Info
- Publication number
- JPH0142344Y2 JPH0142344Y2 JP18627783U JP18627783U JPH0142344Y2 JP H0142344 Y2 JPH0142344 Y2 JP H0142344Y2 JP 18627783 U JP18627783 U JP 18627783U JP 18627783 U JP18627783 U JP 18627783U JP H0142344 Y2 JPH0142344 Y2 JP H0142344Y2
- Authority
- JP
- Japan
- Prior art keywords
- board
- metal substrate
- substrate
- metal
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 33
- 239000002184 metal Substances 0.000 claims description 29
- 239000008188 pellet Substances 0.000 claims description 20
- 239000004065 semiconductor Substances 0.000 claims description 9
- 229920005989 resin Polymers 0.000 description 6
- 239000011347 resin Substances 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004049 embossing Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
Description
【考案の詳細な説明】
イ 産業上の利用分野
この考案は１枚の基板上に複数の半導体ペレツ
トをマウントして配線した混成集積回路装置に利
用される。[Detailed description of the invention] A. Field of industrial application This invention is used for a hybrid integrated circuit device in which a plurality of semiconductor pellets are mounted and wired on one substrate.
ロ 従来技術
一般にモノリシツクICは、１個のモノシリツ
クICペレツトを有し、このICペレツトはシグナ
ル用、パワー用、スイツチング用などとその用途
を限定して用いているため、自ずと１個のICの
機能もそのICペレツトの機能に限定される。そ
こで多機能の回路を構成するには多種のICペレ
ツトを組合せ使用する必要がある。しかし単に多
種のICペレツト使用しただけでは、実装に多大
工数や実装スペースに大きなものが必要で高コス
ト化となる。そこで最近は、多種のICペレツト
を、受動素子である抵抗を含めてパターン配線し
た、１枚の基板上にマウントした混成集積回路装
置が上記問題を解決した半導体装置として賞用さ
れる傾向にある。(b) Prior art In general, a monolithic IC has one monolithic IC pellet, and this IC pellet is used for limited purposes such as signal, power, and switching purposes, so the functions of one IC naturally differ. is also limited to the functionality of its IC pellet. Therefore, in order to construct a multifunctional circuit, it is necessary to use a combination of various types of IC pellets. However, simply using a variety of IC pellets requires a large amount of man-hours and space for mounting, resulting in high costs. Recently, therefore, hybrid integrated circuit devices, in which various types of IC pellets are patterned including resistors, which are passive elements, and mounted on a single substrate, are being used as semiconductor devices that solve the above problems. .
混成集積回路装置として現在使用されているも
のはパツケージが樹脂の粉体塗装や液体塗装によ
るもの、セラミツクや金属、プラスチツクのケー
スによるものが大部分を占めている。ところが、
これら混成集積回路装置は未だ内部配線のシヨー
ト対策や導出リードの設計が不完全で、生産性が
悪く、信頼性に劣る問題があつた。 Most of the hybrid integrated circuit devices currently in use have packages made of resin powder coating or liquid coating, and cases made of ceramic, metal, or plastic. However,
These hybrid integrated circuit devices still suffer from problems such as poor productivity and poor reliability due to incomplete shorting measures for internal wiring and incomplete design of lead-out leads.
ハ 考案の目的
本考案の目的は、上記問題を解決することであ
り、より生産性が良く、信頼性に優れた混成集積
回路装置を提供することにある。C. Purpose of the invention The purpose of the invention is to solve the above-mentioned problems, and to provide a hybrid integrated circuit device with better productivity and reliability.
ニ 考案の構成
本考案はパツケージが生産性、信頼性に優れた
樹脂モールド成形タイプのものに好適な混成集積
回路装置であつて、周辺近傍に複数のリードを配
した金属基板上に、上面に配線パターンを形成し
た絶縁基板を貼布し、この配線済絶縁基板上に複
数のICペレツト等の半導体ペレツトをマウント
し、半導体ペレツトと配線パターン、半導体ペレ
ツトとリード、配線パターンとリードとを、夫々
ボンデイングワイヤで電気的接続したものにおい
て、前記配線済絶縁基板を前記金属基板より食み
出す形状寸法に設定したことを特徴とする。上記
リードと金属基板は１枚の金属板から打抜かれた
ものが使用され、配線済絶縁基板は通常のセラミ
ツク基板やその他のプリント基板の如きものが使
用される。D. Structure of the invention The present invention is a hybrid integrated circuit device suitable for a resin molded type package with excellent productivity and reliability. An insulating substrate on which a wiring pattern has been formed is pasted, and a plurality of semiconductor pellets such as IC pellets are mounted on this wired insulating substrate, and the semiconductor pellet and the wiring pattern, the semiconductor pellet and the lead, and the wiring pattern and the lead are respectively attached. In the electrical connection made by bonding wire, the wired insulating substrate is set to have a shape and dimension that protrudes from the metal substrate. The leads and the metal board are punched from a single metal plate, and the wired insulating board is a normal ceramic board or other printed circuit board.
ホ 実施例
本考案の説明の前に本考案の前提技術である混
成集積回路装置の一例を第１図乃至第４図により
説明すると、１は金属基板、２…は金属基板１の
周辺近傍から延びる複数のリードで、これらは始
め１枚の金属板から打抜き加工されたリードフレ
ームの一部として一体形成されているもので、後
述する通り樹脂モールド成形後に個々に分離され
る。３は金属基板１上にエポキシ樹脂系等の接着
剤４で貼布された配線済絶縁基板で、トリアジン
等の絶縁板５上に複数の配線パターン６，６…を
PR法やスクリーン印刷法等で被着形成したもの
である。７，７…は配線済絶縁基板３上の複数個
所にマウントした複数種類のペレツト、８，８…
はICペレツト７，７…の表面電極と配線パター
ン６，６…、リード２，２…とを選択的に電気的
接線するボンデイングワイヤで、８ａ，８ａ…は
ICペレツト７，７…と配線パターン６，６…を
接続するワイヤ、８ｂ，８ｂ…はICペレツト７，
７…とリード２，２…を接続するワイヤ、８ｃ，
８ｃ…は配線パターン６，６…とリード２，２…
を接続するワイヤを示す。９はリード２，２…の
外側端部を導出させ配線済絶縁基板３、ペレツト
７，７、…、ボンデイングワイヤ８ａ，８ａ，…
８ｂ，８ｂ，…８ｃ，８ｃ，…を保護するために
モールド成形した外装樹脂材（パツケージ）で、
このモールド成形後にリード２，２…の分離や折
曲加工が行われる。E. Example Before explaining the present invention, an example of a hybrid integrated circuit device, which is a basic technology of the present invention, will be explained with reference to FIGS. The plurality of extending leads are initially integrally formed as part of a lead frame punched from a single metal plate, and are separated into individual parts after resin molding as described later. Reference numeral 3 denotes a wired insulating board which is pasted on a metal substrate 1 with an adhesive 4 such as epoxy resin, and a plurality of wiring patterns 6, 6, . . . are formed on an insulating board 5 made of triazine or the like.
It is formed by adhesion using the PR method, screen printing method, etc. 7, 7... are multiple types of pellets mounted at multiple locations on the wired insulating substrate 3, 8, 8...
8a, 8a, . . . are bonding wires that selectively connect electrically the surface electrodes of the IC pellets 7, 7, and the wiring patterns 6, 6, and leads 2, 2, and 8a, 8a, .
Wires connecting the IC pellets 7, 7... and the wiring patterns 6, 6, 8b, 8b... are the IC pellets 7, 8b, 8b...
7... and a wire connecting leads 2, 2..., 8c,
8c... is the wiring pattern 6, 6... and the leads 2, 2...
Shows the wires to connect. Reference numeral 9 shows the outer ends of the leads 2, 2, .
8b, 8b,...8c, 8c,... with molded exterior resin material (package) to protect.
After this molding, the leads 2, 2... are separated and bent.
このような樹脂モールド成形タイプの混成集積
回路装置は通常のモノリシツクIC装置と同様な
製造工程で製作できるので、樹脂塗装やケースに
よるパツケージの混成集積回路装置に比べ生産性
が良く、信頼性も良く、而もユーザにとつて実装
がし易い。 These resin molded hybrid integrated circuit devices can be manufactured using the same manufacturing process as ordinary monolithic IC devices, so they have better productivity and reliability than hybrid integrated circuit devices that are packaged with resin coating or a case. , it is also easy for users to implement.
ところで上記混成集積回路装置は配線済絶縁基
板３を金属基板１と同一形状にしている。そのた
め金属基板１上に配線済絶縁基板３を貼布する場
合、配線済絶縁基板３が少しでも横ずれすると、
第４図に示すように、金属基板１から少し食み出
し、この食み出しと反対側では、金属基板１が配
線済絶縁基板３から食み出す。このように金属基
板１が配線済絶縁基板３から食み出すと、この食
み出し部分１′上を跨ぐワイヤ８ｂ…，８ｃ…が
第４図鎖線で示すように垂れ下がると食み出し部
分１′にシヨートする恐れがある。 Incidentally, in the above hybrid integrated circuit device, the wired insulating substrate 3 has the same shape as the metal substrate 1. Therefore, when pasting the wired insulating board 3 on the metal board 1, if the wired insulating board 3 shifts even slightly,
As shown in FIG. 4, the metal substrate 1 protrudes a little from the metal substrate 1, and on the opposite side to this protrusion, the metal substrate 1 protrudes from the wired insulating substrate 3. When the metal substrate 1 protrudes from the wired insulating substrate 3 in this way, the wires 8b..., 8c... that straddle the protruding portion 1' hang down as shown by the chain lines in FIG. There is a risk of being shot.
そこで本考案は上記シヨート防止手段として第
５図及び第６図に示すように配線基板１０にその
配線済絶縁基板１１が金属基板１２より全体に一
回り大きな形状のものを使用する。尚、第５図と
第６図の第１図乃至第４図と同一参照符号のもの
は同一内容のものを示す。また配線基板１０の大
きさは金属基板１２に貼布した時に横ずれしても
金属基板１２から食み出さない程度である。この
ようにすると仮りに上記ワイヤ８ｂ…，８ｃ…が
大きく垂れ下がつても配線済絶縁基板１１に当た
るだけで金属基板１２に当たつてシヨートする心
配が無くなる。 Therefore, in the present invention, as the shot prevention means, as shown in FIGS. 5 and 6, a wiring board 10 having a wired insulating board 11 that is slightly larger than the metal board 12 is used. Note that the same reference numerals in FIGS. 5 and 6 as in FIGS. 1 to 4 indicate the same contents. Further, the size of the wiring board 10 is such that it does not protrude from the metal substrate 12 even if it shifts laterally when attached to the metal substrate 12. In this way, even if the wires 8b, 8c, etc. hang down significantly, they will only hit the wired insulating board 11, and there will be no fear that they will hit the metal board 12 and shoot.
また、上記配線基板１０と金属基板１２間に両
者の位置決め手段１３を設けることが望ましい。
この位置決め手段１３としては配線済絶縁基板１
１の２〜３箇所に位置決め用穴１４，１４…を形
成し、穴１４，１４…に対応する金属基板１２上
にエンボス１５，１５…を突設して、この両者の
嵌合にて行うものが好適である。このように位置
決め手段１３を介して配線基板１０を金属基板１
２上に貼布すると配線基板１０の横ずれがほとん
ど無くなり、在つても微少なためワイヤ８ｂ…，
８ｃ…と金属基板１２のシヨートがより確実に防
止される。 Further, it is desirable to provide positioning means 13 between the wiring board 10 and the metal board 12.
As this positioning means 13, the wired insulating substrate 1
Positioning holes 14, 14... are formed at two to three locations in 1, and embossing 15, 15... is provided protrudingly on the metal substrate 12 corresponding to the holes 14, 14..., and the fitting is performed by fitting these two together. Preferably. In this way, the wiring board 10 is moved to the metal board 1 via the positioning means 13.
2, there is almost no lateral displacement of the wiring board 10, and even if there is, it is minute, so the wires 8b...,
8c... and the shot of the metal substrate 12 is more reliably prevented.
次に本考案の変形例を第７図により説明する。
これは金属基板１６とリード１７，１７…が上記
実施例と形状が異なるもので、配線の必要上一部
のリード１７′を金属基板１６の一角に回り込ま
せて配置した例を示し、この場合は配線基板１
０′の配線済絶縁基板１１′を金属基板１６より形
状大にすると共に、リード１７′に沿う部分にリ
ード１７′上に跨がる張出部分１１″，１１″を形
成する。このようにするとリード１７′を跨つて
配線されたワイヤ８′，８′…とリード１７′との
シヨートをも防止される。 Next, a modification of the present invention will be explained with reference to FIG.
This is an example in which the metal substrate 16 and the leads 17, 17... are different in shape from the above embodiment, and some of the leads 17' are placed around one corner of the metal substrate 16 due to wiring requirements. is wiring board 1
The wired insulating substrate 11' of 0' is made larger in shape than the metal substrate 16, and projecting portions 11'', 11'' are formed along the leads 17' to extend over the leads 17'. In this way, it is also possible to prevent the wires 8', 8', .
ヘ 考案の効果
以上の如く、本考案によれば配線基板をマウン
トする金属基板とボンデイングワイヤのシヨート
が無くなり、従つて混成集積回路装置の歩留まり
向上、信頼性改善が図れる。F. Effects of the Invention As described above, according to the present invention, the metal substrate on which the wiring board is mounted and the shoot of the bonding wire are eliminated, thereby improving the yield and reliability of the hybrid integrated circuit device.
第１図及び第２図は本考案の前提となる混成集
積回路装置の平面図及び側面図、第３図及び第４
図は第２図のＡ−Ａ線に沿う要部での拡大断面
図、第５図は本考案の一実施例を示す平面図、第
６図は第５図のＢ−Ｂ線に沿う要部の拡大断面
図、第７図は本考案の他の実施例を示す要部斜視
図である。
１……金属基板、２……リード、６……配線パ
ターン、７……半導体ペレツト（ICペレツト）、
８，８′，８ａ，８ｂ，８ｃ……ボンデイングワ
イヤ、１０，１０′……配線基板、１１，１１′…
…配線済絶縁基板、１２……金属基板、１６……
金属基板、１７，１７′……リード。
1 and 2 are a plan view and a side view of a hybrid integrated circuit device, which is the premise of the present invention, and FIGS. 3 and 4 are
The figure is an enlarged sectional view of the main part along the line A-A in Fig. 2, Fig. 5 is a plan view showing one embodiment of the present invention, and Fig. 6 is the main part taken along the line B-B in Fig. 5. FIG. 7 is a perspective view of a main part showing another embodiment of the present invention. 1... Metal substrate, 2... Lead, 6... Wiring pattern, 7... Semiconductor pellet (IC pellet),
8, 8', 8a, 8b, 8c... bonding wire, 10, 10'... wiring board, 11, 11'...
...wired insulating board, 12...metal board, 16...
Metal substrate, 17, 17'...Lead.
Claims (1)
に、複数の配線パターンを形成した絶縁基板を貼
布し、この絶縁基板上に複数の半導体ペレツトを
マウントして、半導体ペレツトと配線パターン、
半導体ペレツトとリード、配線パターンとリード
をボンデイングワイヤで電気的接続したものであ
つて、前記配線済絶縁基板を前記金属基板から食
み出す形状寸法に設定したことを特徴とする混成
集積回路装置。 An insulating substrate on which a plurality of wiring patterns are formed is pasted on a metal substrate with a plurality of leads arranged near the periphery, a plurality of semiconductor pellets are mounted on this insulating substrate, and the semiconductor pellets and the wiring patterns are bonded together.
1. A hybrid integrated circuit device in which a semiconductor pellet and a lead, and a wiring pattern and a lead are electrically connected by a bonding wire, and the wired insulating substrate is set to have a shape and dimension that protrudes from the metal substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1983186277U JPS6092832U (en) | 1983-11-30 | 1983-11-30 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1983186277U JPS6092832U (en) | 1983-11-30 | 1983-11-30 | Hybrid integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6092832U JPS6092832U (en) | 1985-06-25 |
| JPH0142344Y2 true JPH0142344Y2 (en) | 1989-12-12 |
Family
ID=30402394
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1983186277U Granted JPS6092832U (en) | 1983-11-30 | 1983-11-30 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6092832U (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2810285B2 (en) * | 1993-01-20 | 1998-10-15 | 株式会社日立製作所 | Semiconductor device and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5245056A (en) * | 1976-09-27 | 1977-04-08 | Gen Corp | Integrated circuit and method of producing same |
| JPS58122763A (en) * | 1982-01-14 | 1983-07-21 | Toshiba Corp | Resin sealed type semiconductor device |
-
1983
- 1983-11-30 JP JP1983186277U patent/JPS6092832U/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5245056A (en) * | 1976-09-27 | 1977-04-08 | Gen Corp | Integrated circuit and method of producing same |
| JPS58122763A (en) * | 1982-01-14 | 1983-07-21 | Toshiba Corp | Resin sealed type semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6092832U (en) | 1985-06-25 |
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