JPH0358464A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0358464A JPH0358464A JP19493489A JP19493489A JPH0358464A JP H0358464 A JPH0358464 A JP H0358464A JP 19493489 A JP19493489 A JP 19493489A JP 19493489 A JP19493489 A JP 19493489A JP H0358464 A JPH0358464 A JP H0358464A
- Authority
- JP
- Japan
- Prior art keywords
- package
- insulating layer
- semiconductor device
- lead
- sealing part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000007789 sealing Methods 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 2
- 241000272168 Laridae Species 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関する.
〔従来の技術〕
従来の半導体装置は、第5図に示すように半導体チップ
(図示せず)に電気的に接続されたり一ド2が封止部1
の側面より導出されて構成され、外部回路との信号の伝
達に使用されていた.〔発明が解決しようとする課題〕
上述した従来の半導体装置は、1本のリードで伝達でき
る電気信号は、1種類のみであるため、伝達すべき電気
信号の種類の増加に併せてリード数を増加させねばなら
ず、この場合、パッケージの寸法による制限を受けたり
、あるいは半導体チップの大きさに比べて不必要に大き
な寸法のパッケージを準備しなければならないという欠
点がある.
〔課題を解決するための手段〕
本発明の半導体装置は、半導体チップを封止した封止部
と、前記半導体チップと電気的に接続して前記封止部よ
り外部に導出されたリードとを有する半導体装置におい
て、前記リードが絶縁層を介して互に絶縁された複数層
で構成される。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device. [Prior Art] In a conventional semiconductor device, as shown in FIG.
It was constructed by being derived from the aspects of , and was used for transmitting signals with external circuits. [Problems to be Solved by the Invention] In the conventional semiconductor device described above, only one type of electrical signal can be transmitted by one lead, so the number of leads must be increased as the number of types of electrical signals to be transmitted increases. In this case, there are disadvantages such as being limited by the size of the package or having to prepare a package that is unnecessarily large in size compared to the size of the semiconductor chip. [Means for Solving the Problems] A semiconductor device of the present invention includes a sealing portion that seals a semiconductor chip, and a lead electrically connected to the semiconductor chip and led out from the sealing portion. In the semiconductor device having the above-mentioned semiconductor device, the lead is composed of a plurality of layers insulated from each other via an insulating layer.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例を示す斜視図である.
半導体チップを封止した封止部1の側面より導出したリ
ード2a,2bの間に絶縁層3を挟んで形成され、リー
ド2a,2bを電気的に絶縁し、1本のリードで2系統
の信号が伝達できる。FIG. 1 is a perspective view showing an embodiment of the present invention. An insulating layer 3 is sandwiched between the leads 2a and 2b led out from the side surface of the sealing part 1 in which the semiconductor chip is sealed, and the leads 2a and 2b are electrically insulated. Signals can be transmitted.
第2図及び第3図は本発明の第2及び第3の実施例を示
す斜視図である.
第2図に示すように、絶縁層3を介して導出したリード
2a,2bを■形に整形したものと、第3図に示すよう
に、絶縁層3を挟んで導出された一方のリード2aをガ
ルウィング形に整形し、他方のりード2bをJ字形に整
形した以外は第1の実施例と同じ構成を有する。2 and 3 are perspective views showing second and third embodiments of the present invention. As shown in FIG. 2, the leads 2a and 2b led out through the insulating layer 3 are shaped into a ■ shape, and as shown in FIG. 3, one lead 2a led out with the insulating layer 3 in between. It has the same structure as the first embodiment except that the lead 2b is shaped into a gull wing shape and the other lead 2b is shaped into a J shape.
第4図は本発明の第4の実施例を示す斜視図である。FIG. 4 is a perspective view showing a fourth embodiment of the present invention.
第4図に示すように、封止部1の側面より互に絶縁層3
で絶縁されたリード2a,2b,2cが導出されている
以外は第1の実施例の同じ楕或を有している.
〔発明の効果〕
以上説明したように本発明は、絶縁層を介して電気的に
分離され且つ積層された複数のリードを封止部の側面よ
り導出した構成により、伝達すべき電気信号の種類が増
加しても、パッケージの寸法に制限を受けることなく、
リード数を増加させて容易に多くの信号を扱うことので
きる半導体装置を実現できるという効果を有する。As shown in FIG. 4, the insulating layers 3
This embodiment has the same ellipse as the first embodiment except that the leads 2a, 2b, and 2c are led out insulated by the ellipse. [Effects of the Invention] As explained above, the present invention has a configuration in which a plurality of leads are electrically separated via an insulating layer and are stacked and led out from the side of the sealing part, so that the types of electrical signals to be transmitted can be easily transmitted. increases, without being limited by package dimensions.
This has the effect that it is possible to realize a semiconductor device that can easily handle many signals by increasing the number of leads.
また、半導体チップの大きさに比例したパッケージを用
いることが可能となるので半導体集積回路を基板に実装
する際の実装面積を小さくすることができる効果もある
.Furthermore, since it becomes possible to use a package proportional to the size of the semiconductor chip, it is possible to reduce the mounting area when mounting a semiconductor integrated circuit on a substrate.
第1図乃至第4図は本発明の第1乃至第4の実施例を示
す斜視図、第5図は従来の半導体装置の斜視図である.
1・・・封止部、2 . 2 a , 2 b , 2
c ・−リード、3・・・絶縁層.1 to 4 are perspective views showing first to fourth embodiments of the present invention, and FIG. 5 is a perspective view of a conventional semiconductor device. 1... Sealing part, 2. 2 a, 2 b, 2
c ・-Lead, 3... Insulating layer.
Claims (1)
電気的に接続して前記封止部より外部に導出されたリー
ドとを有する半導体装置において、前記リードが絶縁層
を介して互に絶縁された複数層からなることを特徴とす
る半導体装置。In a semiconductor device having a sealing part that seals a semiconductor chip, and leads electrically connected to the semiconductor chip and led out from the sealing part, the leads are insulated from each other via an insulating layer. A semiconductor device comprising a plurality of layers.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19493489A JPH0358464A (en) | 1989-07-26 | 1989-07-26 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19493489A JPH0358464A (en) | 1989-07-26 | 1989-07-26 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0358464A true JPH0358464A (en) | 1991-03-13 |
Family
ID=16332773
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19493489A Pending JPH0358464A (en) | 1989-07-26 | 1989-07-26 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0358464A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2021193443A (en) * | 2015-03-06 | 2021-12-23 | ハッチンソン テクノロジー インコーポレイテッドHutchinson Technology Incorporated | Shape memory alloy wire attachment structures for suspension assembly |
US11977241B2 (en) | 2014-12-02 | 2024-05-07 | Hutchinson Technology Incorporated | Camera lens suspension with limiter |
-
1989
- 1989-07-26 JP JP19493489A patent/JPH0358464A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11977241B2 (en) | 2014-12-02 | 2024-05-07 | Hutchinson Technology Incorporated | Camera lens suspension with limiter |
JP2021193443A (en) * | 2015-03-06 | 2021-12-23 | ハッチンソン テクノロジー インコーポレイテッドHutchinson Technology Incorporated | Shape memory alloy wire attachment structures for suspension assembly |
US11782286B2 (en) | 2015-03-06 | 2023-10-10 | Hutchinson Technology Incorporated | Shape memory alloy wire attachment structures for a suspension assembly |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS62126661A (en) | Hybrid integrated circuit device | |
KR930011178A (en) | Semiconductor package | |
JPH03169062A (en) | Semiconductor device | |
JPH0199248A (en) | Semiconductor device | |
JPS63211663A (en) | Circuit board | |
JPS62119952A (en) | Integrated circuit device | |
JPH0358464A (en) | Semiconductor device | |
KR880008441A (en) | Ceramic Packages for High Frequency Semiconductor Devices | |
JPS63308943A (en) | Semiconductor device | |
JPH10256472A (en) | Structure of semiconductor device provided with ic chips | |
JPH04142073A (en) | Semiconductor device | |
JPS63175450A (en) | Hermetic seal type semiconductor device | |
JPH0216791A (en) | Hybrid integrated circuit device | |
JPH01222467A (en) | Package for semiconductor device | |
JPS63208252A (en) | Package for semiconductor device | |
JPS629652A (en) | Semiconductor device | |
JPS6366959A (en) | Multiple lead frame | |
JPH01257361A (en) | Resin-sealed semiconductor device | |
JPH05102336A (en) | Semiconductor device | |
JPH02210858A (en) | Semiconductor device | |
JPS6130286Y2 (en) | ||
JPH01186660A (en) | Semiconductor element package | |
JPS6132560A (en) | Semiconductor device | |
JPH04144161A (en) | Semiconductor integrated circuit device | |
JPH0387054A (en) | Semiconductor device |