JPH08340021A - Electronic component and electronic component module - Google Patents
Electronic component and electronic component moduleInfo
- Publication number
- JPH08340021A JPH08340021A JP7144350A JP14435095A JPH08340021A JP H08340021 A JPH08340021 A JP H08340021A JP 7144350 A JP7144350 A JP 7144350A JP 14435095 A JP14435095 A JP 14435095A JP H08340021 A JPH08340021 A JP H08340021A
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- electrode
- wiring film
- semiconductor
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は電子部品および電子部品
モジュール、特に重ねて実装できる電子部品および半導
体部品（半導体チップ，半導体装置）を積層した構造の
電子部品モジュールに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic component and an electronic component module, and more particularly to an electronic component module having a structure in which electronic components and semiconductor components (semiconductor chips, semiconductor devices) that can be mounted in a stack are stacked.
【０００２】[0002]
【従来の技術】ＬＳＩ等のＩＣの実装では、ＩＣの実装
数の増加に伴って二次元的に実装面積が増大する。実装
ボードを複数枚重ねるようにして使用することによって
初めて三次元的になる。ＩＣメモリ（メモリ集積回路）
では、記憶容量増大および実装密度向上のために、半導
体装置を重ねて実装している。2. Description of the Related Art In mounting an IC such as an LSI, the mounting area increases two-dimensionally as the number of mounted ICs increases. It becomes three-dimensional only when multiple mounting boards are used by stacking them. IC memory (memory integrated circuit)
In order to increase the storage capacity and the mounting density, semiconductor devices are stacked and mounted.
【０００３】たとえば、日経ＢＰ社発行「日経マイクロ
デバイス」1989年12月号、同年12月１日発行、Ｐ48に
は、ＴＡＢ構造の半導体装置（ＳＲＡＭ）を４個重ね、
チップ選択端子以外の各共通端子をアウターリード部分
で４本ずつ重ねて接続したモジュールが記載されてい
る。For example, the "Nikkei Microdevice" issued by Nikkei BP, December 1989 issue, December 1, the same year, P48, four semiconductor devices (SRAM) of the TAB structure are stacked,
There is described a module in which four common terminals other than the chip selection terminal are stacked and connected at the outer lead portion.
【０００４】[0004]
【発明が解決しようとする課題】ＩＣを配線基板（ボー
ド）に実装する場合、１個部品が増加する毎に部品の占
める面積の２倍以上の実装面積を必要とする。When an IC is mounted on a wiring board (board), a mounting area which is more than twice the area occupied by each component is required every time one component is added.
【０００５】また、従来のメモリＩＣでは、前記文献に
も記載されているが、三次元実装を行っているが、ロジ
ックＩＣ等他のＩＣでは、共通ピンが殆どないため、複
数の半導体装置を単純に重ね合わせる手段は採用できな
い。Further, in the conventional memory IC, although described in the above-mentioned document, three-dimensional mounting is performed, but in other ICs such as a logic IC, since there are almost no common pins, a plurality of semiconductor devices are mounted. Means of simply overlapping cannot be adopted.
【０００６】本発明の目的は、三次元実装が達成できる
電子部品および電子部品モジュールを提供することにあ
る。An object of the present invention is to provide an electronic component and an electronic component module which can achieve three-dimensional mounting.
【０００７】本発明の他の目的は、メモリＩＣ以外の他
のＩＣの三次元実装が可能な電子部品および電子部品モ
ジュールを提供することにある。Another object of the present invention is to provide an electronic component and an electronic component module capable of three-dimensionally mounting an IC other than the memory IC.
【０００８】本発明の前記ならびにそのほかの目的と新
規な特徴は、本明細書の記述および添付図面からあきら
かになるであろう。The above and other objects and novel features of the present invention will be apparent from the description of the present specification and the accompanying drawings.
【０００９】[0009]
【課題を解決するための手段】本願において開示される
発明のうち代表的なものの概要を簡単に説明すれば、下
記のとおりである。The outline of the representative ones of the inventions disclosed in the present application will be briefly described as follows.
【００１０】（１）電極を有する半導体部品と、前記電
極に電極を介して接続され前記半導体部品の上下面に亘
って延在する可撓性の配線フィルムと、前記半導体部品
の上下面側の配線フィルム部分の露出面に設けられた電
極とを有する。前記半導体部品の下面側の配線フィルム
部分の露出面には接着剤が設けられている。前記半導体
部品は予備電極位置の所定位置にチップ選択電極を有す
るメモリ集積回路となっている。(1) A semiconductor component having an electrode, a flexible wiring film connected to the electrode through the electrode and extending over the upper and lower surfaces of the semiconductor component, and upper and lower surfaces of the semiconductor component. And an electrode provided on the exposed surface of the wiring film portion. An adhesive is provided on the exposed surface of the wiring film portion on the lower surface side of the semiconductor component. The semiconductor component is a memory integrated circuit having a chip selection electrode at a predetermined position of the preliminary electrode position.
【００１１】（２）電極を有する半導体部品と、前記電
極に電極を介して接続され前記半導体部品の上下面に亘
って延在する可撓性の配線フィルムと、前記半導体部品
の上下面側の配線フィルム部分の露出面に設けられた電
極とを有する電子部品を、相互に電極を介して多段に積
み重ねて接続した構造となっている。前記各電子部品は
チップ選択電極が相互に電気的に独立したメモリ集積回
路となっている。(2) A semiconductor component having an electrode, a flexible wiring film connected to the electrode through the electrode and extending over the upper and lower surfaces of the semiconductor component, and an upper and lower surface side of the semiconductor component. It has a structure in which electronic components having electrodes provided on the exposed surface of the wiring film portion are stacked and connected to each other in multiple stages via electrodes. Each of the electronic components is a memory integrated circuit in which chip selection electrodes are electrically independent from each other.
【００１２】（３）前記（２）の手段にあって、一部の
段において複数の電子部品が並んで取り付けられてい
る。(3) In the above-mentioned means (2), a plurality of electronic components are mounted side by side in some stages.
【００１３】（４）積層状態の複数の半導体部品と、前
記各半導体部品の電極と電極を介して電気的に接続され
る可撓性の配線フィルムとを有し、前記配線フィルムは
前記最下段の半導体部品の下面側に延在し下面に電極を
有する。前記配線フィルムは積層された複数の半導体部
品を包んで構造となっている。(4) A plurality of semiconductor components in a stacked state and a flexible wiring film electrically connected to the electrodes of each semiconductor component via the electrodes, wherein the wiring film is the lowermost layer. Of the semiconductor component extends to the lower surface side and has an electrode on the lower surface. The wiring film has a structure that wraps a plurality of stacked semiconductor components.
【００１４】（５）前記手段（４）の構成において、前
記配線フィルムは一定長さで交互に折り返えされ、前記
折り返しによって形成された下層および上層の配線フィ
ルム部分間に半導体部品が挟まれている構造となってい
る。(5) In the structure of the above-mentioned means (4), the wiring film is alternately folded back at a constant length, and a semiconductor component is sandwiched between the lower and upper wiring film portions formed by the folding back. It has a structure.
【００１５】[0015]
【作用】前記（１）の手段によれば、（ａ）メモリＩＣ
を構成する半導体部品は可撓性の配線フィルムに実装さ
れ、かつ半導体部品の上下面側の配線フィルム部分には
露出した電極が設けられていることから、順次積み重ね
て実装することができ、三次元実装に適した電子部品と
なる。また、メモリＩＣ以外のロジックＩＣ等他のＩＣ
を組み込んだ三次元実装も可能な電子部品となる。According to the means (1), (a) a memory IC
Since the semiconductor components that make up the are mounted on a flexible wiring film and exposed electrodes are provided on the wiring film portions on the upper and lower surfaces of the semiconductor component, they can be sequentially stacked and mounted. It becomes an electronic component suitable for original mounting. Also, other ICs such as logic ICs other than memory ICs
It becomes an electronic component that can be mounted in 3D by incorporating.
【００１６】（ｂ）の手段によれば、前記半導体部品の
下面側の配線フィルム部分の露出面には接着剤が設けら
れているため、電子部品を実装したり順次積み重ねる際
固定が容易となる。According to the means (b), since the adhesive is provided on the exposed surface of the wiring film portion on the lower surface side of the semiconductor component, it becomes easy to fix the electronic components when mounting or sequentially stacking them. .
【００１７】（ｃ）前記半導体部品は予備電極位置の所
定位置にチップ選択電極を有するメモリ集積回路となっ
ていることから、チップ選択電極の位置が異なる複数の
電子部品を選択して重ねて実装することができ、複数の
電子部品を積み重ねてモジュール化を図った場合、実装
面積を増大させることなくメモリ容量を増大させること
ができる。(C) Since the semiconductor component is a memory integrated circuit having a chip selection electrode at a predetermined position of the preliminary electrode position, a plurality of electronic components having different chip selection electrode positions are selected and mounted in a stack. When a plurality of electronic components are stacked and modularized, the memory capacity can be increased without increasing the mounting area.
【００１８】前記（２）の手段によれば、（ａ）上下面
側に電極を有する電子部品を、相互に電極を介して多段
に積み重ねて接続した構造となっていることから、電子
部品モジュールの三次元実装化が図れるとともに、実装
面積の低減が図れる。According to the means (2), (a) the electronic parts having the electrodes on the upper and lower surfaces are connected in a multi-tiered manner with the electrodes interposed therebetween. The three-dimensional mounting can be achieved and the mounting area can be reduced.
【００１９】（ｂ）前記各電子部品はチップ選択電極が
相互に電気的に独立したメモリ集積回路となっているこ
とから、電子部品モジュールの実装面積を増大させるこ
となくメモリ容量の増大を図ることができる。(B) Since each electronic component is a memory integrated circuit whose chip selection electrodes are electrically independent from each other, the memory capacity can be increased without increasing the mounting area of the electronic component module. You can
【００２０】（ｃ）配線フィルムの配線パターンを一般
の配線ボードのようにすることによって、メモリＩＣ以
外のロジックＩＣ等他のＩＣを組み込んだ電子部品モジ
ュールともなる。(C) By forming the wiring pattern of the wiring film on a general wiring board, an electronic component module incorporating another IC such as a logic IC other than the memory IC can be obtained.
【００２１】前記（３）の手段によれば、（ａ）電子部
品の大きさが異なるものも組み込むことができモジュー
ル化が容易となる。According to the above-mentioned means (3), (a) electronic parts having different sizes can be incorporated, which facilitates modularization.
【００２２】（ｂ）配線フィルムの配線パターンを一般
の配線ボードのようにすることによって、メモリＩＣ以
外のロジックＩＣ等他のＩＣを組み込んだ電子部品モジ
ュールともなる。(B) By forming the wiring pattern of the wiring film like a general wiring board, an electronic component module incorporating another IC such as a logic IC other than the memory IC can be obtained.
【００２３】前記（４）の手段によれば、（ａ）複数の
半導体部品が積層状態となっていることから、実装面積
を低減できる電子部品モジュールとなる。According to the means (4), (a) since the plurality of semiconductor components are in a stacked state, the electronic component module can reduce the mounting area.
【００２４】（ｂ）前記配線フィルムは積層された複数
の半導体部品を包んだ構造となり、製造が容易となる。(B) The wiring film has a structure that encloses a plurality of laminated semiconductor components, which facilitates manufacturing.
【００２５】（ｃ）配線フィルムの配線パターンを一般
の配線ボードのようにすることによって、メモリＩＣ以
外のロジックＩＣ等他のＩＣを組み込んだ電子部品モジ
ュールともなる。(C) By forming the wiring pattern of the wiring film on a general wiring board, an electronic component module incorporating another IC such as a logic IC other than the memory IC can be obtained.
【００２６】前記（５）の手段によれば、（ａ）前記配
線フィルムは一定長さで交互に折り返えされ、前記折り
返しによって形成された下層および上層の配線フィルム
部分間に半導体部品が挟まれる構造となっていることか
ら、製造が容易となる。According to the means (5), (a) the wiring film is alternately folded back with a constant length, and the semiconductor component is sandwiched between the lower and upper wiring film portions formed by the folding back. Since the structure is such that it can be manufactured easily.
【００２７】（ｂ）配線フィルムの配線パターンを一般
の配線ボードのようにすることによって、メモリＩＣ以
外のロジックＩＣ等他のＩＣを組み込んだ電子部品モジ
ュールともなる。(B) By making the wiring pattern of the wiring film like a general wiring board, it becomes an electronic component module incorporating other ICs such as logic ICs other than memory ICs.
【００２８】[0028]
【実施例】以下、図面を参照して本発明の実施例を詳細
に説明する。Embodiments of the present invention will be described below in detail with reference to the drawings.
【００２９】なお、実施例を説明するための全図におい
て、同一機能を有するものは同一符号を付け、その繰り
返しの説明は省略する。In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.
【００３０】（実施例１）図１は本発明の一実施例（実
施例１）である電子部品の断面図、図２は同じく斜視
図、図３は同じく電子部品に組み込まれる半導体チップ
の平面図、図４は同じく電子部品の製造で使用する配線
フィルムの平面図、図５は同じく配線フィルムの底面
図、図６は本実施例１の配線フィルムの製造において複
数のフィルムを積み重ねる状態を示す断面図、図７は本
実施例１の配線フィルムの構造を示す断面図、図８は本
実施例１による電子部品モジュールを示す斜視図、図９
は電子部品と電子部品モジュールを実装した状態を示す
模式的斜視図である。(Embodiment 1) FIG. 1 is a sectional view of an electronic component according to an embodiment (Embodiment 1) of the present invention, FIG. 2 is a perspective view thereof, and FIG. 3 is a plan view of a semiconductor chip similarly incorporated in the electronic component. FIG. 4, FIG. 4 is a plan view of the same wiring film used in the manufacture of electronic parts, FIG. 5 is a bottom view of the same wiring film, and FIG. 6 shows a state in which a plurality of films are stacked in the manufacture of the wiring film of the first embodiment. Sectional view, FIG. 7 is a sectional view showing the structure of the wiring film of the first embodiment, FIG. 8 is a perspective view showing an electronic component module according to the first embodiment, and FIG.
FIG. 3 is a schematic perspective view showing a state in which an electronic component and an electronic component module are mounted.
【００３１】本実施例１の電子部品１は、図１に示すよ
うに、半導体部品である半導体チップ２を配線フィルム
３で包み、接着剤１４，１５で一体化した構造となって
いる。半導体チップ２は、下面に電極４を有し、配線フ
ィルム３の内面側に設けられた電極１７と電気的に接続
されている。As shown in FIG. 1, the electronic component 1 of the first embodiment has a structure in which a semiconductor chip 2 which is a semiconductor component is wrapped with a wiring film 3 and integrated with adhesives 14 and 15. The semiconductor chip 2 has an electrode 4 on the lower surface and is electrically connected to an electrode 17 provided on the inner surface side of the wiring film 3.
【００３２】また、半導体チップ２の下面側の配線フィ
ルム３部分には、露出する電極２１が複数設けられてい
る。これらの電極２１は、電子部品１を実装する際に使
用される。また、半導体チップ２の下面側の配線フィル
ム３部分には、接着剤２４が塗布されている。この接着
剤２４は電子部品１を実装する際の接着剤として使用さ
れる。A plurality of exposed electrodes 21 are provided on the wiring film 3 portion on the lower surface side of the semiconductor chip 2. These electrodes 21 are used when mounting the electronic component 1. An adhesive 24 is applied to the wiring film 3 portion on the lower surface side of the semiconductor chip 2. The adhesive 24 is used as an adhesive when mounting the electronic component 1.
【００３３】半導体チップ２の上面側の配線フィルム３
部分の上面（露出面）には、電極２３が複数設けられて
いる。これら電極２３は、電子部品１に重ねられる同一
構造の電子部品の実装用の電極となる。Wiring film 3 on the upper surface side of semiconductor chip 2
A plurality of electrodes 23 are provided on the upper surface (exposed surface) of the portion. These electrodes 23 are electrodes for mounting electronic components of the same structure, which are stacked on the electronic component 1.
【００３４】本実施例１の電子部品１は、メモリ集積回
路からなる半導体チップ２を組み込んだ構造となってい
る。そして、チップ選択電極は、たとえば、並んだ４個
の予備電極位置の所定位置に位置するチップ選択電極を
有する構造となっている。The electronic component 1 of the first embodiment has a structure in which a semiconductor chip 2 composed of a memory integrated circuit is incorporated. The chip selection electrode has, for example, a structure having a chip selection electrode located at a predetermined position of the four preliminary electrode positions arranged side by side.
【００３５】また、本実施例１では、４個の電子部品１
を積み重ねて、図８に示されるような電子部品モジュー
ル４０とされる。この場合、各電子部品１におけるチッ
プ選択電極は、相互に独立している。すなわち、これ
は、後述するが、４個の電子部品１において、それぞれ
組み込まれる半導体チップ２のチップ選択電極の位置が
それぞれ異なる位置にある。In the first embodiment, four electronic components 1 are used.
Are stacked to form an electronic component module 40 as shown in FIG. In this case, the chip selection electrodes in each electronic component 1 are independent of each other. That is, as will be described later, the positions of the chip selection electrodes of the semiconductor chips 2 incorporated in the four electronic components 1 are different from each other, which will be described later.
【００３６】以下、本実施例１の電子部品の構造を、電
子部品の製造および配線フィルム３の製造方法をも参照
しながら説明する。The structure of the electronic component of the first embodiment will be described below with reference to the method of manufacturing the electronic component and the method of manufacturing the wiring film 3.
【００３７】配線フィルム３は、展開状態では図４に示
すようになり、裏面は図５に示すようになっている。The wiring film 3 is as shown in FIG. 4 in the unfolded state, and the back surface is as shown in FIG.
【００３８】前記配線フィルム３に包み込まれる半導体
チップ２は、特に限定はされないが、図３に示すように
正方形となり、主面（表面）の縁に沿って電極４を有し
ている。Although not particularly limited, the semiconductor chip 2 wrapped in the wiring film 3 has a square shape as shown in FIG. 3 and has electrodes 4 along the edge of the main surface (front surface).
【００３９】この半導体チップ２は、たとえば、メモリ
集積回路を構成し、チップ選択電極４ａを有している。
前記電極４のうちの一つがチップ選択電極４ａとなる。
本実施例１では、たとえば、チップ選択電極の配置位置
が異なる半導体チップ２が４種類用意される。図３の半
導体チップ２において、並んだ４箇所が予備電極位置５
ａ〜５ｄとなり、予備電極位置５ａにチップ選択電極４
ａが設けられている。残りの予備電極位置５ｂ，５ｃ，
５ｄには電極が設けられていない。The semiconductor chip 2 constitutes, for example, a memory integrated circuit and has a chip selection electrode 4a.
One of the electrodes 4 becomes the chip selection electrode 4a.
In the first embodiment, for example, four types of semiconductor chips 2 having different chip selection electrode arrangement positions are prepared. In the semiconductor chip 2 of FIG. 3, four lined up are the spare electrode positions 5.
a to 5d, and the chip selection electrode 4 is placed at the preliminary electrode position 5a.
a is provided. The remaining spare electrode positions 5b, 5c,
No electrode is provided on 5d.
【００４０】図示はしないが、残りの３種類の半導体チ
ップ２は、予備電極位置５ｂ，５ｃ，５ｄにそれぞれチ
ップ選択電極が設けられた構造となる。これは、本実施
例１の場合は、電子部品１を４個積み重ねることを意図
としている。したがって、さらに多くの電子部品１を積
み重ねる場合には、その数以上の予備電極位置を有する
複数種類の半導体チップ２を使用する。Although not shown, the remaining three types of semiconductor chips 2 have a structure in which chip selection electrodes are provided at the preliminary electrode positions 5b, 5c and 5d, respectively. This is intended to stack four electronic components 1 in the case of the first embodiment. Therefore, when stacking a larger number of electronic components 1, a plurality of types of semiconductor chips 2 having the number of spare electrode positions or more are used.
【００４１】配線フィルム３は、図４および図５に示す
ように、半導体チップ２の主面に対面する四角形部１０
と、四角形部１０の各辺に連なる略三角形状となる三角
形部１１とからなり、図４に示す四角形部１０の表面部
１２に半導体チップ２を載置し、各三角形部１１を内側
に折り返すことによって、図２に示すように半導体チッ
プ２の側面と裏面を完全に覆うようになる。The wiring film 3 is, as shown in FIGS. 4 and 5, a square portion 10 facing the main surface of the semiconductor chip 2.
And a triangular portion 11 having a substantially triangular shape connected to each side of the square portion 10, the semiconductor chip 2 is mounted on the surface portion 12 of the square portion 10 shown in FIG. 4, and each triangle portion 11 is folded back inward. As a result, the side surface and the back surface of the semiconductor chip 2 are completely covered as shown in FIG.
【００４２】また、前記表面部１２および三角形部１１
の表面部１３には、接着剤１４，１５が設けられ、四角
形部１０の表面部１２および三角形部１１の表面部１３
と、半導体チップ２との接着を図るようになっている。The surface portion 12 and the triangular portion 11 are also provided.
Adhesives 14 and 15 are provided on the surface portion 13 of the rectangular portion 10 and the surface portion 13 of the triangular portion 11.
Then, the semiconductor chip 2 and the semiconductor chip 2 are bonded together.
【００４３】配線フィルム３の表面部１２には電極１７
が設けられている。この電極１７は前記半導体チップ２
の電極４に対応している。An electrode 17 is provided on the surface portion 12 of the wiring film 3.
Is provided. This electrode 17 is the semiconductor chip 2
It corresponds to the electrode 4 of.
【００４４】図５に示される配線フィルム３の裏面にお
いて、四角形部１０の裏面部２０には電子部品１の実装
用の電極２１が設けられ、三角形部１１の裏面部２２に
は積まれる電子部品１を接続するための電極２３が設け
られている。また、裏面部２０には電子部品１を実装す
るための接着剤２４が設けられている。On the back surface of the wiring film 3 shown in FIG. 5, an electrode 21 for mounting the electronic component 1 is provided on the back surface portion 20 of the square portion 10, and an electronic component to be stacked on the back surface portion 22 of the triangular portion 11. An electrode 23 for connecting 1 is provided. Further, the back surface portion 20 is provided with an adhesive 24 for mounting the electronic component 1.
【００４５】一方、配線フィルム３は、特に限定はされ
ないが、図７に示すように、絶縁性の第１フィルム３０
と、この第１フィルム３０に張り合わされる絶縁性の第
２フィルム３１と、前記第１フィルム３０と第２フィル
ム３１との間に延在する配線３２と、前記配線３２に電
気的に接続されて配線フィルム３の表面および裏面に露
出する電極１７，２１，２３とからなっている。なお、
図７においては、接着剤は省略してある。On the other hand, the wiring film 3 is not particularly limited, but as shown in FIG. 7, the insulating first film 30 is used.
And an electrically insulating second film 31 attached to the first film 30, a wire 32 extending between the first film 30 and the second film 31, and electrically connected to the wire 32. And the electrodes 17, 21, 23 exposed on the front and back surfaces of the wiring film 3. In addition,
In FIG. 7, the adhesive is omitted.
【００４６】配線フィルム３の製造においては、最初に
２枚の絶縁性フィルムが用意される。この絶縁性フィル
ムは、たとえば、厚さ０．１ｍｍ程度のポリイミドフィ
ルムからなり、図６に示すように、第１フィルム３０お
よび第２フィルム３１とされる。これらの第１・第２フ
ィルム３０，３１は、パンチングによってスルーホール
３３が開けられる。最終的には前記スルーホール３３が
設けられた部分に前記電極１７，２１，２３が設けられ
る。In manufacturing the wiring film 3, first, two insulating films are prepared. This insulating film is made of, for example, a polyimide film having a thickness of about 0.1 mm, and is a first film 30 and a second film 31, as shown in FIG. Through holes 33 are formed in the first and second films 30 and 31 by punching. Finally, the electrodes 17, 21, 23 are provided in the portion where the through hole 33 is provided.
【００４７】つぎに、前記第１フィルム３０上には配線
を形成するため、たとえば、Ａｌが蒸着で形成され、エ
ッチングによってパターニングされる。Next, for forming wiring on the first film 30, for example, Al is formed by vapor deposition and patterned by etching.
【００４８】つぎに、前記第１フィルム３０と第２フィ
ルム３１は重ね合わされて熱圧着等によって積層され
る。Next, the first film 30 and the second film 31 are superposed and laminated by thermocompression bonding or the like.
【００４９】つぎに、配線フィルム３の表裏面のスルー
ホール３３部分に、ハンダ等からなる電極１７，２１，
２３が形成される（図７参照）。また、配線フィルム３
の表裏面の所定箇所に接着剤１４，１５，２４が形成さ
れ、図４および図５に示される配線フィルム３が形成さ
れる。Next, in the through holes 33 on the front and back surfaces of the wiring film 3, the electrodes 17, 21, made of solder, etc.
23 is formed (see FIG. 7). Also, wiring film 3
Adhesives 14, 15, and 24 are formed at predetermined locations on the front and back surfaces, and the wiring film 3 shown in FIGS. 4 and 5 is formed.
【００５０】このような配線フィルム３を用いて本実施
例１の電子部品１を製造する場合は、図４に示す配線フ
ィルム３の四角形部１０の表面部１２上に、半導体チッ
プ２をフェイスダウンボンディングによって位置決め
し、接着剤１４で接着する。この際、半導体チップ２の
電極４と表面部１２の電極１７は相互に重なる。When the electronic component 1 of the first embodiment is manufactured using such a wiring film 3, the semiconductor chip 2 is face down on the surface portion 12 of the square portion 10 of the wiring film 3 shown in FIG. It is positioned by bonding and is bonded with an adhesive 14. At this time, the electrode 4 of the semiconductor chip 2 and the electrode 17 of the surface portion 12 overlap each other.
【００５１】つぎに、四角形部１０の４辺に連なる三角
形部１１を折り返し、接着剤１５によって電子部品１の
裏面に接着する。その後、加熱処理が施される。これに
よって、ハンダからなる各電極は相互に接着され、図１
および図２に示す電子部品１が製造される。Next, the triangular portion 11 connected to the four sides of the square portion 10 is folded back and adhered to the back surface of the electronic component 1 with the adhesive 15. Then, heat treatment is performed. As a result, the electrodes made of solder are adhered to each other, as shown in FIG.
And the electronic component 1 shown in FIG. 2 is manufactured.
【００５２】本実施例１の電子部品１は、図９に示され
るように、配線ボード３５に実装される。この実装の
際、電子部品１の下面の接着剤２４によって電子部品１
を配線ボード３５に固定し、リフローによって、電子部
品１の下面の電極２１を配線ボード３５の図示しない電
極に接続して実装を終了する。The electronic component 1 of the first embodiment is mounted on the wiring board 35 as shown in FIG. At the time of this mounting, the adhesive 24 on the lower surface of the electronic component 1
Is fixed to the wiring board 35, and the electrode 21 on the lower surface of the electronic component 1 is connected to an electrode (not shown) of the wiring board 35 by reflowing to complete the mounting.
【００５３】図８は本実施例１の電子部品モジュール４
０を示すものである。この電子部品モジュール４０は、
配線フィルム３によって半導体チップ２を包んだ状態に
おいて、半導体チップ２のチップ選択電極の位置がそれ
ぞれ異なる４種類の電子部品１を順次位置決めして重
ね、その後リフローして各電極を一時的に溶かして各電
極の接合を図った末に製造されたものである。すなわ
ち、図示はしないが、最下段から上段に向かう各電子部
品１のチップ選択電極は、４ａ〜４ｄと順次変わる。こ
れによって、実装面積を単一の電子部品１の実装面積と
したままで、メモリ容量を４倍にすることができる。FIG. 8 shows the electronic component module 4 of the first embodiment.
It shows 0. This electronic component module 40 is
In a state where the semiconductor chip 2 is wrapped with the wiring film 3, four types of electronic components 1 having different chip selection electrodes of the semiconductor chip 2 are sequentially positioned and stacked, and then reflowed to temporarily melt each electrode. It is manufactured after joining the electrodes. That is, although not shown, the chip selection electrodes of each electronic component 1 from the bottom to the top sequentially change to 4a to 4d. As a result, the memory capacity can be quadrupled while the mounting area remains the mounting area of the single electronic component 1.
【００５４】図９に配線ボード３５に電子部品モジュー
ル４０を実装した状態を示してある。また、図９におい
て、電子部品１および電子部品モジュール４０の上面の
電極は省略してある。FIG. 9 shows a state in which the electronic component module 40 is mounted on the wiring board 35. Further, in FIG. 9, electrodes on the upper surfaces of the electronic component 1 and the electronic component module 40 are omitted.
【００５５】なお、前記接着剤としては、たとえば、エ
ポキシ樹脂系接着材を使用しているが、一定温度で溶融
するフィルムを使用してもよい。また、電子部品１の下
面の接着剤は設けず、実装時に用意するようにしても良
い。As the adhesive, for example, an epoxy resin adhesive is used, but a film that melts at a constant temperature may be used. Further, the adhesive on the lower surface of the electronic component 1 may not be provided and may be prepared at the time of mounting.
【００５６】また、電極としてハンダバンプを使用しな
いで、異方性導電膜を使用してもよい。Alternatively, an anisotropic conductive film may be used without using the solder bump as the electrode.
【００５７】前記電子部品１において、半導体チップ２
が外気と接触しないように、配線フィルム３の切れ目を
接着剤で覆うようにしても良い。In the electronic component 1, the semiconductor chip 2
The cuts of the wiring film 3 may be covered with an adhesive so as not to come into contact with the outside air.
【００５８】前記電子部品１において信頼性向上のため
に複数枚のフィルムで多重に包み込む構造としても良
い。The electronic component 1 may have a structure in which a plurality of films are multiply wrapped to improve reliability.
【００５９】前記配線フィルム３において、配線３２を
多層構造としても良い。この場合、配線の引回し余裕度
が向上する。In the wiring film 3, the wiring 32 may have a multi-layer structure. In this case, the wiring routing margin is improved.
【００６０】本実施例１の電子部品において、半導体チ
ップとしてロジックＩＣ等他のＩＣを組み込んでもよ
い。この場合、配線フィルム３の配線パターンは通常の
平坦な配線基板の構造と同様な配線となる。このため、
一部の電子部品１においては、電子部品１の上下面の電
極に連なる配線は、電子部品１の上下面の電子部品の電
極に接続されるもの、または上下面側の電子部品の一方
の電極に接続されるもの等の配線構造となる。In the electronic component of the first embodiment, another IC such as a logic IC may be incorporated as a semiconductor chip. In this case, the wiring pattern of the wiring film 3 has the same wiring as the structure of a normal flat wiring board. For this reason,
In some of the electronic components 1, the wiring connected to the electrodes on the upper and lower surfaces of the electronic component 1 is connected to the electrodes of the electronic components on the upper and lower surfaces of the electronic component 1, or one electrode of the electronic components on the upper and lower surfaces. It has a wiring structure such as that connected to.
【００６１】本実施例１の電子部品においては、以下の
効果を奏する。The electronic component of the first embodiment has the following effects.
【００６２】（１）メモリＩＣを構成する半導体部品で
ある半導体チップ２は可撓性の配線フィルム３に実装さ
れ、かつ半導体チップ２の上下面側の配線フィルム３部
分には露出した電極２３，２１が設けられていることか
ら、順次積み重ねて実装することができ、三次元実装に
適したものとなる。(1) The semiconductor chip 2 which is a semiconductor component constituting the memory IC is mounted on the flexible wiring film 3, and the exposed electrodes 23 are formed on the wiring film 3 on the upper and lower surfaces of the semiconductor chip 2. Since 21 is provided, they can be sequentially stacked and mounted, which is suitable for three-dimensional mounting.
【００６３】（２）前記半導体チップ２の下面側の配線
フィルム３部分の露出面には接着剤２４が設けられてい
るため、電子部品１を実装したり順次積み重ねる際固定
が容易となる。(2) Since the adhesive 24 is provided on the exposed surface of the wiring film 3 portion on the lower surface side of the semiconductor chip 2, the electronic parts 1 can be easily fixed when mounting or sequentially stacking them.
【００６４】（３）前記半導体チップ２は予備電極位置
の所定位置にチップ選択電極を有するメモリ集積回路と
なっていることから、チップ選択電極の位置が異なる複
数の電子部品１を選択して重ねて実装することができ、
複数の電子部品１を積み重ねてモジュール化を図った場
合、実装面積を増大させることなくメモリ容量を増大さ
せることができる。(3) Since the semiconductor chip 2 is a memory integrated circuit having a chip selection electrode at a predetermined position of the preliminary electrode position, a plurality of electronic components 1 having different chip selection electrode positions are selected and stacked. Can be implemented as
When a plurality of electronic components 1 are stacked to be modularized, the memory capacity can be increased without increasing the mounting area.
【００６５】（４）配線フィルム３の配線パターンを選
択すれば、メモリＩＣ以外のロジックＩＣ等他のＩＣを
組み込んだ電子部品モジュール製造用の電子部品とな
る。(4) If the wiring pattern of the wiring film 3 is selected, an electronic component for manufacturing an electronic component module incorporating another IC such as a logic IC other than the memory IC is obtained.
【００６６】本実施例１の電子部品モジュールにおいて
は、以下の効果を奏する。The electronic component module of the first embodiment has the following effects.
【００６７】（１）上下面側に電極２３，２１を有する
電子部品１を、相互に電極２３，１１を介して多段に積
み重ねて接続した構造となっていることから、三次元実
装化が図れるとともに、実装面積の低減が図れる。(1) Since the electronic components 1 having the electrodes 23 and 21 on the upper and lower surfaces are stacked and connected to each other through the electrodes 23 and 11 in multiple stages, three-dimensional mounting can be achieved. At the same time, the mounting area can be reduced.
【００６８】（２）前記各電子部品１はチップ選択電極
が相互に電気的に独立したメモリ集積回路となっている
ことから、実装面積を増大させることなくメモリ容量の
増大を図ることができる。(2) Since the chip selection electrodes of each electronic component 1 are electrically independent memory integrated circuits, the memory capacity can be increased without increasing the mounting area.
【００６９】（３）配線フィルム３の配線パターンを選
択すれば、メモリＩＣ以外のロジックＩＣ等他のＩＣを
組み込んだ電子部品モジュールも提供できる。(3) If the wiring pattern of the wiring film 3 is selected, it is possible to provide an electronic component module incorporating another IC such as a logic IC other than the memory IC.
【００７０】（実施例２）図１０は本発明の他の実施例
（実施例２）である電子部品の断面図、図１１は同じく
斜視図である。(Embodiment 2) FIG. 10 is a sectional view of an electronic component which is another embodiment (Embodiment 2) of the present invention, and FIG. 11 is a perspective view of the same.
【００７１】本実施例２の電子部品１は、半導体部品と
してリード（電極）５０がＪ−ベント型となる半導体装
置５１を配線フィルム３で包む構造となっている。した
がって、前記実施例１と同様な効果が得られる。The electronic component 1 according to the second embodiment has a structure in which a lead (electrode) 50 as a semiconductor component is a J-vent type semiconductor device 51 which is wrapped with a wiring film 3. Therefore, the same effect as that of the first embodiment can be obtained.
【００７２】また、本実施例２の電子部品１の場合に
は、半導体装置５１のパッケージ５２内に図示しない半
導体チップが封止されているため、半導体チップの耐湿
性が高い。したがって、図１１に示すように、半導体装
置５１を包む配線フィルム３は、半導体装置５１のパッ
ケージ５２の隅部が露出しても問題がない。本実施例２
の構造では、配線フィルム３による包み込みの余裕度が
高くなり、配線フィルム３による封止作業が容易になる
効果がある。Further, in the case of the electronic component 1 of the second embodiment, since the semiconductor chip (not shown) is sealed in the package 52 of the semiconductor device 51, the moisture resistance of the semiconductor chip is high. Therefore, as shown in FIG. 11, the wiring film 3 wrapping the semiconductor device 51 has no problem even if the corners of the package 52 of the semiconductor device 51 are exposed. Example 2
In the structure (1), the margin of wrapping with the wiring film 3 is increased, and the sealing work with the wiring film 3 is facilitated.
【００７３】本実施例２の他の構成としては、前記半導
体装置としては、リードが真っ直ぐ下方に延在するバッ
トリード型半導体装置やＢＧＡ（ball grid array)を組
み込んでも同様の効果を得ることができる。As another configuration of the second embodiment, the same effect can be obtained even if a butt-lead type semiconductor device or a BGA (ball grid array) in which leads extend straight downward is incorporated as the semiconductor device. it can.
【００７４】（実施例３）図１２は本発明の他の実施例
（実施例３）である電子部品モジュールを示す斜視図、
図１３は電子部品モジュールの配線接続状態を示す模式
図である。(Embodiment 3) FIG. 12 is a perspective view showing an electronic component module which is another embodiment (Embodiment 3) of the present invention.
FIG. 13 is a schematic diagram showing a wiring connection state of the electronic component module.
【００７５】本実施例３の電子部品モジュール５５は４
段に本実施例１による電子部品１を積み重ねた構造で、
電子部品モジュール５５の下面には実装用の電極が設け
られている。この実施例の場合は、一部の段において複
数、たとえば、２個の電子部品１を並べて実装し、電子
部品モジュールとしてさらに多機能化を図ったものであ
る。図１２において、最上段の電子部品１の上の面の電
極は省略してある。The electronic component module 55 of the third embodiment has four
With a structure in which the electronic components 1 according to the first embodiment are stacked in layers,
Electrodes for mounting are provided on the lower surface of the electronic component module 55. In the case of this embodiment, a plurality of, for example, two electronic components 1 are mounted side by side in some stages to further increase the functionality as an electronic component module. In FIG. 12, electrodes on the upper surface of the uppermost electronic component 1 are omitted.
【００７６】図１３は、配線３２と配線３２に設けられ
た電極１７，２１，２３と、半導体チップ２と半導体チ
ップ２に設けられた電極４を示した模式図であり、配線
フィルム３の絶縁性フィルムは省略してある。また、図
面を明瞭にするために配線３２は二点鎖線で描き、かつ
配線３２に設けられた電極１７，２１，２３と、半導体
チップ２の電極４との間は隙間をもたせてある。また、
一部の配線３２は、配線フィルム３が配線構造となるた
め、上と下の半導体チップ２の電極を接続するための配
線ともなっている。FIG. 13 is a schematic view showing the wiring 32, the electrodes 17, 21 and 23 provided on the wiring 32, and the semiconductor chip 2 and the electrode 4 provided on the semiconductor chip 2. The insulation of the wiring film 3 is shown in FIG. The plastic film is omitted. Further, the wiring 32 is drawn by a two-dot chain line for clarity of the drawing, and a gap is provided between the electrodes 17, 21, 23 provided on the wiring 32 and the electrode 4 of the semiconductor chip 2. Also,
Since the wiring film 3 has a wiring structure, some of the wirings 32 are also wirings for connecting the electrodes of the upper and lower semiconductor chips 2.
【００７７】本実施例３の電子部品モジュール５５は、
電子部品１の大きさが異なるものも組み込むことができ
モジュール化が容易となる。また、メモリＩＣ以外のロ
ジックＩＣ等他のＩＣをも組み込むことができる。The electronic component module 55 of the third embodiment is
The electronic parts 1 having different sizes can be incorporated, which facilitates modularization. Further, other ICs such as a logic IC other than the memory IC can be incorporated.
【００７８】（実施例４）図１４は本発明の他の実施例
（実施例４）である電子部品モジュールを示す斜視図、
図１５は電子部品モジュールの配線接続状態を示す一部
の断面図である。本実施例４および次の本実施例５は、
積層状態の複数の半導体部品（半導体装置や半導体チッ
プ）と、前記各半導体部品の電極と電極を介して電気的
に接続される可撓性の配線フィルムとを有し、前記配線
フィルムは前記最下段の半導体部品の下面側に延在し下
面に電極を有する構造となっている。(Embodiment 4) FIG. 14 is a perspective view showing an electronic component module according to another embodiment (Embodiment 4) of the present invention.
FIG. 15 is a partial cross-sectional view showing a wiring connection state of the electronic component module. This Example 4 and the following Example 5 are
The semiconductor device has a plurality of semiconductor components (semiconductor devices or semiconductor chips) in a stacked state, and electrodes of the semiconductor components and a flexible wiring film electrically connected through the electrodes. The structure is such that it extends to the lower surface side of the lower semiconductor component and has electrodes on the lower surface.
【００７９】本実施例４の電子部品モジュール６０は、
図１５に示すように、積み重ねられた複数の半導体装置
５１（Ｊ−ベント型）を配線フィルム３で包む構造とな
っている。したがって、配線３２との電気的接続は、半
導体装置５１のパッケージ５２の側面に突出するリード
５０に配線３２に接続される電極１７を電気的に接続さ
せる構造となっている。したがって、配線フィルム３の
配線パターンを一般のマザーボードのように形成するこ
とによって、メモリＩＣ以外のロジックＩＣ等他のＩＣ
の組み込みも達成できる。The electronic component module 60 of the fourth embodiment is
As shown in FIG. 15, the stacked semiconductor devices 51 (J-vent type) are wrapped with the wiring film 3. Therefore, the electrical connection with the wiring 32 has a structure in which the electrode 50 connected to the wiring 32 is electrically connected to the lead 50 protruding to the side surface of the package 52 of the semiconductor device 51. Therefore, by forming the wiring pattern of the wiring film 3 like a general mother board, other ICs such as logic ICs other than memory ICs can be obtained.
Can also be incorporated.
【００８０】本実施例４の電子部品モジュール６０は、
複数の半導体装置５１が積層状態となっていることか
ら、実装面積を低減できる電子部品モジュールとなる。The electronic component module 60 of the fourth embodiment is
Since the plurality of semiconductor devices 51 are stacked, the electronic component module can have a reduced mounting area.
【００８１】また、配線フィルム３は積層された複数の
半導体装置５１を包んだ構造となり、製造が容易とな
る。Further, the wiring film 3 has a structure in which a plurality of semiconductor devices 51 laminated is wrapped, which facilitates manufacturing.
【００８２】（実施例５）図１６は本発明の他の実施例
（実施例５）である電子部品モジュールを示す模式図、
図１７は電子部品モジュールの配線接続状態を示す一部
断面図である。(Embodiment 5) FIG. 16 is a schematic diagram showing an electronic component module which is another embodiment (Embodiment 5) of the present invention,
FIG. 17 is a partial cross-sectional view showing a wiring connection state of the electronic component module.
【００８３】本実施例５の電子部品モジュール６５は、
一定長さで交互に折り返えされた配線フィルム３の間に
半導体チップ２を挟む構造となっている。すなわち、配
線フィルム３を一定長さで交互に折り返えし、折り返し
によって形成された下層および上層の配線フィルム部分
間に半導体チップ２を挟み、半導体チップ２の電極４と
配線フィルム３の電極１７とを電気的に接続した構造と
なっている。The electronic component module 65 of the fifth embodiment is
The structure is such that the semiconductor chip 2 is sandwiched between the wiring films 3 which are alternately folded back with a constant length. That is, the wiring film 3 is alternately folded back with a fixed length, the semiconductor chip 2 is sandwiched between the wiring film portions of the lower layer and the upper layer formed by folding back, and the electrode 4 of the semiconductor chip 2 and the electrode 17 of the wiring film 3 are sandwiched. It has a structure in which and are electrically connected.
【００８４】図１７は、半導体チップ２と半導体チップ
２に設けられた電極４と、配線３２と配線３２に設けら
れた電極１７，２１を示した模式図であり、配線フィル
ム３の絶縁性フィルムは省略してある。また、図面を明
瞭にするために配線３２は二点鎖線で描き、かつ配線３
２に設けられた電極１７，２１と、半導体チップ２の電
極４との間は隙間をもたせてある。また、一部の配線３
２は、配線フィルム３が配線構造となるため、上と下の
半導体チップ２の電極を接続するための配線ともなって
いる。FIG. 17 is a schematic view showing the semiconductor chip 2, the electrode 4 provided on the semiconductor chip 2, the wiring 32, and the electrodes 17 and 21 provided on the wiring 32. The insulating film of the wiring film 3 is shown in FIG. Is omitted. In addition, the wiring 32 is drawn with a chain double-dashed line to clarify the drawing, and the wiring 3
A gap is provided between the electrodes 17 and 21 provided on the second electrode 2 and the electrode 4 of the semiconductor chip 2. Also, some wiring 3
Since the wiring film 3 has a wiring structure, the wiring 2 also serves as a wiring for connecting the electrodes of the upper and lower semiconductor chips 2.
【００８５】本実施例５の電子部品モジュール６５は、
半導体チップ２を配線フィルム３を一定長さで交互に折
り返えし、折り返しによって形成された下層および上層
の配線フィルム部分間に挟む構造となっていることか
ら、製造が容易となる。The electronic component module 65 of the fifth embodiment is
The semiconductor chip 2 has a structure in which the wiring film 3 is alternately folded back with a constant length and is sandwiched between the wiring film portions of the lower layer and the upper layer formed by folding back, which facilitates manufacturing.
【００８６】本実施例５においては、半導体チップ２の
代わりにバットリード型半導体装置を折り返しによって
形成された下層および上層の配線フィルム部分間に挟む
構造としても前記実施例同様な効果が得られる。In the fifth embodiment, the same effect as in the previous embodiment can be obtained even if the butt-lead type semiconductor device is sandwiched between the lower and upper wiring film portions formed by folding instead of the semiconductor chip 2.
【００８７】以上本発明者によってなされた発明を実施
例に基づき具体的に説明したが、本発明は上記実施例に
限定されるものではなく、その要旨を逸脱しない範囲で
種々変更可能であることはいうまでもない。Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.
【００８８】[0088]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
【００８９】（１）メモリＩＣを構成する半導体部品は
可撓性の配線フィルムに実装され、かつ半導体部品の上
下面側の配線フィルム部分には露出した電極が設けられ
ていることから、順次積み重ねて実装することができ、
三次元実装に適した電子部品となる。(1) Since the semiconductor components constituting the memory IC are mounted on a flexible wiring film and exposed electrodes are provided on the wiring film portions on the upper and lower surfaces of the semiconductor components, they are sequentially stacked. Can be implemented as
It becomes an electronic component suitable for three-dimensional mounting.
【００９０】（２）また、メモリＩＣ以外のロジックＩ
Ｃ等他のＩＣを組み込んだ三次元実装も可能な電子部品
となる。(2) Also, logic I other than the memory IC
It becomes an electronic component in which other ICs such as C are incorporated and three-dimensional mounting is possible.
【００９１】（３）前記半導体部品の下面側の配線フィ
ルム部分の露出面には接着剤が設けられているため、電
子部品を実装したり順次積み重ねる際固定が容易とな
る。(3) Since the adhesive is provided on the exposed surface of the wiring film portion on the lower surface side of the semiconductor component, it is easy to fix the electronic components when mounting or sequentially stacking them.
【００９２】（４）前記半導体部品は予備電極位置の所
定位置にチップ選択電極を有するメモリ集積回路となっ
ていることから、チップ選択電極の位置が異なる複数の
電子部品を選択して重ねて実装することができ、複数の
電子部品を積み重ねてモジュール化を図った場合、実装
面積を増大させることなくメモリ容量を増大させること
ができる。(4) Since the semiconductor component is a memory integrated circuit having a chip selection electrode at a predetermined position of the preliminary electrode position, a plurality of electronic components having different chip selection electrode positions are selected and mounted in a stack. When a plurality of electronic components are stacked and modularized, the memory capacity can be increased without increasing the mounting area.
【００９３】（５）上下面側に電極を有する電子部品
を、相互に電極を介して多段に積み重ねて接続した構造
となっていることから、電子部品モジュールの三次元実
装化が図れるとともに、実装面積の低減が図れる。ま
た、配線フィルムの配線パターンをの選択によって、メ
モリＩＣ以外のロジックＩＣ等他のＩＣの組み込みも達
成できる。(5) Since electronic components having electrodes on the upper and lower surfaces are stacked and connected to each other through electrodes, the electronic component module can be three-dimensionally mounted and mounted. The area can be reduced. Further, by selecting the wiring pattern of the wiring film, it is possible to incorporate other ICs such as logic ICs other than the memory IC.
【００９４】（６）前記各電子部品はチップ選択電極が
相互に電気的に独立したメモリ集積回路となっているこ
とから、電子部品モジュールの実装面積を増大させるこ
となくメモリ容量の増大を図ることができる。(6) Since the chip selection electrodes of each electronic component are memory integrated circuits electrically independent of each other, the memory capacity can be increased without increasing the mounting area of the electronic component module. You can
【図１】本発明の一実施例（実施例１）である電子部品
の断面図である。FIG. 1 is a cross-sectional view of an electronic component that is an embodiment (Embodiment 1) of the present invention.
【図２】本実施例１の電子部品の斜視図である。FIG. 2 is a perspective view of an electronic component of the first embodiment.
【図３】本実施例１の電子部品に組み込まれる半導体チ
ップを示す平面図である。FIG. 3 is a plan view showing a semiconductor chip incorporated in the electronic component of the first embodiment.
【図４】本実施例１の電子部品の製造で使用する配線フ
ィルムの平面図である。FIG. 4 is a plan view of a wiring film used in manufacturing the electronic component of the first embodiment.
【図５】本実施例１の電子部品の製造で使用する配線フ
ィルムの底面図である。5 is a bottom view of the wiring film used in manufacturing the electronic component of the first embodiment. FIG.
【図６】本実施例１の配線フィルムの製造において複数
のフィルムを積み重ねる状態を示す断面図である。FIG. 6 is a cross-sectional view showing a state in which a plurality of films are stacked in manufacturing the wiring film of the first embodiment.
【図７】本実施例１の配線フィルムの構造を示す断面図
である。7 is a cross-sectional view showing the structure of the wiring film of Example 1. FIG.
【図８】本実施例１による電子部品モジュールを示す斜
視図である。FIG. 8 is a perspective view showing an electronic component module according to the first embodiment.
【図９】本実施例１の電子部品と電子部品モジュールを
実装した状態を示す模式的斜視図である。FIG. 9 is a schematic perspective view showing a state in which the electronic component and the electronic component module of the first embodiment are mounted.
【図１０】本発明の他の実施例（実施例２）である電子
部品の断面図である。FIG. 10 is a cross-sectional view of an electronic component that is another embodiment (Embodiment 2) of the present invention.
【図１１】本実施例２の電子部品の斜視図である。FIG. 11 is a perspective view of an electronic component according to a second embodiment.
【図１２】本発明の他の実施例（実施例３）である電子
部品モジュールを示す斜視図である。FIG. 12 is a perspective view showing an electronic component module which is another embodiment (Embodiment 3) of the present invention.
【図１３】本実施例３の電子部品モジュールの配線接続
状態を示す模式図である。FIG. 13 is a schematic diagram showing a wiring connection state of the electronic component module of the third embodiment.
【図１４】本発明の他の実施例（実施例４）である電子
部品モジュールを示す斜視図である。FIG. 14 is a perspective view showing an electronic component module which is another embodiment (Embodiment 4) of the present invention.
【図１５】本実施例４の電子部品モジュールの配線接続
状態を示す一部の断面図である。FIG. 15 is a partial cross-sectional view showing a wiring connection state of the electronic component module of the fourth embodiment.
【図１６】本発明の他の実施例（実施例５）である電子
部品モジュールを示す模式図である。FIG. 16 is a schematic diagram showing an electronic component module which is another embodiment (embodiment 5) of the present invention.
【図１７】本実施例５である電子部品モジュールの配線
接続状態を示す一部断面図である。FIG. 17 is a partial cross-sectional view showing a wiring connection state of the electronic component module according to the fifth embodiment.
１…電子部品、２…半導体チップ、２ａ…チップ選択電
極、３…配線フィルム、４ａ…チップ選択電極、５ａ〜
５ｄ…予備電極位置、１０…四角形部、１１…三角形
部、１２，１３…表面部、１４，１５…接着剤、１７…
電極、２０…裏面部、２１…電極、２２…裏面部、２３
…電極、２４…接着剤、３０…第１フィルム、３１…第
２フィルム、３２…配線、３３…スルーホール、３５…
配線ボード、４０…電子部品モジュール、５０…リー
ド、５１…半導体装置、５２…パッケージ、５５，６
０，６５…電子部品モジュール。DESCRIPTION OF SYMBOLS 1 ... Electronic component, 2 ... Semiconductor chip, 2a ... Chip selection electrode, 3 ... Wiring film, 4a ... Chip selection electrode, 5a ...
5d ... Preliminary electrode position, 10 ... Square portion, 11 ... Triangle portion, 12, 13 ... Surface portion, 14, 15 ... Adhesive agent, 17 ...
Electrode, 20 ... Back surface part, 21 ... Electrode, 22 ... Back surface part, 23
... Electrodes, 24 ... Adhesives, 30 ... First film, 31 ... Second film, 32 ... Wiring, 33 ... Through holes, 35 ...
Wiring board, 40 ... Electronic component module, 50 ... Lead, 51 ... Semiconductor device, 52 ... Package, 55, 6
0,65 ... Electronic component module.
Claims (9)
電極を介して接続され前記半導体部品の上下面に亘って
延在する可撓性の配線フィルムと、前記半導体部品の上
下面側の配線フィルム部分の露出面に設けられた電極と
を有することを特徴とする電子部品。1. A semiconductor component having an electrode, a flexible wiring film connected to the electrode through the electrode and extending over the upper and lower surfaces of the semiconductor component, and wiring on the upper and lower surfaces of the semiconductor component. An electronic component, comprising: an electrode provided on an exposed surface of a film portion.
部分の露出面には接着剤が設けられていることを特徴と
する請求項１記載の電子部品。2. The electronic component according to claim 1, wherein an adhesive is provided on the exposed surface of the wiring film portion on the lower surface side of the semiconductor component.
置にチップ選択電極を有するメモリ集積回路となってい
ることを特徴とする請求項１記載の電子部品。3. The electronic component according to claim 1, wherein the semiconductor component is a memory integrated circuit having a chip selection electrode at a predetermined position of a preliminary electrode position.
電極を介して接続され前記半導体部品の上下面に亘って
延在する可撓性の配線フィルムと、前記半導体部品の上
下面側の配線フィルム部分の露出面に設けられた電極と
を有する電子部品を、相互に電極を介して多段に積み重
ねて接続してなることを特徴とする電子部品モジュー
ル。4. A semiconductor component having an electrode, a flexible wiring film connected to the electrode via the electrode and extending over the upper and lower surfaces of the semiconductor component, and wiring on the upper and lower surfaces of the semiconductor component. An electronic component module, comprising: electronic components each having an electrode provided on an exposed surface of a film portion, which are stacked and connected to each other in multiple stages via electrodes.
に電気的に独立したメモリ集積回路となっていることを
特徴とする請求項４記載の電子部品モジュール。5. The electronic component module according to claim 4, wherein each electronic component is a memory integrated circuit in which chip select electrodes are electrically independent from each other.
で取り付けられていることを特徴とする請求項４記載の
電子部品モジュール。6. The electronic component module according to claim 4, wherein a plurality of electronic components are mounted side by side in some stages.
半導体部品の電極と電極を介して電気的に接続される可
撓性の配線フィルムとを有し、前記配線フィルムは前記
最下段の半導体部品の下面側に延在し下面に電極を有す
ることを特徴とする電子部品モジュール。7. A plurality of semiconductor components in a laminated state and a flexible wiring film electrically connected to the electrodes of each semiconductor component via the electrodes, wherein the wiring film is the lowermost layer. An electronic component module, characterized in that the electronic component module extends to the lower surface side of a semiconductor component and has an electrode on the lower surface.
導体部品を包んでいることを特徴とする請求項７記載の
電子部品モジュール。8. The electronic component module according to claim 7, wherein the wiring film encloses a plurality of stacked semiconductor components.
り返えされ、前記折り返しによって形成された下層およ
び上層の配線フィルム部分間に半導体部品が挟まれてい
ることを特徴とする請求項７記載の電子部品モジュー
ル。9. The wiring film is alternately folded back with a constant length, and a semiconductor component is sandwiched between the wiring film portions of the lower layer and the upper layer formed by the folding back. The described electronic component module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14435095A JP3688755B2 (en) | 1995-06-12 | 1995-06-12 | Electronic components and electronic component modules |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14435095A JP3688755B2 (en) | 1995-06-12 | 1995-06-12 | Electronic components and electronic component modules |
Related Child Applications (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002155783A Division JP2003037246A (en) | 2002-05-29 | 2002-05-29 | Electronic component and electronic component module |
| JP2002155784A Division JP3643570B2 (en) | 2002-05-29 | 2002-05-29 | Electronic components and electronic component modules |
| JP2005085870A Division JP2005184036A (en) | 2005-03-24 | 2005-03-24 | Electronic component and electronic component module |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08340021A true JPH08340021A (en) | 1996-12-24 |
| JP3688755B2 JP3688755B2 (en) | 2005-08-31 |
Family
ID=15360067
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14435095A Expired - Fee Related JP3688755B2 (en) | 1995-06-12 | 1995-06-12 | Electronic components and electronic component modules |
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| Country | Link |
|---|---|
| JP (1) | JP3688755B2 (en) |
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| US6172418B1 (en) | 1998-06-24 | 2001-01-09 | Nec Corporation | Semiconductor device and method for fabricating the same |
| WO2004047173A1 (en) * | 2002-11-20 | 2004-06-03 | Nec Corporation | Semiconductor package and laminated semiconductor package |
| KR100514558B1 (en) * | 1998-09-09 | 2005-09-13 | 세이코 엡슨 가부시키가이샤 | Semiconductor device, method of manufacture thereof, circuit board, and electronic device |
| EP1447845A3 (en) * | 2003-02-12 | 2005-10-12 | Matsushita Electric Industrial Co., Ltd. | Package of electronic components and method for producing the same |
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| US6172418B1 (en) | 1998-06-24 | 2001-01-09 | Nec Corporation | Semiconductor device and method for fabricating the same |
| KR100514558B1 (en) * | 1998-09-09 | 2005-09-13 | 세이코 엡슨 가부시키가이샤 | Semiconductor device, method of manufacture thereof, circuit board, and electronic device |
| CN100438024C (en) * | 2002-11-20 | 2008-11-26 | 日本电气株式会社 | Semiconductor package and laminated semiconductor package |
| WO2004047173A1 (en) * | 2002-11-20 | 2004-06-03 | Nec Corporation | Semiconductor package and laminated semiconductor package |
| US7230328B2 (en) | 2002-11-20 | 2007-06-12 | Nec Corporation | Semiconductor package and laminated semiconductor package |
| EP1447845A3 (en) * | 2003-02-12 | 2005-10-12 | Matsushita Electric Industrial Co., Ltd. | Package of electronic components and method for producing the same |
| US7141874B2 (en) | 2003-05-14 | 2006-11-28 | Matsushita Electric Industrial Co., Ltd. | Electronic component packaging structure and method for producing the same |
| US7443021B2 (en) | 2003-05-14 | 2008-10-28 | Matsushita Electric Industrial Co., Ltd. | Electronic component packaging structure and method for producing the same |
| JP2007067245A (en) * | 2005-08-31 | 2007-03-15 | Sumitomo Bakelite Co Ltd | Film-like interconnect line tape and its manufacturing method, and method of manufacturing semiconductor device using the same |
| JP2007201616A (en) * | 2006-01-24 | 2007-08-09 | Epson Toyocom Corp | Surface mount piezoelectric oscillator, and manufacturing method thereof |
| JP2009540592A (en) * | 2006-06-16 | 2009-11-19 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Stackable IC package with upper and lower interconnects |
| JP2008016528A (en) * | 2006-07-04 | 2008-01-24 | Casio Comput Co Ltd | Semiconductor device and manufacturing method therefor |
| JP2008211264A (en) * | 2008-06-09 | 2008-09-11 | Nec Corp | Semiconductor package and stacked semiconductor package |
| JP4715870B2 (en) * | 2008-06-09 | 2011-07-06 | 日本電気株式会社 | Semiconductor package and stacked semiconductor package |
| JP2009016882A (en) * | 2008-10-20 | 2009-01-22 | Panasonic Corp | Semiconductor device and its manufacturing method |
| JP2011171411A (en) * | 2010-02-17 | 2011-09-01 | Nec Tohoku Ltd | Method of manufacturing semiconductor device |
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