JPH06188362A - Installation structure of semiconductor element - Google Patents
Installation structure of semiconductor elementInfo
- Publication number
- JPH06188362A JPH06188362A JP4334796A JP33479692A JPH06188362A JP H06188362 A JPH06188362 A JP H06188362A JP 4334796 A JP4334796 A JP 4334796A JP 33479692 A JP33479692 A JP 33479692A JP H06188362 A JPH06188362 A JP H06188362A
- Authority
- JP
- Japan
- Prior art keywords
- bare
- bare chip
- substrate
- bare chips
- chips
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、第１と第２のベアチッ
プを重ね合わせることで基板に実装するように形成され
た半導体素子の実装構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting structure for a semiconductor element formed so as to be mounted on a substrate by stacking first and second bare chips.
【０００２】基板に半導体素子を実装することで形成さ
れる電子機器は、近年、高密度実装化が図られるように
なった。そこで、このようなベアチップの実装は、ベア
チップにバンプを形成し、基板にはバンプに対応するフ
ットパターンを形成し、バンプをフットパターンに接続
することで行われる。In recent years, electronic devices formed by mounting semiconductor elements on a substrate have been designed for high-density mounting. Therefore, such bare chip mounting is performed by forming a bump on the bare chip, forming a foot pattern corresponding to the bump on the substrate, and connecting the bump to the foot pattern.
【０００３】したがって、ベアチップが直接基板に固着
されるように形成し、実装効率の向上を図ることが行わ
れていた。Therefore, it has been attempted to improve the mounting efficiency by forming the bare chip directly on the substrate.
【０００４】[0004]
【従来の技術】従来は、図４の従来の説明図に示すよう
に形成されていた。図４の(a) は側面断面図,(b)は平面
図である。2. Description of the Related Art Conventionally, the structure was formed as shown in the conventional explanatory view of FIG. 4A is a side sectional view and FIG. 4B is a plan view.
【０００５】図４の(a)(b)に示すように、テープ12によ
って保持されたフラットリード13の一端をベアチップ10
の電極10A に接続し、他端を基板1 の表面に配設された
フットパターン8 に接続することで基板1 の所定箇所に
ベアチップ10を実装することが行われていた。As shown in FIGS. 4A and 4B, one end of the flat lead 13 held by the tape 12 is attached to the bare chip 10.
It has been practiced to mount the bare chip 10 at a predetermined position on the substrate 1 by connecting the electrode 10A to the electrode 10A and connecting the other end to the foot pattern 8 provided on the surface of the substrate 1.
【０００６】また、ベアチップ10の電極10A 側にはポッ
ティングによって合成樹脂材による保護部材11が設けら
れ、外気と遮断することが行われてる。このようなベア
チップ10の実装は、フラットリード13が固着され、更
に、保護部材11が形成されたベアチップ10をエアの吸引
によって保持する吸着ヘッドによって保持し、フラット
リード13に対応するようフットパターン8 が配設された
基板1 の所定箇所に位置決めし、吸着ヘッドの降下によ
ってフラットリード13をフットパターン8 に圧接させ、
所定温度に加熱し、フットパターン8 に施された予備を
溶融させ、フラットリード13をフットパターン8 に半田
付けすることで行われる。Further, a protective member 11 made of a synthetic resin material is provided on the bare chip 10 on the side of the electrode 10A by potting so as to be shielded from the outside air. In mounting the bare chip 10 as described above, the flat lead 13 is fixed and the bare chip 10 on which the protection member 11 is formed is held by the suction head that holds the air by suction, and the foot pattern 8 corresponding to the flat lead 13 is held. Is positioned at a predetermined position on the substrate 1 on which the flat lead 13 is pressed against the foot pattern 8 by lowering the suction head.
This is performed by heating to a predetermined temperature, melting the preliminary applied to the foot pattern 8, and soldering the flat lead 13 to the foot pattern 8.
【０００７】[0007]
【発明が解決しようとする課題】しかし、このようなフ
ラットリード13を形成することで基板1 にベアチップ10
を実装することでは、基板1 の表面にベアチップ10が所
定間隔で一づつ平面的に配列されることになる。However, the bare chip 10 is formed on the substrate 1 by forming the flat lead 13 as described above.
By mounting, the bare chips 10 are arranged in a plane on the surface of the substrate 1 at predetermined intervals.
【０００８】したがって、一個のベアチップを実装する
ためには所定の占有面積が必要であり、ベアチップを所
定の実装面積を有する基板に実装する場合は、当然、実
装されるベアチップの数量はに限界が生じ、それ以上の
ベアチップの実装は不可能となる問題を有していた。Therefore, a predetermined occupying area is required to mount one bare chip, and when mounting a bare chip on a substrate having a predetermined mounting area, the number of bare chips to be mounted is naturally limited. However, there is a problem in that the bare chip cannot be mounted any further.
【０００９】そこで、本発明では、一個のベアチップを
実装するのに必要な所定の占有面積に二個のベアチップ
の実装が行えるようにすることで、ベアチップの実装密
度の向上を図ることを目的とする。Therefore, an object of the present invention is to improve the mounting density of bare chips by enabling mounting of two bare chips in a predetermined occupying area necessary for mounting one bare chip. To do.
【００１０】[0010]
【課題を解決するための手段】図１は本発明の原理説明
図であり、図１に示すように、第１と第２のベアチップ
2,4 を重ね合わせることで固着し、互いを固着した該第
１と第２のベアチップ2,4 が所定の基板1 に実装される
ように、また、互いのバンプ3,5 が対向するよう重ね合
わせられる第１と第２のベアチップ2,4 と、一端がそれ
ぞれの該バンプ3,5 に挟持され、他端が基板1 のフット
パターン8 に固着されるインナーリード6 と、該第１と
第２のベアチップ2,4 間に充填される接着剤7 とを備
え、該インナーリード6 を介して該第１と第２のベアチ
ップ2,4 が該基板1 に実装されるように構成する。FIG. 1 is a diagram for explaining the principle of the present invention. As shown in FIG. 1, first and second bare chips are provided.
The first and second bare chips 2,4 fixed to each other by stacking the two and four are fixed so that they are mounted on a predetermined substrate 1, and the bumps 3,5 are opposed to each other. The first and second bare chips 2 and 4 to be overlapped with each other, the inner lead 6 having one end sandwiched between the bumps 3 and 5 and the other end fixed to the foot pattern 8 of the substrate 1, and the first and second An adhesive 7 filled between the second bare chips 2 and 4 is provided, and the first and second bare chips 2 and 4 are mounted on the substrate 1 via the inner leads 6.
【００１１】このように構成することによって前述の課
題は解決される。With this configuration, the above-mentioned problems can be solved.
【００１２】[0012]
【作用】即ち、第１と第２のベアチップ2,4 を接着剤7
によって固着し、第１と第２のベアチップ2,4 に形成さ
れたバンプ3,5 がインナーリード6 の一端に接続される
ように形成したものである。[Function] That is, the first and second bare chips 2 and 4 are bonded by the adhesive 7
The bumps 3 and 5 which are fixed to each other and formed on the first and second bare chips 2 and 4 are connected to one end of the inner lead 6.
【００１３】そこで、インナーリード6 の他端を基板1
に配設されたフットパターン8 に接続することでインナ
ーリード6 によって第１と第２のベアチップ2,4 が基板
1 に実装させることが行える。Therefore, the other end of the inner lead 6 is connected to the substrate 1
The inner leads 6 connect the first and second bare chips 2, 4 to the substrate by connecting to the foot pattern 8 arranged on the substrate.
Can be implemented in 1.
【００１４】したがって、一つのベアチップの実装が可
能な実装スペースに第１と第２のベアチップ2,4 の2 組
のベアチップの実装が行えることになり、基板1 に於け
る実装密度が倍になり、高い実装密度を図ることができ
る。Therefore, two sets of bare chips, the first and second bare chips 2 and 4, can be mounted in a mounting space capable of mounting one bare chip, and the mounting density on the substrate 1 is doubled. Therefore, high packaging density can be achieved.
【００１５】[0015]
【実施例】以下本発明を図２および図３を参考に詳細に
説明する。図２は本発明による一実施例の説明図で、
(a) は側面断面図,(b)は結線図, 図３は本発明のベアチ
ップの固着説明図で、(a)(b)は側面図である。全図を通
じて、同一符号は同一対象物を示す。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to FIGS. FIG. 2 is an explanatory view of an embodiment according to the present invention,
(a) is a side sectional view, (b) is a connection diagram, FIG. 3 is an explanatory view of the sticking of the bare chip of the present invention, and (a) and (b) are side views. Throughout the drawings, the same reference numerals denote the same objects.
【００１６】本発明は、図２の(a) に示すように、第１
のベアチップ2 の電極2Aにはバンプ3 を設け、第２のベ
アチップ2 の電極4Aにはバンプ5 を設け、テープ9 によ
って保持されたインナーリード6 の一方の先端部6Aが第
１のベアチップ2 のバンプ3と、第２のベアチップ4 の
バンプ5 とに接続されるように接着剤7 によって固着
し、インナーリード6 の他方の先端部6Bが基板1 に配設
されたフットパターン8にボンディングされるように形
成したものである。The present invention, as shown in FIG.
Bumps 3 are provided on the electrodes 2A of the bare chip 2 and bumps 5 are provided on the electrodes 4A of the second bare chip 2, and one tip 6A of the inner lead 6 held by the tape 9 is attached to the first bare chip 2. The bump 3 and the bump 5 of the second bare chip 4 are fixed by an adhesive 7 so as to be connected, and the other tip portion 6B of the inner lead 6 is bonded to the foot pattern 8 arranged on the substrate 1. It is formed as follows.
【００１７】したがって、第１と第２のベアチップ2,4
を重ね合わせることでインナーリード6 を介して第１と
第２のベアチップ2,4 の実装が基板1 に対して行われる
ようにし、一つのベアチップの実装が行われる実装スペ
ースに第１と第２のベアチップ2,4 の2 組の実装が行え
る。Therefore, the first and second bare chips 2,4
The first and second bare chips 2 and 4 are mounted on the substrate 1 through the inner leads 6 by stacking them, and the first and second bare chips are mounted in the mounting space. Two sets of bare chips 2 and 4 can be mounted.
【００１８】また、この場合、一つのインナーリード6
に入出力される信号が第１と第２のベアチップ2,4 の両
者に接続されることになるため、例えば、図２の(b) に
示すように、インナーリード6 に伝播される選択信号Sa
が第１のベアチップ2 の回路網に接続される電極2Aと、
第２のベアチップ4 の回路網に接続されない空きの電極
4Aとに接続されるようにし、逆に、選択信号Sbを第１の
ベアチップ2 の回路網に接続されない空きの電極2Aと、
第２のベアチップ4 の回路網に接続される電極4Aとに接
続されるように形成すれば、入出力信号S1〜SNが第１と
第２のベアチップ2,4 に接続されていても、選択信号S
a,Sb によって入出力信号S1〜SNを第１のベアチップ2
または第２のベアチップ4 のいづれかに入出力させるよ
う選択することが行える。Also, in this case, one inner lead 6
Since the signal input / output to / from is connected to both the first and second bare chips 2 and 4, for example, as shown in FIG. 2B, the selection signal propagated to the inner lead 6 Sa
Is an electrode 2A connected to the network of the first bare chip 2,
Empty electrode not connected to the circuit of the second bare chip 4
4A, and conversely, the selection signal Sb to the vacant electrode 2A not connected to the circuit network of the first bare chip 2,
If it is formed so as to be connected to the electrode 4A connected to the circuit network of the second bare chip 4, even if the input / output signals S1 to SN are connected to the first and second bare chips 2 and 4, the selection Signal S
Input / output signals S1 to SN are transferred to the first bare chip 2 by a and Sb.
Alternatively, it can be selected to input / output to / from any of the second bare chips 4.
【００１９】したがって、一つのインナーリード6 に第
１と第２のベアチップ2,4 のそれぞれのバンプ3,5 が接
続されていても入出力信号S1〜SNの入出力が第１と第２
のベアチップ2,4 に支障なく選択されることで入出力さ
せることが可能となる。Therefore, even if the bumps 3 and 5 of the first and second bare chips 2 and 4 are connected to one inner lead 6, the input and output of the input and output signals S1 to SN are the first and the second.
It is possible to input and output by selecting the bare chips 2 and 4 without any trouble.
【００２０】また、このような第１と第２ベアチップ2,
4 を固着させることは、図３の(a)に示すように、保持
部材20によってテープ9 と、インナーリード6 とを水平
に保持された上側には吸着ヘッド21により第１のベアチ
ップ2 を保持し、下側には吸着ヘッド22により第２のベ
アチップ4 を保持し、第１のベアチップ2 のバンブ3
と、第２のベアチップ4 のバンプ5 とを対向させ、第１
のベアチップ2 のバンプ3 と、インナーリード6 の先端
部6Aとの位置合わせ、および、第２のベアチップ4 のバ
ンプ5 と、インナーリード6 の先端部6Aとの位置合わせ
を行い、第２のベアチップ4 には所定量の接着剤7 を供
給し、吸着ヘッド21の矢印Z1方向の降下と、吸着ヘッド
22の矢印Z2方向の上昇とを同時に行い、バンブ3 と、バ
ンプ5 とによってインナーリード6 の先端部6Aを挟持す
るように押圧を行う。In addition, the first and second bare chips 2,
As shown in FIG. 3 (a), the fixing of 4 is performed by holding the tape 9 and the inner lead 6 horizontally by the holding member 20 and holding the first bare chip 2 by the suction head 21 on the upper side. The second bare chip 4 is held by the suction head 22 on the lower side, and the bump 3 of the first bare chip 2 is held.
With the bump 5 of the second bare chip 4 facing each other, and
The bump 3 of the bare chip 2 and the tip 6A of the inner lead 6 are aligned with each other, and the bump 5 of the second bare chip 4 and the tip 6A of the inner lead 6 are aligned with each other. A predetermined amount of adhesive 7 is supplied to 4, and the suction head 21 descends in the direction of arrow Z1 and
22 is simultaneously raised in the direction of the arrow Z2, and the bumps 3 and the bumps 5 are pressed so as to sandwich the tip portions 6A of the inner leads 6.
【００２１】このように第１のベアチップ2 と第２のベ
アチップ4 とを重ね合わせ、接着剤7 を硬化させること
で図３の(b) に示すように、第１のベアチップ2 と第２
のベアチップ4 とが接着剤7 を介して固着させることが
できる。In this way, the first bare chip 2 and the second bare chip 4 are superposed and the adhesive 7 is hardened to cure the first bare chip 2 and the second bare chip 2 as shown in FIG. 3 (b).
And the bare chip 4 can be fixed to each other via the adhesive 7.
【００２２】そこで、インナーリード6 を所定の長さL
に切断することと、矢印F のように屈折させるフオーミ
ングとを行い、インナーリード6 が基板1 に配設された
フットパターン8 に対して容易にボンディングすること
ができるように形成する。Therefore, the inner lead 6 is provided with a predetermined length L
The inner lead 6 is formed so that it can be easily bonded to the foot pattern 8 provided on the substrate 1 by cutting the inner lead 6 and bending it as shown by the arrow F 1.
【００２３】このように構成すると、一個のベアチップ
を実装するスペースに対して2 個のベアチップの実装が
行われることになり、実装密度の向上が得られる。According to this structure, two bare chips are mounted in the space for mounting one bare chip, and the mounting density can be improved.
【００２４】[0024]
【発明の効果】以上説明したように、本発明によれば、
2 組のベアチップを重ね合わせることで、一個のベアチ
ップの実装スぺースに実装を行うことができ、実装密度
が倍増されることになる。As described above, according to the present invention,
By stacking two sets of bare chips, it is possible to mount in the mounting space of one bare chip, and the mounting density will be doubled.
【００２５】したがって、所定の基板に対するベアチッ
プの実装量が増加することで、小形化が図れ、更に、接
着剤によって2 組のベアチップを固着することで、従来
行われていたベアチップの回路面を保護するポッティン
グ工程が不要となり、実用的効果は大である。Therefore, the mounting amount of the bare chip on a predetermined substrate is increased, so that the size can be reduced. Further, by fixing the two bare chips with an adhesive, the circuit surface of the bare chip which has been conventionally used can be protected. This eliminates the need for the potting step, and has a great practical effect.
【図１】 本発明の原理説明図FIG. 1 is an explanatory view of the principle of the present invention.
【図２】 本発明による一実施例の説明図FIG. 2 is an explanatory diagram of an embodiment according to the present invention.
【図３】 本発明のベアチップの固着説明図FIG. 3 is an explanatory view of the sticking of the bare chip of the present invention.
【図４】 従来の説明図FIG. 4 is a conventional explanatory diagram.
１ 基板 ２ 第１のベアチップ 3,5 バンプ ４ 第２のベアチップ ６ インナーリード ７ 接着剤 1 substrate 2 first bare chip 3,5 bump 4 second bare chip 6 inner lead 7 adhesive
フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０５Ｋ 1/18 Ｓ 7128−4Ｅ Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display area H05K 1/18 S 7128-4E
Claims (1)
合わせられる第１と第２のベアチップ(2,4) と、一端が
それぞれの該バンプ(3,5) に挟持され、他端が基板(1)
のフットパターン(8) に固着されるインナーリード(6)
と、該第１と第２のベアチップ(2,4) 間に充填される接
着剤(7) とを備え、該インナーリード(6) を介して該第
１と第２のベアチップ(2,4) が該基板(1) に実装される
ことを特徴とする半導体素子の実装構造。1. A first and a second bare chip (2, 4) which are stacked so that their bumps (3, 5) face each other, and one end is sandwiched between the bumps (3, 5), and the other. Board edge (1)
Inner leads (6) that attach to the foot pattern (8) of
And an adhesive (7) filled between the first and second bare chips (2, 4), and the first and second bare chips (2, 4) via the inner lead (6). ) Is mounted on the substrate (1), a mounting structure of a semiconductor element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4334796A JPH06188362A (en) | 1992-12-16 | 1992-12-16 | Installation structure of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4334796A JPH06188362A (en) | 1992-12-16 | 1992-12-16 | Installation structure of semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06188362A true JPH06188362A (en) | 1994-07-08 |
Family
ID=18281325
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4334796A Withdrawn JPH06188362A (en) | 1992-12-16 | 1992-12-16 | Installation structure of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06188362A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5949135A (en) * | 1997-07-15 | 1999-09-07 | Mitsubishi Denki Kabushiki Kaisha | Module mounted with semiconductor device |
| KR100355744B1 (en) * | 2000-10-25 | 2002-10-19 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package structure |
| US7112468B2 (en) | 1998-09-25 | 2006-09-26 | Stmicroelectronics, Inc. | Stacked multi-component integrated circuit microprocessor |
| US8384200B2 (en) | 2006-02-20 | 2013-02-26 | Micron Technology, Inc. | Semiconductor device assemblies including face-to-face semiconductor dice and systems including such assemblies |
-
1992
- 1992-12-16 JP JP4334796A patent/JPH06188362A/en not_active Withdrawn
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5949135A (en) * | 1997-07-15 | 1999-09-07 | Mitsubishi Denki Kabushiki Kaisha | Module mounted with semiconductor device |
| US7112468B2 (en) | 1998-09-25 | 2006-09-26 | Stmicroelectronics, Inc. | Stacked multi-component integrated circuit microprocessor |
| KR100355744B1 (en) * | 2000-10-25 | 2002-10-19 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package structure |
| US8384200B2 (en) | 2006-02-20 | 2013-02-26 | Micron Technology, Inc. | Semiconductor device assemblies including face-to-face semiconductor dice and systems including such assemblies |
| US8927332B2 (en) | 2006-02-20 | 2015-01-06 | Micron Technology, Inc. | Methods of manufacturing semiconductor device assemblies including face-to-face semiconductor dice |
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