JPS5864095A - Multilayer circuit board with connecting pins - Google Patents

Multilayer circuit board with connecting pins

Info

Publication number
JPS5864095A
JPS5864095A JP16273981A JP16273981A JPS5864095A JP S5864095 A JPS5864095 A JP S5864095A JP 16273981 A JP16273981 A JP 16273981A JP 16273981 A JP16273981 A JP 16273981A JP S5864095 A JPS5864095 A JP S5864095A
Authority
JP
Japan
Prior art keywords
wiring board
multilayer
multilayer wiring
board
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16273981A
Other languages
Japanese (ja)
Inventor
幸雄 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP16273981A priority Critical patent/JPS5864095A/en
Publication of JPS5864095A publication Critical patent/JPS5864095A/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は、多層配線基板に外部接続用ピンが取付けられ
た接続用ピン付多層配線基板に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multilayer wiring board with connection pins, in which external connection pins are attached to the multilayer wiring board.

集積回路技術の進歩によって、基板上への素子の搭載は
9個別トランジスタの搭載から半導体集積回路の搭載そ
して、複数個のLSIの搭載へと向かって来た。それに
伴い、混成集積回路においては、同一基板上に高密度な
回路を構成する必要に迫られ、−液の基板上に実装でき
る回路密度は限定されているので、より実装密度を向上
させるために、内部配線の多層化された多層配線基板が
使用されている。
With the advancement of integrated circuit technology, the mounting of elements on a substrate has progressed from mounting nine individual transistors to mounting semiconductor integrated circuits and then mounting multiple LSIs. Accordingly, in hybrid integrated circuits, it is necessary to configure high-density circuits on the same substrate, and since the circuit density that can be mounted on a liquid substrate is limited, it is necessary to further improve the mounting density. , a multilayer wiring board with multiple layers of internal wiring is used.

従来、厚膜混成集積回路′用多層配線基板として。Conventionally, used as a multilayer wiring board for thick film hybrid integrated circuits.

絶縁性、熱放散性2機械的強度に優れた多層セラミック
基板が用いられている。
A multilayer ceramic substrate with excellent insulation, heat dissipation properties, and mechanical strength is used.

第1図は、この種の多層配線基板に外部接続用ピンが取
付けら汀た。接続用ピン付多層配線基板の従来例の構成
を示した正面断面図である。図において、1は第1の多
層配線基板、2は接続用ピンである。第1の多層配線基
板1は、多層セラミ、り板11とMoやWなどからなる
第1の導電体12から構成される◎そして、第1の導電
体12は、複数のセラミック材が積層された多層セラミ
ック板11の内部及び表面に配線されている。このよう
な構造の接続用ピン付多層配線基板は、セラミック材が
焼結前の状態、いわゆるグリーンシートの状態のときに
、そのグリーンシート上にMoやWなどの導体ペースト
で配線をスクリーン印刷し、このようにして配線された
複数のセラミック材を位置を合わせて積層し、それから
焼結して第1の多層配線基板1を形成−し、その後接続
爪ピン2をロウ付けして製造する。
In FIG. 1, external connection pins are attached to this type of multilayer wiring board. FIG. 2 is a front sectional view showing the configuration of a conventional example of a multilayer wiring board with connection pins. In the figure, 1 is a first multilayer wiring board, and 2 is a connection pin. The first multilayer wiring board 1 is composed of a multilayer ceramic plate 11 and a first conductor 12 made of Mo, W, etc. ◎The first conductor 12 is composed of a plurality of laminated ceramic materials. Wiring is conducted inside and on the surface of the multilayer ceramic board 11. A multilayer wiring board with connection pins having such a structure is produced by screen-printing wiring with a conductive paste such as Mo or W on a green sheet while the ceramic material is in a state before sintering, a so-called green sheet state. A plurality of ceramic materials wired in this manner are aligned and laminated, and then sintered to form the first multilayer wiring board 1, and then the connecting claw pins 2 are brazed to manufacture it.

基板の配線は、一般に、電源やグランドとして使用され
る比較的粗い配線の電源用配線と、信号用の高密度で微
細な配線の信号用配線とに分けられる。従って、第1図
の接続用ピン付多層配線基板においては、基板の信号用
配線も多層セラミック板11の内部及び表面に配線して
いた。しかしながら、従来の製造過程では、高温で焼結
するため2個々のセラミック材の板厚を薄くすることや
信号用配線の線幅を微細にすることに限界があった。ま
た、高温焼結のため、配線に使用される第1の導電体1
2は、セラミック材の焼結温度に耐えられる前記Moや
Wの高融点金属に限られていた。
Wiring on a substrate is generally divided into power supply wiring, which is a relatively coarse wiring used as a power supply or ground, and signal wiring, which is a high-density and fine wiring for signals. Therefore, in the multilayer wiring board with connection pins shown in FIG. 1, the signal wiring of the board was also wired inside and on the surface of the multilayer ceramic board 11. However, in the conventional manufacturing process, since the ceramic material is sintered at a high temperature, there is a limit in reducing the thickness of the two individual ceramic materials and in making the line width of the signal wiring finer. In addition, due to high temperature sintering, the first conductor 1 used for wiring
No. 2 has been limited to high melting point metals such as Mo and W, which can withstand the sintering temperature of ceramic materials.

従って9例えば複数個のLSIチップを基板上に実装す
るようなマルチチップLSIでは基板がキャリアの役目
を果すので、第1の導電体12の電気抵抗が大きい基板
は9回路特性として好ましいものではない。
Therefore, for example, in a multi-chip LSI in which multiple LSI chips are mounted on a board, the board plays the role of a carrier, so a board where the electrical resistance of the first conductor 12 is large is not desirable in terms of circuit characteristics. .

本発明の目的は、高密度微細な配線層を形成した接続用
ピン付多層配線基板を提供することにある。
An object of the present invention is to provide a multilayer wiring board with connection pins in which a high-density and fine wiring layer is formed.

本発明の他の目的は、信号用配線の導電体として電気抵
抗の低い通常の導体金属を用いることを可能にした接続
用ピン付多層配線基板を提供することにある。
Another object of the present invention is to provide a multilayer wiring board with connection pins that makes it possible to use ordinary conductive metals with low electrical resistance as conductors for signal wiring.

本発明によると、複数のセラミック材が積層された多層
セラミ、り板および該多層セラミック板の内部と表面に
配線された第1の導電体とから構成される第1の多層配
線基板に外部接続用ピンが取付けられた接続用ピン付多
層配線基板、において。
According to the present invention, an external connection is made to a first multilayer wiring board that is composed of a multilayer ceramic plate in which a plurality of ceramic materials are laminated, and a first conductor wired inside and on the surface of the multilayer ceramic plate. In a multilayer wiring board with connection pins on which connection pins are attached.

前記第1の多層配線基板の表面の一部分に、複数の低温
焼成無機絶縁材が積層された多層無機絶縁板および該多
層無機絶縁板の内部と表面に配線された第2の導電体と
から構成される第2の多層配線基板を両溝電体が電気的
に接続するように形成してなる多層配線基板とすると共
に、前記第1の多層配線基板の表面の他の部分で前記第
1の導電体に固着した外部接続用ピンを取付けた接続用
、ピン付多層配線基板が得られる。
A multilayer inorganic insulating board in which a plurality of low-temperature fired inorganic insulating materials are laminated on a part of the surface of the first multilayer wiring board, and a second conductor wired inside and on the surface of the multilayer inorganic insulating board. A second multilayer wiring board is formed such that both groove electric bodies are electrically connected, and another part of the surface of the first multilayer wiring board is connected to the first multilayer wiring board. A multilayer wiring board with external connection pins fixed to a conductor is obtained.

以下9本発明の実施例につき図面を参照して説明するみ 第2図は9本発明の一実施例の構成を示した正面断面図
である。図において、1は第1の多層配線基板、 2 
、2’は接続用ピン、20は第2の多層配線基板である
。第1の多層配線基板1は、従来と同様、複数のセラミ
ック材が積層された多層セラミック板11と、多層セラ
ミツ〉板11の内部及び表面に配線されたMoやWから
なる第1の導電体12とから構成され、その製造法も従
来と同様である。一方、第2の多層配線基板2oは、複
数の低温焼成無機絶縁材が積層された多層無機絶縁板2
1と、多層無機絶縁板21の内部及び表面に配線された
第2の導電体22とから構成される。
Hereinafter, nine embodiments of the present invention will be described with reference to the drawings. FIG. 2 is a front sectional view showing the structure of one embodiment of the present invention. In the figure, 1 is a first multilayer wiring board, 2
, 2' are connection pins, and 20 is a second multilayer wiring board. The first multilayer wiring board 1 includes a multilayer ceramic board 11 in which a plurality of ceramic materials are laminated, and a first conductor made of Mo or W wired inside and on the surface of the multilayer ceramic board 11, as in the conventional case. 12, and its manufacturing method is the same as the conventional one. On the other hand, the second multilayer wiring board 2o is a multilayer inorganic insulating board 2 in which a plurality of low-temperature fired inorganic insulating materials are laminated.
1, and a second conductor 22 wired inside and on the surface of the multilayer inorganic insulating board 21.

図に示されるように、第1の多層配線基板1の表面の一
部分に第2の多層配線基板20が両溝電体12.22が
電気的に接続するように形成され。
As shown in the figure, a second multilayer wiring board 20 is formed on a part of the surface of the first multilayer wiring board 1 so that both groove electric bodies 12 and 22 are electrically connected.

且つ接続用♂ン2,2′は、第1の多層配線基板1の表
面の他の部分(本実施例では周辺部分)で第1の導電体
12に固着されている。ことに使用され込低温焼成無機
絶縁材としては9例えば100℃焼成ができる住人化学
工業■製スミセラム(商品名)、150℃焼成ができる
東亜合成化学工業■製アロンセラミック(商品名)など
がある。
In addition, the connecting pins 2 and 2' are fixed to the first conductor 12 at other parts of the surface of the first multilayer wiring board 1 (in this embodiment, the peripheral parts). Examples of low-temperature fired inorganic insulating materials that are commonly used include Sumiceram (trade name) manufactured by Susumu Kagaku Kogyo ■, which can be fired at 100 degrees Celsius, and Aron Ceramic manufactured by Toagosei Chemical Industry ■ (trade name), which can be fired at 150 degrees Celsius. .

このような構成により、第1の多層配線基板1の配線は
、前述した欠点があるので、電源やグランドの粗い配線
ですむ電源用配線に使用する。一方、第2の多層配線基
板2oは、低温焼成の無機絶縁板21で構成されている
ため9個々の基板の板厚を薄くでき、配線の線幅も微細
にすることができる・従って、第2の多層配線基板2o
の配線は、信号用の高密度微細な配線である信号用配線
として使用する。
With such a configuration, the wiring of the first multilayer wiring board 1 has the above-mentioned drawbacks, and is therefore used for power supply wiring, which requires rough wiring for the power supply and ground. On the other hand, since the second multilayer wiring board 2o is composed of an inorganic insulating board 21 fired at a low temperature, the thickness of each board can be reduced, and the line width of the wiring can also be made fine. 2 multilayer wiring board 2o
The wiring is used as a signal wiring, which is a high-density and fine wiring for signals.

又、接続用げン2,2′を第2の多層配線基板20の形
成されてい々側に取付けることにより。
Also, by attaching the connecting wires 2, 2' to each side where the second multilayer wiring board 20 is formed.

第1 、!7)多層配線基板1の特長である。熱放散性
First,! 7) Features of the multilayer wiring board 1. heat dissipation.

機−械的強度を生かすことができた。We were able to take advantage of its mechanical strength.

、更に、第2の多層配線基板20には、低温焼成無機絶
縁材の多層無機絶縁板21が使用されているので、多層
無機絶縁板21の内部及び表面に配線される第2の導電
体22の材料には、従来のM。
Furthermore, since the second multilayer wiring board 20 uses a multilayer inorganic insulating board 21 made of a low-temperature fired inorganic insulating material, the second conductor 22 wired inside and on the surface of the multilayer inorganic insulating board 21 The material is conventional M.

やWと較べてその電気抵抗が数分の1である通常の導体
金属Cuが使用できる。従って、基板の回路特性は、非
常に良くなった。
Ordinary conductive metal Cu, whose electrical resistance is a fraction of that of copper or W, can be used. Therefore, the circuit characteristics of the substrate have been greatly improved.

以上の説明で明らかなように2本発明によると。As is clear from the above description, there are two aspects of the present invention.

高密度微細な配線層を形成でき、且つその回路特性の良
好な接続用ピン付多層配線基板を構成できる。
A multilayer wiring board with connection pins that can form high-density, fine wiring layers and has good circuit characteristics can be constructed.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、従来例の構成を示した正面断面図。 第2図は2本発明の一実施例の構成を示した正面断面図
である。 記号の説明: 1は第1の多層配線基板、2.2’は接続用ピン、  
11は多層セラミック板、  12は第1の導電体、2
0は第2の多層配線基板、  21は多層無機絶縁板、
 22は第2の導電体をそれぞれあられしている。
FIG. 1 is a front sectional view showing the configuration of a conventional example. FIG. 2 is a front sectional view showing the configuration of an embodiment of the present invention. Explanation of symbols: 1 is the first multilayer wiring board, 2.2' is the connection pin,
11 is a multilayer ceramic plate, 12 is a first conductor, 2
0 is a second multilayer wiring board, 21 is a multilayer inorganic insulating board,
22 denotes the second conductor, respectively.

Claims (1)

【特許請求の範囲】[Claims] 1、 複数のセラミック材が積層された多層セラミック
板および該多層セラミック板の内部と表面に配線された
第1の導電体とから構成される第1の多層配線基板に外
部接続用ピンが取付けられた接続用ピン付多層配線基板
において、複数の低温焼成無機絶縁材が積層された多層
無機絶縁板および該多層無機絶縁板の内部と表面に配線
された第2の導電体とから構成される第29多層配線基
板番前記第1の多層配線基板の表面の一部分に両溝電体
が電気的に接続するように形成してなる多層配線基板と
すると共に、前記外部接続用ピンを前記第1の多層配線
基板の表面の他の部分で前記第1の導電体に固着ビたこ
とを特徴とす不接続用ピン付多層配線基板。
1. External connection pins are attached to a first multilayer wiring board consisting of a multilayer ceramic board in which a plurality of ceramic materials are laminated and a first conductor wired inside and on the surface of the multilayer ceramic board. In the multilayer wiring board with connection pins, the second conductor is composed of a multilayer inorganic insulating board in which a plurality of low-temperature fired inorganic insulating materials are laminated, and a second conductor wired inside and on the surface of the multilayer inorganic insulating board. No. 29 Multilayer Wiring Board No. 29 A multilayer wiring board in which both groove electric bodies are formed to be electrically connected to a part of the surface of the first multilayer wiring board, and the external connection pins are connected to the first multilayer wiring board. A multilayer wiring board with non-connection pins, characterized in that another portion of the surface of the multilayer wiring board is fixed to the first conductor.
JP16273981A 1981-10-14 1981-10-14 Multilayer circuit board with connecting pins Pending JPS5864095A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16273981A JPS5864095A (en) 1981-10-14 1981-10-14 Multilayer circuit board with connecting pins

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16273981A JPS5864095A (en) 1981-10-14 1981-10-14 Multilayer circuit board with connecting pins

Publications (1)

Publication Number Publication Date
JPS5864095A true JPS5864095A (en) 1983-04-16

Family

ID=15760335

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16273981A Pending JPS5864095A (en) 1981-10-14 1981-10-14 Multilayer circuit board with connecting pins

Country Status (1)

Country Link
JP (1) JPS5864095A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6147689A (en) * 1984-08-13 1986-03-08 日本電気株式会社 Plug-in package
JPH022699A (en) * 1987-12-22 1990-01-08 Thomson Csf High density hybrid integrated circuit
JPH07797U (en) * 1993-02-17 1995-01-06 株式会社貝印刃物開発センター chisel

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5586195A (en) * 1978-12-25 1980-06-28 Fujitsu Ltd Method of fabricating multilayer circuit board
JPS56115498A (en) * 1980-02-19 1981-09-10 Shimizu Construction Co Ltd Method of executing moving type side wall flask

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5586195A (en) * 1978-12-25 1980-06-28 Fujitsu Ltd Method of fabricating multilayer circuit board
JPS56115498A (en) * 1980-02-19 1981-09-10 Shimizu Construction Co Ltd Method of executing moving type side wall flask

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6147689A (en) * 1984-08-13 1986-03-08 日本電気株式会社 Plug-in package
JPH0476211B2 (en) * 1984-08-13 1992-12-03 Nippon Electric Co
JPH022699A (en) * 1987-12-22 1990-01-08 Thomson Csf High density hybrid integrated circuit
JPH07797U (en) * 1993-02-17 1995-01-06 株式会社貝印刃物開発センター chisel

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