JPH04130757A - Ceramic package for semiconductor element - Google Patents

Ceramic package for semiconductor element

Info

Publication number
JPH04130757A
JPH04130757A JP2249967A JP24996790A JPH04130757A JP H04130757 A JPH04130757 A JP H04130757A JP 2249967 A JP2249967 A JP 2249967A JP 24996790 A JP24996790 A JP 24996790A JP H04130757 A JPH04130757 A JP H04130757A
Authority
JP
Japan
Prior art keywords
substrate
glass ceramic
conductor
package
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2249967A
Other languages
Japanese (ja)
Inventor
Yasuhiro Kurokawa
泰弘 黒川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2249967A priority Critical patent/JPH04130757A/en
Publication of JPH04130757A publication Critical patent/JPH04130757A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49109Connecting at different heights outside the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To enable the propagation delay time and the propagation loss of the signal at very high frequencies to be cut down by a method wherein the title ceramic package for semiconductor element is provided with a composite structure equipped with a multiple layer structure comprising copper conductors and a glass ceramic layer of low permittivity on an aluminum nitride substrate. CONSTITUTION:A glass ceramic layer 17 of low permittivity is formed on a part of one side surface of an AlN substrate 10 while a copper conductors 18 are formed on the glass ceramic layer 17 and the loading part of a semiconductor element 8 of the AlN substrate 10. The semiconductor element 8 loaded on a package is connected to the copper conductor 18 by a bonding wire 9. Since the copper wiring 18 is formed on the glass ceramic layer 17 of low permittivity, the delay time can be cut down comparing with that of the conventional package wherein the W conductor plated with nickel and Au is formed on an alumina substrate of 10 in permittivity.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は高密度配線を有する半導体素子用セラミックパ
ッケージに関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a ceramic package for semiconductor devices having high-density wiring.

[従来の技術] LSI等の半導体素子の高速化、高集積化に伴い、微細
で高密度に配線された導体および多くの外部出力金属ピ
ンを有する半導体素子用パッケージが要求されている。
[Prior Art] As semiconductor devices such as LSIs become faster and more highly integrated, there is a demand for packages for semiconductor devices that have fine, densely wired conductors and many external output metal pins.

特にPGA (Pin Grid^rray )パッケ
ージと呼ばれる数百本程度の金属ピンがパッケージ表面
に格子状に並んだセラミックスパッケージが放熱性や高
信頼性を有するため使用されている。
In particular, a ceramic package called a PGA (Pin Grid^rray) package, in which several hundred metal pins are arranged in a grid pattern on the package surface, is used because of its heat dissipation properties and high reliability.

第5図は従来のセラミックスPGAパッケージの断面図
で、第6図はそれを詳細に示す断面図である。
FIG. 5 is a sectional view of a conventional ceramic PGA package, and FIG. 6 is a sectional view showing it in detail.

従来のセラミックスPGAパッケージは、テープキャス
ティング法により形成したピアホール付きのグリーンシ
ート上にW粉末を主成分とするペーストを印刷した後、
積層および焼成してできたアルミナセラミックス基板1
とタングステン(W>導体2を有する一体構造体である
。この外部金属表面にニッケルメッキ5を施した後、所
定位置に外部出力金属ピン4をACICUろう材6によ
り垂直に接合したのち、最後に金メツキ7が施されてい
る。半導体素子8はパッケージに搭載後、ワイヤボンデ
ィング9によって接続されている。
Conventional ceramic PGA packages are made by printing a paste mainly composed of W powder on a green sheet with peer holes formed by tape casting.
Alumina ceramic substrate 1 made by laminating and firing
and tungsten (W>conductor 2). After applying nickel plating 5 to the external metal surface, external output metal pin 4 is vertically joined to a predetermined position with ACICU brazing material 6, and finally Gold plating 7 is applied. After the semiconductor element 8 is mounted on the package, it is connected by wire bonding 9.

しかしながら近年、内部配線の密度および外部出力ピン
の数が増加する技術動向のなかで、高R波回路や高速用
に適した低電気抵抗の銅導体がれ目されている。
However, in recent years, with technological trends increasing the density of internal wiring and the number of external output pins, copper conductors with low electrical resistance suitable for high R-wave circuits and high speed applications have been overlooked.

銅導体は従来のW導体に比べ、電気抵抗が17〜115
と小さいため、配線抵抗を小さくできるづえに、半田耐
熱性に優れ良好な半田濡れ性を示し超高周波帯での信号
の伝送損失が少なく、エレクトロマイグレイジョンが起
こりにくい等の多くc利点を有する。
Copper conductor has an electrical resistance of 17 to 115 compared to conventional W conductor.
Because of its small size, it has many advantages such as low wiring resistance, excellent solder heat resistance, good solder wettability, low signal transmission loss in ultra-high frequency bands, and less electromigration. .

一方、高速化のために従来のセラミックス材料であるア
ルミナよりも低誘電率材料のガラスセラミックスや有機
のポリイミドなどが期待されている。特に銅ペーストと
ガラスセラミックスを同時焼成する多層配線基板の開発
が期待され、活発に検討されている(日経マグロウヒル
社発行[日経ニューマテリアルJ  1987年8月3
日号、pp93103)。またポリイミドでは、セラミ
ックス基板上にCuやAuなどの信号導体線のみを多層
構造形成する利用の例が多く報告されている(日経マグ
ロウヒル社発行「日経マイクロデバイス」1989年6
月、pp50−61 )。
On the other hand, glass ceramics, which have a lower dielectric constant than alumina, which is a conventional ceramic material, and organic polyimide are expected to increase speed. In particular, the development of multilayer wiring boards that co-fire copper paste and glass ceramics is expected and is being actively studied (Published by Nikkei McGraw-Hill, Inc. [Nikkei New Materials J, August 3, 1987).
issue, pp93103). In addition, there have been many reports of polyimide being used to form a multilayer structure of only signal conductor lines such as Cu or Au on a ceramic substrate (Nikkei Microdevices, published by Nikkei McGraw-Hill, June 1989).
Month, pp50-61).

さらに半導体素子パッケージにおいては放熱性の向上も
重要な特性のひとつであるため、窒化アルミニウム<A
IN>がパッケージ材料として注目を集めている。例え
ば最近、第7図と第8図に示すようなAINセラミック
スと薄膜導体を組み合わせた新しい構造のセラミックス
PGAパッケージが開発されている( Proceed
ings of the 6thInternatio
nal )licrOelectrOnics Con
ference。
Furthermore, since improving heat dissipation is one of the important properties for semiconductor device packages, aluminum nitride < A
IN> is attracting attention as a packaging material. For example, recently, a ceramic PGA package with a new structure combining AIN ceramics and thin film conductors as shown in Figures 7 and 8 has been developed (Proceed
ings of the 6th International
nal )licrOelectrOnics Con
ference.

1990、1)217 )。このパッケージは、電源配
線としてのW導体3および11を同時焼成法により内部
に形成したAlNセラミックス基板10の表面に多層ポ
リイミド絶縁層と薄膜プロセスによる信号用の多層配線
12を形成した構造となっている。図中、13はフィン
、14はAffiNキャップ、15は接着剤層、16は
プリント基板である。ポリイミドは低誘電率を有するた
めに高速素子実装において遅延時間を短くすることに有
効であるとされている。
1990, 1) 217). This package has a structure in which a multilayer polyimide insulating layer and a multilayer signal wiring 12 are formed by a thin film process on the surface of an AlN ceramic substrate 10 in which W conductors 3 and 11 as power wiring are formed by a co-firing method. There is. In the figure, 13 is a fin, 14 is an AffiN cap, 15 is an adhesive layer, and 16 is a printed circuit board. Since polyimide has a low dielectric constant, it is said to be effective in shortening delay time in high-speed device packaging.

しかしながら、このようなポリイミドと薄膜プロセスを
使用した多層構造では、ポリイミド材料や設備費が高く
、生産のための時間が長くかがるなど(よるコストおよ
び生産性の問題があり、工業上の多くの問題を残すもの
であった。
However, such multilayer structures using polyimide and thin film processes have cost and productivity problems such as high polyimide material and equipment costs and long production times. The problem remained.

[発明が解決しようとする課題] 従来の一般的アルミナパッケージでは、誘電率が9〜1
0とガラスセラミックスやポリイミド材料の値より2〜
3倍大きいため高速化に対して不十分であり、またCu
導体を内部に形成することが不可能であった。一方、ガ
ラスセラミックスと銅導体の多層配線基板ではガラスセ
ラミックス材料の熱伝導率が従来のアルミナより一桁程
度小さいため放熱性に問題があった。さらにAINはア
ルミナの5〜10倍の高熱伝導性を有するが誘電率はア
ルミナ程度の値であり、高速化に有効ではない。
[Problems to be solved by the invention] Conventional general alumina packages have a dielectric constant of 9 to 1.
0 and 2 to 2 from the values of glass ceramics and polyimide materials.
Since it is three times larger, it is insufficient for speeding up, and Cu
It was not possible to form conductors inside. On the other hand, multilayer wiring boards made of glass ceramics and copper conductors have problems with heat dissipation because the thermal conductivity of the glass ceramic material is about an order of magnitude lower than that of conventional alumina. Furthermore, although AIN has thermal conductivity 5 to 10 times higher than that of alumina, its dielectric constant is about the same as that of alumina, so it is not effective for increasing speed.

そこで放熱性に優れるA!N基板と優れた電気的特性を
有する銅導体を組み合わせたうえ、さらに高速化の特徴
を発揮するための構造を本発明者は鋭意検討した結果、
本発明の複合構造セラミックパッケージを発明するに至
った。
Therefore, A with excellent heat dissipation! In addition to combining an N substrate and a copper conductor with excellent electrical properties, the inventors have diligently studied a structure that will further exhibit the characteristics of increased speed.
The composite structure ceramic package of the present invention has been invented.

[課題を解決するための手段] 本発明は、窒化アルミニウム基板上に銅導体と低誘電率
のガラスセラミックス層からなる多層構造を装備した複
合構造を有してなることを特徴とする半導体素子用セラ
ミックパッケージである。
[Means for Solving the Problems] The present invention provides a semiconductor device having a composite structure equipped with a multilayer structure consisting of a copper conductor and a low dielectric constant glass ceramic layer on an aluminum nitride substrate. It is a ceramic package.

ここで、ガラスセラミックスの誘電率は窒化アルミニウ
ムの値より小さいことが望ましい。
Here, it is desirable that the dielectric constant of the glass ceramic is smaller than that of aluminum nitride.

以下、本発明をさらに詳しく説明する。The present invention will be explained in more detail below.

第1図は本発明の半導体素子用パッケージの一例の断面
構造を示したものである。高熱伝導性AβN基板10の
片面上に低誘電率を有するガラスセラミックス層17が
形成され、ざらにこの上に銅導体配線部18が形成され
ている。AぶN基板は焼結助剤に関連したアルカリ土類
金属(Ca、Ba。
FIG. 1 shows a cross-sectional structure of an example of a package for a semiconductor device according to the present invention. A glass ceramic layer 17 having a low dielectric constant is formed on one side of a highly thermally conductive AβN substrate 10, and a copper conductor wiring portion 18 is formed roughly thereon. The AbuN substrate contains alkaline earth metals (Ca, Ba, etc.) associated with sintering aids.

Sr等)や希土類金属(Y、La、Gd等)の化合物を
不純物として含有してもよい。
It may contain compounds of Sr, etc.) or rare earth metals (Y, La, Gd, etc.) as impurities.

低誘電率のガラスセラミックス層の材料としては、室温
での誘電率が窒化アルミニウムの値以下の材料であり、
−船釣に公知の組成物が利用可能である。例えば、具体
的にはホウケイ酸ガラスとアルミナの複合材料、ホウケ
イ酸ガラスとシリヵの複合材料、ホウケイ酸ガラスとコ
ージェライトの複合材料、ZnO−MgO−N1203
−5i02系コージエライト材料、その他ホウケイ酸ガ
ラス、シリカ、コージェライト、ムライト、ホルステラ
イト等から選ばれた単独または複合組成物の材料で、周
波数1  MHzでの値が3.5〜8のものが有効であ
る。
The material for the low dielectric constant glass ceramic layer is a material whose dielectric constant at room temperature is less than the value of aluminum nitride.
- Compositions known for boat fishing are available. For example, specifically, a composite material of borosilicate glass and alumina, a composite material of borosilicate glass and silica, a composite material of borosilicate glass and cordierite, ZnO-MgO-N1203
-5i02 cordierite materials, other single or composite materials selected from borosilicate glass, silica, cordierite, mullite, holsterite, etc., with a value of 3.5 to 8 at a frequency of 1 MHz are effective. It is.

低誘電率のガラスセラミックス層のAlN基板上への形
成プロセスとしては、印刷またはテープ積層後に800
〜1000 ’Cで熱処理する同相法以外に、気相法で
あるスパッタ法や蒸着法、および液相法であるゾルゲル
法などの手法も適応できる。
The process for forming a low dielectric constant glass ceramic layer on an AlN substrate is as follows:
In addition to the in-phase method of heat treatment at ~1000'C, methods such as the sputtering method and vapor deposition method, which are gas phase methods, and the sol-gel method, which is a liquid phase method, can also be applied.

導体としての銅配線は銅ペーストを印刷した後に熱処理
した厚膜印刷法、物理的手段である蒸着法ヤスバッタ法
、化学的手法である無電界メツキ法などのプロセスで形
成したものが利用可能である。
Copper wiring as a conductor can be formed by processes such as thick-film printing, which involves printing copper paste and then heat-treating it, physical methods such as vapor deposition and Yasbatta method, and chemical methods such as electroless plating. .

[作用] 本発明においては、半導体素子から発生した熱は、高熱
伝導性のA!N基板により放散される。
[Function] In the present invention, the heat generated from the semiconductor element is transferred to A!, which has high thermal conductivity. Dissipated by the N substrate.

ざらにAf!N基板上の低誘電率ガラスセラミックスに
接した銅導体により伝搬遅延時間および超高周波での信
号の伝搬損失の低減が可能になる。このため、本発明の
半導体素子用セラミックパッケージは、熱的および電気
的に優れ、高速LSI素子の実装に適したものである。
Zarani Af! The copper conductor in contact with the low-permittivity glass-ceramic on the N-substrate makes it possible to reduce propagation delay time and signal propagation loss at very high frequencies. Therefore, the ceramic package for semiconductor devices of the present invention is excellent thermally and electrically and is suitable for mounting high-speed LSI devices.

[実施例] 次に第1図から第4図を参照して本発明の実施例につい
て説明する。
[Example] Next, an example of the present invention will be described with reference to FIGS. 1 to 4.

第1図は本発明の一実施例を示す断面図で、A!N基板
10上の片面の一部に低誘電率のガラスセラミックス層
17が形成されていて、銅導体18がこのガラスセラミ
ックス層上および半導体素子の搭載部のAlN基板上に
形成されている。半導体素子8はパッケージに搭載後、
ワイヤボンディング9によって接続されている。
FIG. 1 is a sectional view showing an embodiment of the present invention, and A! A glass ceramic layer 17 with a low dielectric constant is formed on a part of one side of the N substrate 10, and a copper conductor 18 is formed on the glass ceramic layer and on the AlN substrate on the mounting portion of the semiconductor element. After the semiconductor element 8 is mounted on the package,
They are connected by wire bonding 9.

本実施例では低誘電率を有するガラスセラミックス層上
に銅配線が形成されているために、第5図に示すような
、誘電率10のアルミナ基板上にニッケルおよび金メツ
キされたW導体の配線が形成されている従来のパッケー
ジより遅延時間を低減することに有効である。たとえば
ガラスセラミックス材料として誘電率5.0の]−ジェ
ライト系ガラスセラミックスからなる20 JUの層を
厚さ10庫の銅導体とAIN基板の間に設けることによ
り、アルミナに比ベパッケージ内部での約20%遅延時
間の短縮となり、高速LSI素子の実装に有効である。
In this example, since the copper wiring is formed on a glass ceramic layer having a low dielectric constant, the wiring is made of a W conductor plated with nickel and gold on an alumina substrate with a dielectric constant of 10, as shown in FIG. This is effective in reducing delay time compared to conventional packages in which For example, by providing a 20 JU layer of [-gelite glass ceramics] with a dielectric constant of 5.0 as a glass ceramic material between a 10-thick copper conductor and an AIN substrate, it is possible to reduce This results in a 20% reduction in delay time, which is effective for mounting high-speed LSI devices.

またWやニッケルより低電気抵抗の銅導体を使用してい
ることにより、高周波領域でのデジタル信号の伝送損失
が少ない特徴も有する。さらにLSI素子の搭載部を銅
導体で形成することにより、従来のW層とNi層より熱
伝導率が優れることにより、高熱伝導性AIN基板への
LSI素子からの熱を効率よく伝え、放熱性においても
効果がある。一方、本発明の銅導体形成プロセスにおい
ては、従来技術のような同時焼成過程でのセラミックス
表面内でのW導体の収縮がないため、導体の位置や寸法
を高精度に形成できるため、導体のファインピッチ化や
高密度化に対しても効果がある。
Furthermore, by using a copper conductor that has a lower electrical resistance than W or nickel, it also has the characteristic of less transmission loss of digital signals in the high frequency range. Furthermore, by forming the mounting part of the LSI element with a copper conductor, the thermal conductivity is superior to that of the conventional W layer and Ni layer, so the heat from the LSI element is efficiently transferred to the highly thermally conductive AIN board, and heat dissipation is improved. It is also effective in On the other hand, in the copper conductor forming process of the present invention, there is no shrinkage of the W conductor within the ceramic surface during the simultaneous firing process as in the conventional technology, so the position and dimensions of the conductor can be formed with high precision. It is also effective for fine pitch and high density.

第1図では、銅導体はAj!N基板上のガラスセラミッ
クス層の上に形成されているが、Aj!N基板上に直接
銅導体を形成し、この上にガラスセラミックス層を形成
することも可能である。さらに第1図では低誘電率ガラ
スセラミックス層はAlN基板上のみであるが、第2図
のように、低誘電率ガラスセラミックス層と銅導体を交
互に積層した多層構造を形成することも可能である。
In Figure 1, the copper conductor is Aj! Although it is formed on the glass ceramic layer on the N substrate, Aj! It is also possible to form a copper conductor directly on the N substrate and form a glass ceramic layer thereon. Furthermore, in Figure 1, the low dielectric constant glass ceramic layer is only on the AlN substrate, but as shown in Figure 2, it is also possible to form a multilayer structure in which low dielectric constant glass ceramic layers and copper conductors are alternately laminated. be.

第2図の場合は、Al1N基板上の多層配線銅導体は、
同時焼成法でAj! N基板内部に形成されたW内部導
体3により素子搭載面の反対側の外部出力用の金属ピン
4に接続されている。金属ピン4の接合方法としては、
AgCuやAuSn系のろう材6によりNiメツキ5し
たW外部導体部に形成する技術が利用できる。
In the case of Figure 2, the multilayer wiring copper conductor on the Al1N substrate is
Aj with simultaneous firing method! It is connected to a metal pin 4 for external output on the opposite side of the element mounting surface by a W internal conductor 3 formed inside the N substrate. The method for joining the metal pin 4 is as follows:
A technique can be used to form the W outer conductor portion plated with Ni using a brazing filler metal 6 made of AgCu or AuSn.

また外部出力用の金属ピンは、第3図のように素子搭載
面側に垂直に形成することも可能である。
Moreover, the metal pin for external output can also be formed perpendicularly to the element mounting surface side as shown in FIG.

この場合、AIN基板内部にはW内部導体を形成する必
要はない。ざらに外部出力ビンとしては、AlN基板上
に垂直に立った構造ではなく、第4図に示すように、基
板の水平方向に形成したリド19も利用可能である。
In this case, there is no need to form a W internal conductor inside the AIN substrate. As an external output bin, it is also possible to use a lid 19 formed in the horizontal direction of the substrate, as shown in FIG. 4, instead of vertically standing on the AlN substrate.

[発明の効果] 以上説明したように、本発明の半導体素子用セラミック
パッケージでは次に述べるような優れた効果を得ること
ができる。
[Effects of the Invention] As explained above, the ceramic package for semiconductor elements of the present invention can provide the following excellent effects.

■半導体素子を高熱伝導性のAIN基板上に搭載できる
ことにより、熱放散性を良くし、半導体素子の低熱抵抗
化に効果的である。特に半導体素子の搭載部の金属とし
て銅導体を形成した場合、従来のW導体およびNiとA
uメツキの組み合わせの場合よりさらに有効である。
■By being able to mount a semiconductor element on a highly thermally conductive AIN substrate, it improves heat dissipation and is effective in lowering the thermal resistance of the semiconductor element. In particular, when a copper conductor is formed as the metal for the mounting part of a semiconductor element, conventional W conductors and Ni and A
This is even more effective than the combination of u plating.

■導体配線が低誘電率を有するガラスセラミックス層と
接して形成されていることより、伝搬遅延時間の低減に
有効であり、高速LSIの実装に適している。
(2) Since the conductor wiring is formed in contact with a glass ceramic layer having a low dielectric constant, it is effective in reducing propagation delay time and is suitable for mounting high-speed LSIs.

■導体として電気抵抗の小さい銅を使用することにより
、配線抵抗を小さくしたり、超高周波帯での信号の伝搬
損失が少なくなる。これ以外に、銅導体は半田耐熱性に
優れ良好な半田濡れ性を示し、さらにはエレクトロマイ
グレーションが起こりにくい等の多くの長所を有する。
■Using copper, which has low electrical resistance, as a conductor reduces wiring resistance and signal propagation loss in ultra-high frequency bands. In addition to this, copper conductors have many other advantages such as excellent solder heat resistance, good solder wettability, and resistance to electromigration.

■従来技術のように同時焼成過程でのセラミックス基板
表面での導体の収縮が起きないため、導体の位置や寸法
を高精度に形成でき、ファインピッチ化や高密度化にも
効果的である。
■Since the conductor does not shrink on the surface of the ceramic substrate during the co-firing process unlike the conventional technology, the position and dimensions of the conductor can be formed with high precision, and it is also effective in achieving fine pitch and high density.

【図面の簡単な説明】[Brief explanation of the drawing]

第1〜4図は、それぞれ本発明の一実施例の要部断面図
、第5図は従来の半導体素子用セラミックパッケージの
一例の断面図、第6図はその拡大断面図、第7図は従来
の半導体素子用セラミックパッケージの別の一例の断面
図、第8図はその部分断面図である。 1・・・アルミナセラミックス基板 2・・・W外部導体    3・・・W内部導体4・・
・金属ピン     5・・・ニッケルメッキ6・・・
AgCuろう材  7・・・金メツキ8・・・半導体素
子 9・・・ワイヤボンディング 10・・・AINセラミックス基板 11・・・電源導体層 12・・・ポリイミド薄膜多層配線 13・・・フィン      14・・・AlNキャッ
プ15・・・接着剤層     16・・・プリント基
板17・・・ガラスセラミックス層
1 to 4 are sectional views of essential parts of an embodiment of the present invention, FIG. 5 is a sectional view of an example of a conventional ceramic package for semiconductor elements, FIG. 6 is an enlarged sectional view thereof, and FIG. FIG. 8 is a cross-sectional view of another example of a conventional ceramic package for semiconductor devices, and FIG. 8 is a partial cross-sectional view thereof. 1... Alumina ceramics substrate 2... W outer conductor 3... W inner conductor 4...
・Metal pin 5...Nickel plating 6...
AgCu brazing material 7... Gold plating 8... Semiconductor element 9... Wire bonding 10... AIN ceramics substrate 11... Power supply conductor layer 12... Polyimide thin film multilayer wiring 13... Fin 14. ... AlN cap 15 ... adhesive layer 16 ... printed circuit board 17 ... glass ceramic layer

Claims (2)

【特許請求の範囲】[Claims] (1)窒化アルミニウム基板上に銅導体と低誘電率のガ
ラスセラミックス層からなる多層構造を装備した複合構
造を有してなることを特徴とする半導体素子用セラミッ
クパッケージ。
(1) A ceramic package for a semiconductor device characterized by having a composite structure equipped with a multilayer structure consisting of a copper conductor and a low dielectric constant glass ceramic layer on an aluminum nitride substrate.
(2)ガラスセラミックスの誘電率は窒化アルミニウム
の値より小さい請求項1記載の半導体素子用セラミック
パッケージ。
(2) The ceramic package for a semiconductor device according to claim 1, wherein the dielectric constant of the glass ceramic is smaller than that of aluminum nitride.
JP2249967A 1990-09-21 1990-09-21 Ceramic package for semiconductor element Pending JPH04130757A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2249967A JPH04130757A (en) 1990-09-21 1990-09-21 Ceramic package for semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2249967A JPH04130757A (en) 1990-09-21 1990-09-21 Ceramic package for semiconductor element

Publications (1)

Publication Number Publication Date
JPH04130757A true JPH04130757A (en) 1992-05-01

Family

ID=17200857

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2249967A Pending JPH04130757A (en) 1990-09-21 1990-09-21 Ceramic package for semiconductor element

Country Status (1)

Country Link
JP (1) JPH04130757A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06120400A (en) * 1992-10-06 1994-04-28 Kyocera Corp Semiconductor-device storing package
WO2018181523A1 (en) * 2017-03-29 2018-10-04 株式会社村田製作所 Composite ceramic multilayer substrate, heat-generating element mounting module, and method for manufacturing composite ceramic multilayer substrate

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02231746A (en) * 1989-03-06 1990-09-13 Fujitsu Ltd Manufacture of ceramic circuit board
JPH02238642A (en) * 1989-03-10 1990-09-20 Fujitsu Ltd Manufacture of ceramic circuit board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02231746A (en) * 1989-03-06 1990-09-13 Fujitsu Ltd Manufacture of ceramic circuit board
JPH02238642A (en) * 1989-03-10 1990-09-20 Fujitsu Ltd Manufacture of ceramic circuit board

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06120400A (en) * 1992-10-06 1994-04-28 Kyocera Corp Semiconductor-device storing package
WO2018181523A1 (en) * 2017-03-29 2018-10-04 株式会社村田製作所 Composite ceramic multilayer substrate, heat-generating element mounting module, and method for manufacturing composite ceramic multilayer substrate
JPWO2018181523A1 (en) * 2017-03-29 2019-11-07 株式会社村田製作所 Composite ceramic multilayer substrate, heating element mounting module, and method of manufacturing composite ceramic multilayer substrate
CN110462826A (en) * 2017-03-29 2019-11-15 株式会社村田制作所 The manufacturing method of power module and power module
CN110520986A (en) * 2017-03-29 2019-11-29 株式会社村田制作所 The manufacturing method of composite ceramics multilager base plate, heater element installation module and composite ceramics multilager base plate
US11107741B2 (en) 2017-03-29 2021-08-31 Murata Manufacturing Co., Ltd. Composite ceramic multilayer substrate, heat generating element-mounting module, and method of producing composite ceramic multilayer substrate
US11114355B2 (en) 2017-03-29 2021-09-07 Murata Manufacturing Co., Ltd. Power module and method for manufacturing power module
CN110520986B (en) * 2017-03-29 2023-03-24 株式会社村田制作所 Composite ceramic multilayer substrate, heating element mounting module, and method for manufacturing composite ceramic multilayer substrate
CN110462826B (en) * 2017-03-29 2023-09-19 株式会社村田制作所 Power module and method for manufacturing power module

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