JPS60154596A - Multilayer circuit board - Google Patents
Multilayer circuit boardInfo
- Publication number
- JPS60154596A JPS60154596A JP1074784A JP1074784A JPS60154596A JP S60154596 A JPS60154596 A JP S60154596A JP 1074784 A JP1074784 A JP 1074784A JP 1074784 A JP1074784 A JP 1074784A JP S60154596 A JPS60154596 A JP S60154596A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- wiring board
- gold
- chromium
- multilayer wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4664—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
本発明は、コンビ瓢−夕などに用いられるＬ８工実装用
多層配線基板の構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to the structure of a multilayer wiring board for L8 assembly used in combination gourds and the like.
従来、Ｌ８Ｉ実装用多層配線基板は、外部との接続には
配線基板の配線表面に専用のパッドを必要とし、また絶
縁体はアルミナあるいは酸化蒜素などの無機絶縁体で形
成されたものであり、このよう力構・成・上バイアフィ
ル材料に社高温焼成用の厚膜導体ペーストが用いられて
いた。Conventionally, multilayer wiring boards for L8I mounting require dedicated pads on the wiring surface of the wiring board for external connections, and the insulators are made of inorganic insulators such as alumina or arsenic oxide. In this way, a thick film conductor paste for high-temperature firing was used as the upper via fill material.
一方、ＬＳＩの高集積化に伴い接続ビン数は増加する傾
向が強く、配線表面に専用パッドを設ける従来の方法で
は、面積的にも限度を生じ、また無機絶縁体あるいはバ
イアフィル用厚膜導体ペーストの焼結には９００℃以上
の高温処理が必要となるため耐熱性の問題を生じ、さら
忙無機絶縁体特有の表面粗さや比誘電率が大きいなど微
細化および信頼性に多くの問題があった。On the other hand, there is a strong tendency for the number of connection bins to increase as LSIs become more highly integrated, and the conventional method of providing dedicated pads on the wiring surface has a limit in terms of area. Sintering requires high-temperature treatment of 900°C or higher, which causes problems with heat resistance, and there are also many problems with miniaturization and reliability, such as the surface roughness and high dielectric constant characteristic of inorganic insulators. Ta.
本発明は、外部接続に基板裏面のビンおよびポリイミド
絶縁体などを採用することＫより、高集積化をすること
ができ、さらに高信頼性および高品質を有する多層配線
基板を提供することを目的とする。An object of the present invention is to provide a multilayer wiring board that can achieve high integration by employing vias on the back side of the board, polyimide insulators, etc. for external connections, and has high reliability and high quality. shall be.
本発明は、裏面に設けられた複数９個の接続ビンと、こ
の複数個の接続ビンと各々接続する内部スルーホールと
、抵抗の小さい広い面積をもつ共通型、位階とを有する
グリーンシート積層基板と、このグリーンシート積層基
板表面に配設された多層金属から成る導体層と、この導
体層の表面のあらかじめ定められた部分に複数個のバイ
アホールを有するポリイミド樹脂製の絶縁層と、上記バ
イアホールに埋設されたバイアフィルとにより構成され
た配線基板層が１層もしくは繰返し多層化され、この配
線基板層の最上面に多種金属から成る最上導体層を備え
た構造により構成され、高集積化することができ、その
信頼性および品質を高めることができることを特徴とす
る。The present invention provides a green sheet laminated board having a plurality of nine connection bins provided on the back surface, internal through holes each connecting to the plurality of connection bins, and a common type having a large area with low resistance. , a conductive layer made of multilayer metal arranged on the surface of this green sheet laminated substrate, an insulating layer made of polyimide resin having a plurality of via holes in predetermined parts of the surface of this conductive layer, and the above-mentioned vias. The wiring board layer is made up of a single layer or multiple layers made up of via fills embedded in holes, and the top conductor layer made of various metals is provided on the top surface of this wiring board layer, resulting in high integration. It is characterized by being able to improve its reliability and quality.
導体層はクロム−パラジウム−金の５層金属を、バイア
フィルは金−ポリイミド材料を、最上導体層はクロム−
パラジウム−銅−ニツケルー金あるいはクロム−パラジ
ウム−銅を用いる仁とができる。The conductor layer is made of 5-layer metal of chromium-palladium-gold, the via fill is made of gold-polyimide material, and the top conductor layer is made of chromium-palladium-gold.
It is possible to use palladium-copper-nickel gold or chromium-palladium-copper.
次に本発明実施例を図面に基づいて説明する。 Next, embodiments of the present invention will be described based on the drawings.
図は本発明実施例多層配線基板の構成を示す断 、：面
図で、導体３層の場会を示したものである。本発明多層
配線基板は、裏面に複数個の接続ビン１２をもち、内部
にこの複数個の接続ビン１２と各々接続されるスルーホ
ール２０３および導体抵抗の少い広い面積のアース層あ
るいは１源層１０４を有するクリーンシート積層基板１
１．、）にクロム（Ｏｒ）−パラジウム（ｐａ ）−金
（Ａｕ ）の３贋金Ｍ６から成る第１導体層１０１が配
設されている。The figure is a cross-sectional view showing the structure of a multilayer wiring board according to an embodiment of the present invention, and shows the case where three conductor layers are used. The multilayer wiring board of the present invention has a plurality of connection vials 12 on the back surface, through-holes 203 connected to the plurality of interconnection vials 12 inside, and a wide-area ground layer or source layer with low conductor resistance. Clean sheet laminated substrate 1 having 104
1. , ) is provided with a first conductor layer 101 made of three counterfeit metals M6 of chromium (Or)-palladium (pa)-gold (Au).
この第１導体層のあらかじめ定められた部分に複数個の
バイアホールを有するポリイミド樹脂製の＠１ポリイミ
ド絶縁層３０１が積層され、上記バイアホールには、金
（Ａｕ）−ポリイミド材料から成るバイアフィル２０１
が埋設されている。A @1 polyimide insulating layer 301 made of polyimide resin and having a plurality of via holes is laminated on a predetermined portion of the first conductor layer, and a via fill 201 made of gold (Au)-polyimide material is laminated in the via hole.
is buried.
以上を一つの層として、さらに上記第１ポリイミド絶縁
層３０１の上面には上記第１導体層１０１と同じ材質の
第２導体層１０２が配設され、この第２導体層１０２の
あらかじめ定められた部分に複数個のバイア一−ルを有
するボ・ｊイミド樹脂製の第２ポリイミド絶縁層３０２
が積層され、その上の所定の位＃に複数個の最上導体層
１０３が配設された構造罠なっている。In addition to the above as one layer, a second conductor layer 102 made of the same material as the first conductor layer 101 is provided on the upper surface of the first polyimide insulating layer 301. A second polyimide insulating layer 302 made of polyimide resin and having a plurality of via holes in a portion thereof.
are stacked, and a plurality of uppermost conductor layers 103 are disposed at predetermined positions thereon.
以上Ｆｉｓ層の例を示したものであるが、その層の数ｋ
ｉ必ず６本この実施例に限宇され６本のではない。The example of the Fis layer is shown above, and the number of layers k
i There are definitely 6 pieces, not 6 pieces, which is limited to this embodiment.
上記グリーンシート積層基板１１は、その主成分が酸化
アルミ（ＡＬ２０． ）、酸化珪素（Ｓ１０２）などで
あり、厚さ社１箇〜５ｖｍである。ＧＮＤ層あるいは電
源層１０４は導体抵抗が少く、かつ広い面積をもつ材料
嘉使用され、スルーホール２０３けモリブデン（Ｍｏ）
などで形成されている。The green sheet laminated substrate 11 has aluminum oxide (AL20.), silicon oxide (S102), etc. as its main components, and has a thickness of 1 to 5 μm. The GND layer or power supply layer 104 is made of a material with low conductor resistance and a large area, and the through hole 203 is made of molybdenum (Mo).
It is formed by etc.
また接続ビン１２はモリブデン（ＭＯ）材にニッケル（
Ｎ１）メッキ、金（Ａｕ）メッキが施され、裏面全域に
わたって接続ビンの実装が可能となるために高密度に接
続ビンを配置す石ことができ、５０〜５０ビン／ｃ１１
１のビン配列が可能である。The connection bottle 12 is made of molybdenum (MO) and nickel (
N1) Plating, gold (Au) plating is applied, making it possible to mount connection bins over the entire back surface, making it possible to arrange connection bins at high density, 50 to 50 bins/c11
1 bin arrangement is possible.
第１および第２導体層１０１ 、１０２はクロム（Ｏｒ
）−パラジウム（Ｐｄ）−金（ＡＬＬ）の３層構造でそ
の厚さは５００Ａ〜５ｏｏｏｏ Ｘである。また最上導
体層１０３は主としてＬＳＩチップボンデングパッドな
どに用いられるため、クロム（Ｏｒ）−パラジウム（ｐ
ａ） −銅（Ｏｕ）、の構成としｓｕ／Ｐｂ系はんだ性
用パッドとして、あるいはクロム（（３ｒ ）−パラジ
ウム（、ｐａ） −’銅（Ｏｕ）−ニッケル（Ｎ１）−
金（ムＵ）などを有する構成としＡｕ−Ａｕ Ｔｏボン
デンダ用パッドとしてその目的によって使いわけるメタ
ル構成になっている。The first and second conductor layers 101 and 102 are made of chromium (Or
)-palladium (Pd)-gold (ALL) three-layer structure with a thickness of 500A to 5ooooX. Furthermore, since the uppermost conductor layer 103 is mainly used for LSI chip bonding pads, chromium (Or)-palladium (p
a) - Copper (Ou), as a su/Pb solder pad, or chromium ((3r) - palladium (, pa) - 'copper (Ou) - nickel (N1) -
It has a metal structure including gold (muU), etc., and can be used as an Au-Au To bonder pad depending on the purpose.
第１および＠２ポリイミド絶縁層３０１ 、３０２は導
体層間の絶縁の機能を有し、その材料はポリイミド樹脂
が用いられ、これは低温プロセスで形成することができ
、また表面粗さが非常に小さく、低誘電率でかつ高抵抗
の絶縁膜を形成することができる。The first and @2 polyimide insulating layers 301 and 302 have the function of insulating between the conductor layers, and their material is polyimide resin, which can be formed by a low-temperature process and has a very small surface roughness. , it is possible to form an insulating film with a low dielectric constant and high resistance.
またスルーホール２０３はフォトリングラフィ技術が使
われるために孔径の微細化がはかれ、このスルーホール
２０３には金（Ａｕ）−ポリイミド材のバイアフィル２
０１ 、２０２が埋められている。Furthermore, the through hole 203 uses photolithography technology, so the diameter of the hole is made finer.
01 and 202 are filled in.
配線基板の多層化を行うプロセスにおいては、各層のス
テップカバリッジを保証するために、このバイアフィル
２０１ 、２０２が必要であり、スルーホー ル２０３
の導体抵抗、バイアフィルの形状および密着性などは金
（Ａｕ）粒子とポリイミド樹脂の混会の割合によってコ
ントロールすることができる。In the process of multilayering a wiring board, the via fills 201 and 202 are necessary to ensure step coverage of each layer, and the through holes 203
The conductor resistance, shape and adhesion of the viafill, etc. can be controlled by the mixing ratio of gold (Au) particles and polyimide resin.
本発明は単位面積当りのビンの配列が高密度にでき、絶
縁性、導電性の高い材料を用いることによって多層化を
可能にしたもので、多ぐの配線を小さな一つの基板でで
きるところに特徴がある。The present invention allows for high-density arrangement of bins per unit area and enables multi-layering by using materials with high insulating and conductive properties. It has characteristics.
以上説明したように本発明によれば、多層配線基板の構
成を変え、外部接続に基板裏面のピンおよびポリイミド
絶縁体などを採用することＫよって、従来の構成では不
可能であった高集積化かでき、さらに＠頼性および品質
をより高めることができるなどの優れた効果がある。As explained above, according to the present invention, the structure of the multilayer wiring board is changed and pins on the back surface of the board and polyimide insulators are used for external connections, thereby achieving high integration, which was impossible with the conventional structure. It also has excellent effects such as being able to improve reliability and quality.
図は本発明実施例多層配線基板の構成を示す断面図。
１１・・・グリーンシート積層基板、 １２・・・接続
ビン、１０１・・・第１導体層、１０２・・・第２導体
層、１０３・・・最上導体層、１０４・・・ＧＮＤ層／
層温電源層０１ 、２０２・・・ １バイアフイル、２
０３・・・スルーホール、３０１・・・第１ポリイミド
絶縁層、３０２・・・第２ポリイミド絶縁層。The figure is a sectional view showing the structure of a multilayer wiring board according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 11... Green sheet laminated board, 12... Connection bin, 101... First conductor layer, 102... Second conductor layer, 103... Top conductor layer, 104... GND layer/
Layer temperature power layer 01, 202... 1 via file, 2
03... Through hole, 301... First polyimide insulating layer, 302... Second polyimide insulating layer.
Claims (1)
個の接続ピンと各々接続する内部スルーホールと、抵抗
の小さい広い面積をもつ共通電位層とを有するクリーン
シート積層基板と、 仁のグリーンシート積層基板表面に配設された多層金属
から成る導体層と、 仁の導体層の表面のあらかじめ定められた部分に複数個
のバイアホールを有するポリイミド樹脂製の絶縁層と、 上記バイアホールに埋設されたバイアフィルトにより構
成された配線基板層が１層もしくは繰返し多層化され、 この配線基板層の最上面に多種金属から成る最、上導２
体層を備えた構造を特徴とする多層配線基板。 （２）上記導体層はクロム−パラジウム−金の３層金属
である特許請求の範囲第（１）項に記載の多層配線基板
。 （３） 上記バイアフィルは金−ポリイミド材料から成
る特許請求の範囲第（１）項に記載の多層配線基板。 （４） 上記最上導体層はクロム−パラジウム−銅−ニ
ッケルー金−あるいはクロムーバ２ジウムー銅から成る
特許請求の範囲第（１）項に記載の多層配線基板。[Claims] (Li) A clean sheet laminate having a plurality of connection pins provided on the back surface, internal through holes each connected to the plurality of connection pins, and a common potential layer having a large area with low resistance. A conductor layer made of a multilayer metal arranged on the surface of the Jin's green sheet laminated board; an insulating layer made of polyimide resin having a plurality of via holes in predetermined portions of the surface of the Jin's conductor layer; , A wiring board layer composed of via filtration buried in the via hole is formed into one layer or is repeatedly multilayered, and an uppermost conductive layer made of various metals is formed on the top surface of this wiring board layer.
A multilayer wiring board characterized by a structure with body layers. (2) The multilayer wiring board according to claim (1), wherein the conductor layer is a three-layer metal of chromium-palladium-gold. (3) The multilayer wiring board according to claim (1), wherein the via fill is made of a gold-polyimide material. (4) The multilayer wiring board according to claim (1), wherein the uppermost conductor layer is made of chromium-palladium-copper-nickel-gold or chromium didium-copper.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1074784A JPS60154596A (en) | 1984-01-23 | 1984-01-23 | Multilayer circuit board |
| FR8500926A FR2558643B1 (en) | 1984-01-23 | 1985-01-23 | MULTI-LAYER WIRING SUBSTRATE |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1074784A JPS60154596A (en) | 1984-01-23 | 1984-01-23 | Multilayer circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60154596A true JPS60154596A (en) | 1985-08-14 |
Family
ID=11758897
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1074784A Pending JPS60154596A (en) | 1984-01-23 | 1984-01-23 | Multilayer circuit board |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS60154596A (en) |
| FR (1) | FR2558643B1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5127986A (en) * | 1989-12-01 | 1992-07-07 | Cray Research, Inc. | High power, high density interconnect method and apparatus for integrated circuits |
| US5185502A (en) * | 1989-12-01 | 1993-02-09 | Cray Research, Inc. | High power, high density interconnect apparatus for integrated circuits |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3029382A1 (en) * | 1980-08-01 | 1982-03-04 | Siemens AG, 1000 Berlin und 8000 München | Conductor pattern for semiconductor device on insulating substrate - where multilayer pattern includes palladium covered by palladium oxide and then gold |
| JPS57126154A (en) * | 1981-01-30 | 1982-08-05 | Nec Corp | Lsi package |
-
1984
- 1984-01-23 JP JP1074784A patent/JPS60154596A/en active Pending
-
1985
- 1985-01-23 FR FR8500926A patent/FR2558643B1/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| FR2558643A1 (en) | 1985-07-26 |
| FR2558643B1 (en) | 1987-11-13 |
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