JPS5864094A - Multilayer circuit board with connecting pins - Google Patents

Multilayer circuit board with connecting pins

Info

Publication number
JPS5864094A
JPS5864094A JP16273881A JP16273881A JPS5864094A JP S5864094 A JPS5864094 A JP S5864094A JP 16273881 A JP16273881 A JP 16273881A JP 16273881 A JP16273881 A JP 16273881A JP S5864094 A JPS5864094 A JP S5864094A
Authority
JP
Japan
Prior art keywords
wiring board
multilayer wiring
multilayer
board
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16273881A
Other languages
Japanese (ja)
Other versions
JPH0210597B2 (en
Inventor
幸雄 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP16273881A priority Critical patent/JPS5864094A/en
Publication of JPS5864094A publication Critical patent/JPS5864094A/en
Publication of JPH0210597B2 publication Critical patent/JPH0210597B2/ja
Granted legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は、多層配線基板に外部接続用ピンが取付けられ
た接続用ピン付多層配線基板に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multilayer wiring board with connection pins, in which external connection pins are attached to the multilayer wiring board.

集積回路技術の進歩によって、基板上への素子の搭載は
2個別トランジスタの搭載から半7導体集積回路の搭載
そして、複数個のLSIの搭載へと向かって来た。それ
に伴い、混成集積回路においては、同一基板上に高密度
に回路を構成する必要に迫られ、一枚の基板上に実装で
きる回路密度は限定されているので、より実装密度を向
上させるために、内部配線の多層化さ・れた多層配線基
板が使用されている。
With the advancement of integrated circuit technology, the mounting of elements on a substrate has progressed from mounting two individual transistors to mounting seven semiconductor integrated circuits and then mounting multiple LSIs. Accordingly, in hybrid integrated circuits, it is necessary to configure circuits at high density on the same board, and since the circuit density that can be mounted on a single board is limited, it is necessary to further improve the mounting density. , multilayer wiring boards with multilayered internal wiring are used.

従来、厚膜混成集積回路用多層配線基板として。Conventionally, used as a multilayer wiring board for thick film hybrid integrated circuits.

絶縁性、熱放散性2機械的強度に優れた多層セラミ、り
基板が用いられている。
A multilayer ceramic substrate with excellent insulation, heat dissipation properties, and mechanical strength is used.

第1図は、この種の多層配線基板に外部接続用ピンが取
付けられた。接続用ピン付多層配線基板の従来例の構成
を示した正面断面図である。図において、1は第1の多
層配線基板で、多層セラミゝ、り板11と、 MoやW
などからなる第1の導電体12から構成さ′れ、2は接
続用ピンである。図に示されるように、第1の導電体1
2は、複数のセラミック材が積層された多層セラミ、り
板11の内部及び表面に配線されている。この・ような
構造の接続用ピン付多層配線基板は、セラミック材が焼
結前の状態、いわゆるグリーンシートの状態のときに、
そのグリーンシート上にMOやWなどの導体イーストで
配線をスクリーン印刷し、このようにして配線された複
数のセラミ、り材を位置を合わせて積層し、それから焼
結して第1の多層配線基板1を形成し、その後接続用ピ
ン2をロウ付けして製造するものであった。
In FIG. 1, external connection pins are attached to this type of multilayer wiring board. FIG. 2 is a front sectional view showing the configuration of a conventional example of a multilayer wiring board with connection pins. In the figure, 1 is a first multilayer wiring board, which includes a multilayer ceramic board 11, and Mo or W.
2 is a connecting pin. As shown in the figure, the first conductor 1
2 is wired inside and on the surface of the multilayer ceramic plate 11 in which a plurality of ceramic materials are laminated. This multilayer wiring board with connection pins has a structure such as this when the ceramic material is in a state before sintering, a so-called green sheet state.
Wiring is screen printed on the green sheet using conductor yeast such as MO or W, and the multiple ceramics and materials wired in this way are aligned and stacked, and then sintered to form the first multilayer wiring. It was manufactured by forming a substrate 1 and then soldering connection pins 2.

上記の製造過程において、配線された複数のセラミック
材の位置合せは機械的な精度できまるため、積層数を多
くするに、つれ配線の密度を小さくせざるを得す、積層
数に限界があると共に、高温焼結のため9個々のセラミ
ック材の板厚を薄くす□ることや配線の線幅を微細にす
ることにも限界があった。更に、高温で焼結するため、
その配線に使用される第1の導電体12は、セラミ、り
材の焼結温度に耐えられる高融点金属、つまり前記のM
oやWに限られてしまい、これら第1の導電体12の電
気抵抗が大きいことも、基板の回路特性として好ましい
ものではなかった。
In the above manufacturing process, the alignment of multiple wired ceramic materials is determined by mechanical precision, so as the number of layers increases, the density of wiring must be reduced, and there is a limit to the number of layers. At the same time, due to high-temperature sintering, there were limits to reducing the thickness of the individual ceramic materials and making the line width of the wiring finer. Furthermore, since it is sintered at high temperatures,
The first conductor 12 used for the wiring is made of ceramic, a high melting point metal that can withstand the sintering temperature of the material, that is, the above-mentioned M
The electrical resistance of these first conductors 12 is also unfavorable in terms of the circuit characteristics of the substrate.

本発明の目的は、高密度微細な多層配線基板を形成した
接続用ピン付多層配線基板を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a multilayer wiring board with connection pins in which a high-density and fine multilayer wiring board is formed.

本発明の他の目的は、配線用導電体・とじて高温焼結に
適したMoやWだけでなく電気抵抗の低い通常の導体金
属をも用いることを可能にした接続用ピン付多層配線基
板を提供することにある。
Another object of the present invention is to provide a multilayer wiring board with connection pins that makes it possible to use not only Mo and W, which are suitable for high-temperature sintering, but also ordinary conductive metals with low electrical resistance. Our goal is to provide the following.

、本発明によると、複数のセラミ、り材が積層された多
層セラミック板および該多層セラミック板の内部と表面
に配線された第1の導電体とから構成される第1の多層
配線基板と、前記第1の導電体と電気的に接続される外
部接続用ピンとを有する接続用ビン付多層配線基板にお
いて、前記第1の多層配線基板の表面に、複数の低温焼
成無機絶縁材が積層された多層無機絶縁板および該多層
無機絶縁板の内部と表面に配線された第2の導電体とか
ら構成される第2の多層配線基板を両溝電体が電気的−
に接続するように形成してなる多層配線基板とすると共
に、前記第2の多層配線基板の表面で前記第2の導電体
に固着した外部接続用ピンを取付けた接続用ピン付多層
配線基板力!得られる。
According to the present invention, a first multilayer wiring board comprising a multilayer ceramic board in which a plurality of ceramics and materials are laminated, and a first conductor wired inside and on the surface of the multilayer ceramic board; In the multilayer wiring board with connection pins having external connection pins electrically connected to the first conductor, a plurality of low temperature fired inorganic insulating materials are laminated on the surface of the first multilayer wiring board. A second multilayer wiring board consisting of a multilayer inorganic insulating board and a second conductor wired inside and on the surface of the multilayer inorganic insulating board is electrically
a multilayer wiring board formed to be connected to a multilayer wiring board, and a multilayer wiring board with connecting pins having external connection pins fixed to the second conductor on the surface of the second multilayer wiring board; ! can get.

以下2本発明の実施例につき図面を参照して説明する@ 第2図は1本発明の一実施例の構成を示した正面断面図
である。図において、lは第1の多層配線基板、2′は
接続用ピン、20は第2の多層配線基板である。第1の
多層配線基板lは、従来と同様、複数のセラミック材が
積層された多層セラミック板11と、多層セラミック板
11の内部及び表面に配線されたMOやWからなる第1
の導電体12とから構成され、その製造法も従来と同様
で21と、多層無機絶縁板21の内部及び表面に配線さ
れた第2の導電体22とから構成される。図に示される
ように、第1の多層配線基板1と第2の多層配線基板2
0は、互いに表面において両溝電体12と22が互いに
電気的に接続するように形成され、且つ接続用・ピン2
は、第2の多層配線基板20の表面で第2の導電体22
に固着されている。ここに使用される低温焼成無機絶縁
材としては1例えば100℃焼成ができる住人イヒ学工
業■製スミセラム(商品名)、150℃焼成ができる東
亜合成化学工業■製アロンセラミック(商品名)などが
ある。
Two embodiments of the present invention will be described below with reference to the drawings. Fig. 2 is a front sectional view showing the configuration of one embodiment of the present invention. In the figure, 1 is a first multilayer wiring board, 2' is a connection pin, and 20 is a second multilayer wiring board. As in the conventional case, the first multilayer wiring board l includes a multilayer ceramic board 11 in which a plurality of ceramic materials are laminated, and a first board made of MO or W wired inside and on the surface of the multilayer ceramic board 11.
The manufacturing method is the same as that of the conventional one, and the second conductor 21 is wired inside and on the surface of the multilayer inorganic insulating board 21. As shown in the figure, a first multilayer wiring board 1 and a second multilayer wiring board 2
0 is formed so that both groove electric bodies 12 and 22 are electrically connected to each other on the surface, and a connecting pin 2 is provided.
is the second conductor 22 on the surface of the second multilayer wiring board 20
is fixed to. Examples of low-temperature fired inorganic insulating materials used here include Sumiceram (trade name) manufactured by Jumi Ihigaku Kogyo ■, which can be fired at 100 degrees Celsius, and Aron Ceramic manufactured by Toagosei Chemical Industry ■ (trade name), which can be fired at 150 degrees Celsius. be.

このような構成により、従来の第1の多層配線基板1の
積層数を軽減できるので9位置合わせの精度を余り考慮
する必要がなく、それ自体従来よりは高密度化できる。
With such a configuration, the number of laminated layers of the conventional first multilayer wiring board 1 can be reduced, so there is no need to take too much consideration to the accuracy of nine-position alignment, and the density can itself be higher than that of the conventional one.

一方、第2の多層配線基板20社、低温焼成の無機絶縁
板21で構成されているため9個々の基板の板厚を薄く
でき、配線の線−も微細にすることができる。従って、
2個の基板1,200それぞれの表面で両溝電体12と
22が電気的に接続するように配置して構成された新し
い基板は、従来の基板と外形はほとんど同じであるにも
かかわらず、非常に高密度微細な基板を構成できた。
On the other hand, since the second multilayer wiring board is composed of 20 companies and low-temperature fired inorganic insulating boards 21, the thickness of each board can be made thinner, and the wiring lines can also be made finer. Therefore,
Although the new board is constructed by arranging both groove electric bodies 12 and 22 to be electrically connected on the surface of each of the two boards 1,200, the external shape is almost the same as that of the conventional board. , we were able to construct a very high-density and fine substrate.

又、微細化高密度化に適した第2の多層配線基板20と
、前述したように熱放散性2機械的強度に優れた第1の
多層配線基板1とを組合わせたことにより、各々の基板
の特長を生かした多層配線基板が構成できた。
In addition, by combining the second multilayer wiring board 20, which is suitable for miniaturization and high density, and the first multilayer wiring board 1, which has excellent heat dissipation properties and mechanical strength as described above, each We were able to construct a multilayer wiring board that takes advantage of the board's features.

更に、接続用ピン2は、第2の多層配線基板20側へ取
付けられるので、第1の多層配線基板lからの熱放散を
妨げない。従って2本発明による接続用ピン付多層配線
基板は、従来と同様絶縁性、熱放散性9機械的強度にお
いても申し分ない。
Furthermore, since the connecting pins 2 are attached to the second multilayer wiring board 20 side, they do not impede heat dissipation from the first multilayer wiring board l. Therefore, the multilayer wiring board with connection pins according to the present invention has excellent insulation properties, heat dissipation properties, and mechanical strength as well as the conventional ones.

そして、第2の多層配線基板20には、低温焼成無機絶
縁材の多層無機絶縁板21が使用されているので、多層
無機絶縁板21の内部及び表面に配線される第2の導電
体22の材料には、従来のMoやWと較べてその電気抵
抗が数分の1である通常の導体金属Cuが使用でき且つ
、第1の多層配線基板1の積層数も少なくなったので、
基板の回路特性も従来と較べ良くなった。
Since the second multilayer wiring board 20 uses a multilayer inorganic insulating board 21 made of a low-temperature fired inorganic insulating material, the second conductor 22 wired inside and on the surface of the multilayer inorganic insulating board 21 is As the material, ordinary conductive metal Cu, whose electrical resistance is a fraction of that of conventional Mo or W, can be used, and the number of laminated layers of the first multilayer wiring board 1 is reduced.
The circuit characteristics of the board have also improved compared to the conventional one.

以上の説明で明らかなように9本発明によると。As is clear from the above description, according to the present invention.

高密度微細なi続用す付多層配線基板を構成できる。It is possible to construct a multilayer wiring board with high-density and fine i-continuation.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、従来例の構成を示した正面断面図。 第2図は2本発明の一実施例の構成を示した正面断面図
である。 記号の説明: 1は第1の多層配線基板、 2は接続用ピン。 11は多層セラミック板、  12は第1の導電体。 20は第2の多層配線基板、21は多層無機絶縁板、2
2は第2の導電体をそれぞれあられしているO
FIG. 1 is a front sectional view showing the configuration of a conventional example. FIG. 2 is a front sectional view showing the configuration of an embodiment of the present invention. Explanation of symbols: 1 is the first multilayer wiring board, 2 is the connection pin. 11 is a multilayer ceramic plate, and 12 is a first conductor. 20 is a second multilayer wiring board, 21 is a multilayer inorganic insulating board, 2
2 represents the second conductor, respectively.

Claims (1)

【特許請求の範囲】[Claims] 1、 複数のセラミ、り材が積層された多層セラミック
板および該多層セラミック板の内部と表面に配線された
第1の導電体から構成される第1の多層配線基板と、前
記第1の導電体と電気的に接続される外部接続用ピンと
を有する接続用ピン付多層配線基板において、複数の低
温焼成無機絶縁材が積層された多層無機絶縁板および該
多層無機絶縁−板の内部と表面に配線された第2の導電
体とから構成される第2の多層配線基板を、前記第1の
多層配線基板の表面に両溝電体が電気的に接続するよう
に形成してなる多層配線基板とすると共に、前記外部接
続用ピンを前記第2の多層配線基板の表面で前記第2の
導電体に固着したことを特徴とする接続用ピン付多層配
線基板。
1. A first multilayer wiring board composed of a multilayer ceramic board in which a plurality of ceramics and materials are laminated, and a first conductor wired inside and on the surface of the multilayer ceramic board, and the first conductor A multilayer wiring board with connection pins that has external connection pins that are electrically connected to the body, a multilayer inorganic insulating board in which a plurality of low-temperature fired inorganic insulating materials are laminated, and the inside and surface of the multilayer inorganic insulating board. A multilayer wiring board formed by forming a second multilayer wiring board composed of a wired second conductor such that both groove electric bodies are electrically connected to the surface of the first multilayer wiring board. A multilayer wiring board with connection pins, wherein the external connection pins are fixed to the second conductor on the surface of the second multilayer wiring board.
JP16273881A 1981-10-14 1981-10-14 Multilayer circuit board with connecting pins Granted JPS5864094A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16273881A JPS5864094A (en) 1981-10-14 1981-10-14 Multilayer circuit board with connecting pins

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16273881A JPS5864094A (en) 1981-10-14 1981-10-14 Multilayer circuit board with connecting pins

Publications (2)

Publication Number Publication Date
JPS5864094A true JPS5864094A (en) 1983-04-16
JPH0210597B2 JPH0210597B2 (en) 1990-03-08

Family

ID=15760317

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16273881A Granted JPS5864094A (en) 1981-10-14 1981-10-14 Multilayer circuit board with connecting pins

Country Status (1)

Country Link
JP (1) JPS5864094A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60178695A (en) * 1984-02-17 1985-09-12 インタ−ナシヨナル ビジネス マシ−ンズ コ−ポレ−シヨン Electric mutual connecting package

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5586195A (en) * 1978-12-25 1980-06-28 Fujitsu Ltd Method of fabricating multilayer circuit board
JPS56115498A (en) * 1980-02-19 1981-09-10 Shimizu Construction Co Ltd Method of executing moving type side wall flask

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5586195A (en) * 1978-12-25 1980-06-28 Fujitsu Ltd Method of fabricating multilayer circuit board
JPS56115498A (en) * 1980-02-19 1981-09-10 Shimizu Construction Co Ltd Method of executing moving type side wall flask

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60178695A (en) * 1984-02-17 1985-09-12 インタ−ナシヨナル ビジネス マシ−ンズ コ−ポレ−シヨン Electric mutual connecting package

Also Published As

Publication number Publication date
JPH0210597B2 (en) 1990-03-08

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