JPH0238446Y2 - - Google Patents
Info
- Publication number
- JPH0238446Y2 JPH0238446Y2 JP1981122445U JP12244581U JPH0238446Y2 JP H0238446 Y2 JPH0238446 Y2 JP H0238446Y2 JP 1981122445 U JP1981122445 U JP 1981122445U JP 12244581 U JP12244581 U JP 12244581U JP H0238446 Y2 JPH0238446 Y2 JP H0238446Y2
- Authority
- JP
- Japan
- Prior art keywords
- die
- semiconductor element
- pad
- bonding
- bonded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 19
- 239000000853 adhesive Substances 0.000 claims description 3
- 230000001070 adhesive effect Effects 0.000 claims description 3
- 229910015365 Au—Si Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000006023 eutectic alloy Substances 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Description
【考案の詳細な説明】
本考案はICなどの半導体素子がダイボンドさ
れる構造の混成集積回路装置に関する。[Detailed Description of the Invention] The present invention relates to a hybrid integrated circuit device having a structure in which semiconductor elements such as ICs are die-bonded.
従来、素子裏面をアースさせる半導体素子を回
路基板にダイボンドする場合、第１図に示すよう
に、回路基板１のダイボンド部分に素子裏面とほ
ぼ同じ面積でAuからなる膜２を形成し、このAu
膜２から延長してアースパターン３を形成し、さ
らにダイボンド部分の周囲に所定のボンデイング
パツド４を形成し、そしてAu膜２上にAu−Siな
どの共晶合金で半導体素子５をダイボンドするよ
うにしている。しかし、こような構造では、半導
体素子５が大形化していくにともなつて、Au膜
２の面積を広く構成しなければならず、Au膜２
に費やすコストが無視できなくなるという欠点が
あつた。 Conventionally, when die-bonding a semiconductor element whose back surface is grounded to a circuit board, as shown in FIG.
A ground pattern 3 is formed extending from the film 2, a predetermined bonding pad 4 is further formed around the die-bonding part, and a semiconductor element 5 is die-bonded onto the Au film 2 using a eutectic alloy such as Au-Si. That's what I do. However, in such a structure, as the semiconductor element 5 becomes larger, the area of the Au film 2 must be increased, and the area of the Au film 2 becomes larger.
The drawback was that the costs involved could not be ignored.
本考案は、上述した従来の欠点を改良したの
で、搭載する半導体素子の形状、寸法にかかわら
ず、特に半導体素子が大形化しても、ダイボンド
特性をそれ程損わずに、ダイボンド部分のAu膜
を小さな面積で済ませられるようにした混成集積
回路装置を提供することを目的とする。 The present invention improves the above-mentioned conventional drawbacks, so regardless of the shape and dimensions of the semiconductor element to be mounted, even if the semiconductor element becomes large in size, the Au film on the die bond part can be used without significantly impairing the die bonding characteristics. An object of the present invention is to provide a hybrid integrated circuit device that can be completed in a small area.
以下、本考案の実施例を図面を参照しつつ詳述
する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
第２において、６は混成集積回路装置の回路基
板で、この基板６上には、ダイボンドされるIC
などの半導体素子７の裏面に対応するダイボンド
部分の周囲の所定個所にAuからなる複数のボン
デイングパツド８が形成され、さらに別の所定個
所にAuからなる細帯状のアースパツド９が形成
され、このアースパツド９はその先端がダイボン
ド部分にまで延長して形成されている。アースパ
ツド９のダイボンド部分に延びる部分は半導体素
子７の裏面すなわちダイボンド部分に比較して小
さな面積で構成されている。このアースパツド９
の延長部分を含むダイボンド部分にAg−エポキ
シなどの導電性接着剤１０により半導体素子７が
ダイボンドされている。そして、半導体素子７の
各電極と基板６上のパツドとの間にリード細線が
ワイヤボンドされている。本実施例によれば、ダ
イボンド部分のパツド面積が小さくて済み、パツ
ドのAuに費やすコストを低減できる。したがつ
て、従来の構造では半導体素子の大形化にともな
つてAuのコストも増大するが、本実施例はその
コストの増大を効果的に防ぐことができる。しか
もダイボンド特性を損うことはない。 In the second part, 6 is a circuit board of a hybrid integrated circuit device, and on this board 6 is an IC to be die-bonded.
A plurality of bonding pads 8 made of Au are formed at predetermined locations around the die-bonding portion corresponding to the back surface of the semiconductor element 7, and a strip-shaped grounding pad 9 made of Au is formed at another predetermined location. The ground pad 9 is formed such that its tip extends to the die bonding portion. The portion of the ground pad 9 extending to the die bonding portion has a smaller area than the back surface of the semiconductor element 7, that is, the die bonding portion. This earth pad 9
A semiconductor element 7 is die-bonded to a die-bonding portion including an extended portion of the semiconductor element 7 using a conductive adhesive 10 such as Ag-epoxy. A thin lead wire is wire-bonded between each electrode of the semiconductor element 7 and a pad on the substrate 6. According to this embodiment, the pad area of the die-bonding portion can be small, and the cost of Au for the pad can be reduced. Therefore, in the conventional structure, the cost of Au increases as the size of the semiconductor device increases, but this embodiment can effectively prevent the increase in cost. Moreover, the die bonding properties are not impaired.
第３図は他の実施例を示し、上記実施例との相
違点は、ダイボンド部分にダミーパツド１１を設
け、ダイボンド時における半導体素子７の傾きを
なくするようにしたことにある。ダミーパツド１
１の形状および配置は半導体素子７の裏面の形状
にあわせて適宜決定すればよい。他の構成は上記
実施例とほぼ同様であるから同一符号を付けてそ
の説明を省略する。 FIG. 3 shows another embodiment, which differs from the above embodiment in that a dummy pad 11 is provided at the die bonding portion to eliminate the inclination of the semiconductor element 7 during die bonding. Dummy pad 1
The shape and arrangement of the semiconductor element 7 may be appropriately determined according to the shape of the back surface of the semiconductor element 7. Since the other configurations are substantially the same as those of the above embodiment, the same reference numerals are given and the explanation thereof will be omitted.
本考案は、ダイボンド部分に延びるアースパツ
ドの面積を小さくし、そのダイボンド部分に半導
体素子を導電性接着剤によりダイボンドするよう
にしているので、無駄なAuパツドをなくし、コ
スト低減を図ることができる。 In the present invention, the area of the ground pad extending to the die-bonding part is reduced, and the semiconductor element is die-bonded to the die-bonding part using a conductive adhesive, thereby eliminating unnecessary Au pads and reducing costs.
第１図は従来の混成集積回路装置の平面図、第
２図は本考案による混成集積回路装置の一実施例
を示し、同図ａは平面図、同図ｂは断面図、第３
図は他の実施例を示す平面図である。
６……回路基板、７……半導体素子、８……ボ
ンデイングパツド、９……アースパツド。
FIG. 1 is a plan view of a conventional hybrid integrated circuit device, and FIG. 2 is an embodiment of the hybrid integrated circuit device according to the present invention.
The figure is a plan view showing another embodiment. 6... Circuit board, 7... Semiconductor element, 8... Bonding pad, 9... Earth pad.
Claims (1)
え、回路基板のダイボンド部分の周囲に、複数の
Auからなるボンデイングパツドを形成し、かつ
ダイボンド部分より小さい面積でもつてダイボン
ド部分にのびる、Auからなるアースパツドを形
成し、半導体素子を回路基板のダイボンド部分に
導電性接着剤によりダイボンドするようにしたこ
とを特徴とする混成集積回路装置。 It is equipped with a circuit board to which semiconductor elements are die-bonded, and a plurality of
A bonding pad made of Au is formed, and a grounding pad made of Au is formed that extends to the die bonding part with an area smaller than the die bonding part, and the semiconductor element is die-bonded to the die bonding part of the circuit board using a conductive adhesive. A hybrid integrated circuit device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12244581U JPS5827935U (en) | 1981-08-18 | 1981-08-18 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12244581U JPS5827935U (en) | 1981-08-18 | 1981-08-18 | Hybrid integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5827935U JPS5827935U (en) | 1983-02-23 |
| JPH0238446Y2 true JPH0238446Y2 (en) | 1990-10-17 |
Family
ID=29916366
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12244581U Granted JPS5827935U (en) | 1981-08-18 | 1981-08-18 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5827935U (en) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58127338A (en) * | 1982-01-25 | 1983-07-29 | Sharp Corp | Structure of electronic part |
| JPS6122728U (en) * | 1984-07-16 | 1986-02-10 | 株式会社吉野工業所 | container |
| US8740962B2 (en) | 2006-11-07 | 2014-06-03 | Dc Devices, Inc. | Prosthesis for retrieval and deployment |
| US20110257723A1 (en) | 2006-11-07 | 2011-10-20 | Dc Devices, Inc. | Devices and methods for coronary sinus pressure relief |
| US10413284B2 (en) | 2006-11-07 | 2019-09-17 | Corvia Medical, Inc. | Atrial pressure regulation with control, sensing, monitoring and therapy delivery |
| CA2664557C (en) | 2006-11-07 | 2015-05-26 | David Stephen Celermajer | Devices and methods for the treatment of heart failure |
| US9232997B2 (en) | 2006-11-07 | 2016-01-12 | Corvia Medical, Inc. | Devices and methods for retrievable intra-atrial implants |
| US9277995B2 (en) | 2010-01-29 | 2016-03-08 | Corvia Medical, Inc. | Devices and methods for reducing venous pressure |
| EP2673038B1 (en) | 2011-02-10 | 2017-07-19 | Corvia Medical, Inc. | Apparatus to create and maintain an intra-atrial pressure relief opening |
| US9205236B2 (en) | 2011-12-22 | 2015-12-08 | Corvia Medical, Inc. | Methods, systems, and devices for resizable intra-atrial shunts |
| US10675450B2 (en) | 2014-03-12 | 2020-06-09 | Corvia Medical, Inc. | Devices and methods for treating heart failure |
| WO2016014821A1 (en) | 2014-07-23 | 2016-01-28 | Corvia Medical, Inc. | Devices and methods for treating heart failure |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55150251A (en) * | 1979-05-11 | 1980-11-22 | Hitachi Ltd | Semiconductor device |
| JPS5797634A (en) * | 1980-12-11 | 1982-06-17 | Canon Inc | Hybrid integrated circuit |
-
1981
- 1981-08-18 JP JP12244581U patent/JPS5827935U/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55150251A (en) * | 1979-05-11 | 1980-11-22 | Hitachi Ltd | Semiconductor device |
| JPS5797634A (en) * | 1980-12-11 | 1982-06-17 | Canon Inc | Hybrid integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5827935U (en) | 1983-02-23 |
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