JPS58127338A - Structure of electronic part - Google Patents

Structure of electronic part

Info

Publication number
JPS58127338A
JPS58127338A JP57010534A JP1053482A JPS58127338A JP S58127338 A JPS58127338 A JP S58127338A JP 57010534 A JP57010534 A JP 57010534A JP 1053482 A JP1053482 A JP 1053482A JP S58127338 A JPS58127338 A JP S58127338A
Authority
JP
Japan
Prior art keywords
electrode pattern
lsi chip
substrate
region
shielding resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57010534A
Other languages
Japanese (ja)
Other versions
JPS6364899B2 (en
Inventor
Toru Yamashita
徹 山下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP57010534A priority Critical patent/JPS58127338A/en
Publication of JPS58127338A publication Critical patent/JPS58127338A/en
Publication of JPS6364899B2 publication Critical patent/JPS6364899B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To eliminate the inflow process of light shielding resin and prevent mis-operation due to noise by covering region on substrate opposing to the specified region of bottom surface of LSI chip to be bonded with a material used for forming electrode pattern on said substrate. CONSTITUTION:Since a grounding electrode pattern 7 consisting of not-transparent conductive material is extendingly formed on the region 8 on which a light shielding resin of substrate 1 is to be flowed in, light can be shielded. Therefore, after an LSI chip is bonded to an electrode pattern 2, it is no longer necessary to supply the light shielding resin into a narrow gap between them. Namely, the LSI chip can immediately be sealed with the potting resin after the bonding. Moreover, since the bottom part of LSI chip is covered with a conductive film provided on the region 8, namely with the grounding electrode pattern 7, influence of noise can be prevented and cause of misoperation of LSI can be eliminated.

Description

【発明の詳細な説明】 本発明は基板に形成した電極パターンにＬＳＩチップを
ボンディングする電子部品の構造如関するＯ 従来のこの種電子部品の構造は第１図及び第２図に示す
通シ、基板１に形成した電極パターン２の上に図示の如
＜ＬＳＩチップ４を載置し、半田バンプ３のところで該
チップとパターンを電気的に接続するとともに、基板１
とＬＳＩチップとの隙間に遮光用樹脂５を流し込んでの
ち、該チップをポンチング樹脂６にて封入している。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of an electronic component in which an LSI chip is bonded to an electrode pattern formed on a substrate. As shown in the figure, an LSI chip 4 is placed on the electrode pattern 2 formed on the substrate 1, and the chip and the pattern are electrically connected at the solder bumps 3.
After pouring a light shielding resin 5 into the gap between the LSI chip and the LSI chip, the chip is sealed with punching resin 6.

然し乍ら、上記従来の電子部品の構造では非常に狭い隙
間に遮光用樹脂５を流入させる工程が必要であるために
製造が煩雑となる欠点があり、さらに今一つの欠点はＬ
ＳＩチップの下が樹脂であるがために、該チップがノイ
ズを受けて誤動作し易いということである。However, the structure of the conventional electronic component described above has the disadvantage that manufacturing is complicated because it requires a process of flowing the light-shielding resin 5 into a very narrow gap, and another disadvantage is that L
Since the bottom of the SI chip is made of resin, the chip is susceptible to noise and tends to malfunction.

本発明はかかる従来の欠点に鑑み、遮光用樹脂５の流入
工程を省き且つノイズによる誤動作を防止することがで
きる電子部品の構造の提供を目的とするものである。In view of these conventional drawbacks, the present invention aims to provide a structure of an electronic component that can omit the step of introducing the light-shielding resin 5 and prevent malfunctions due to noise.

以下、第３図にもとづいて本発明の一実施例を詳細に説
明すると、本発明の電子部品は電極パターン２の１つで
ある接地用の電極パターン７を基板１の遮光用樹脂を流
入塗布すべき部分、即ち図に示す如く四方に分散形成し
た電極パターン群２の中央部まで延長し、さらに他の電
極パターン２と接触しない程度にできるだけ広い領域８
にわたって形成している。Hereinafter, one embodiment of the present invention will be described in detail based on FIG. 3. In the electronic component of the present invention, the grounding electrode pattern 7, which is one of the electrode patterns 2, is coated with the light-shielding resin of the substrate 1. The area 8 extends to the desired area, that is, the center of the electrode pattern group 2 distributed in all directions as shown in the figure, and is as wide as possible to the extent that it does not come into contact with other electrode patterns 2.
It is formed over a period of time.

かかる構成によれば、従来基板１の遮光用樹脂を流入塗
布すべき領域８に不透明な導電部材からなる接地用電極
パターン７を延長形成しているので、このパターンによ
って光を遮断することができる。このだめ、電極パター
ン２にＬＳＩチップをボンディングしたのちは該両者間
の狭い隙間に遮光用樹脂を流入させる必要がない。つま
り、ボンディング後は直ちにポツティング樹脂にてＬＳ
Ｉチップを封入することができる０ さらに、ＬＳＩチップの底部は上記領域８に設けた導電
膜、すなわち接地用電極パターン７により被覆された形
となっているので、ノイズの影響を防止し、ＬＳＩの誤
動作の原因を解消することができる。According to this configuration, since the grounding electrode pattern 7 made of an opaque conductive material is extended and formed in the region 8 of the conventional substrate 1 where the light-shielding resin is to be applied, light can be blocked by this pattern. . However, after bonding the LSI chip to the electrode pattern 2, there is no need to flow the light-shielding resin into the narrow gap between the two. In other words, after bonding, immediately apply LS with potting resin.
Furthermore, since the bottom of the LSI chip is covered with the conductive film provided in the area 8, that is, the grounding electrode pattern 7, the influence of noise is prevented and the LSI chip is sealed. The cause of the malfunction can be eliminated.

以上のように本発明によれば、ボンディングするＬＳＩ
チップ底面の所定の領域に対向する基板上の領域を該基
板に形成する電極パターン構成部材にて被覆するもので
あるから、遮光用樹脂の流人工程を省き且つノイズによ
る誤動作を防止することができる。As described above, according to the present invention, the LSI to be bonded
Since the area on the substrate opposite to the predetermined area on the bottom of the chip is covered with the electrode pattern component formed on the substrate, the process of distributing the light-shielding resin can be omitted and malfunctions due to noise can be prevented. can.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の電子部品の要部構造を示す図、第２図は
同電子部品の縦断面図、第３図は本発明に係る電子部品
の要部構造を示す図である。 １は基板、２は電極パターン、４はＬＳＩチップ、７は
接地用電極パターン、８は接地用電極パターンの延長形
成部FIG. 1 is a diagram showing the main structure of a conventional electronic component, FIG. 2 is a longitudinal sectional view of the electronic component, and FIG. 3 is a diagram showing the main structure of an electronic component according to the present invention. 1 is a substrate, 2 is an electrode pattern, 4 is an LSI chip, 7 is a grounding electrode pattern, and 8 is an extension of the grounding electrode pattern.

Claims (1)

【特許請求の範囲】 １、基板に形成した電極パターンにＬＳＩチップをボン
ディングする電子部品に於て、上記ＬＳＩチップ底面の
所定の領域に対向する上記基板上の領域を上記電極パタ
ーン構成部材にて被覆して成ることを特徴とする電子部
品の構造。 ２、上記電極パターンのうち接地用電極パターンを上記
基板上の領域まで延長形成してなることを特徴とする特
許請求の範囲第１項に記載の電子部品の構造。[Claims] 1. In an electronic component in which an LSI chip is bonded to an electrode pattern formed on a substrate, an area on the substrate opposite to a predetermined area on the bottom surface of the LSI chip is bonded with the electrode pattern constituent member. A structure of an electronic component characterized by being coated. 2. The structure of an electronic component according to claim 1, wherein a grounding electrode pattern of the electrode pattern is formed to extend to a region on the substrate.
JP57010534A 1982-01-25 1982-01-25 Structure of electronic part Granted JPS58127338A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57010534A JPS58127338A (en) 1982-01-25 1982-01-25 Structure of electronic part

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57010534A JPS58127338A (en) 1982-01-25 1982-01-25 Structure of electronic part

Publications (2)

Publication Number Publication Date
JPS58127338A true JPS58127338A (en) 1983-07-29
JPS6364899B2 JPS6364899B2 (en) 1988-12-14

Family

ID=11752924

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57010534A Granted JPS58127338A (en) 1982-01-25 1982-01-25 Structure of electronic part

Country Status (1)

Country Link
JP (1) JPS58127338A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60147140A (en) * 1984-01-11 1985-08-03 Hitachi Ltd Mounting process of semiconductor element chip
EP1246241A3 (en) * 2001-03-30 2005-05-18 Kabushiki Kaisha Toshiba Semiconductor package

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS519681A (en) * 1974-07-15 1976-01-26 Seiko Instr & Electronics
JPS53112061A (en) * 1977-03-11 1978-09-30 Sharp Corp Wiring substrate of semiconductor chip
JPS5474369A (en) * 1977-11-26 1979-06-14 Fujitsu Ltd Semiconductor device
JPS56110292A (en) * 1980-02-06 1981-09-01 Hitachi Ltd Semiconductor device
JPS56148840A (en) * 1980-04-22 1981-11-18 Citizen Watch Co Ltd Mounting structure for ic
JPS5827935U (en) * 1981-08-18 1983-02-23 株式会社村田製作所 Hybrid integrated circuit device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5827935B2 (en) * 1975-03-31 1983-06-13 アルトン オクスナ− メデイカル フアウンデ−シヨン Short circuit defect closure device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS519681A (en) * 1974-07-15 1976-01-26 Seiko Instr & Electronics
JPS53112061A (en) * 1977-03-11 1978-09-30 Sharp Corp Wiring substrate of semiconductor chip
JPS5474369A (en) * 1977-11-26 1979-06-14 Fujitsu Ltd Semiconductor device
JPS56110292A (en) * 1980-02-06 1981-09-01 Hitachi Ltd Semiconductor device
JPS56148840A (en) * 1980-04-22 1981-11-18 Citizen Watch Co Ltd Mounting structure for ic
JPS5827935U (en) * 1981-08-18 1983-02-23 株式会社村田製作所 Hybrid integrated circuit device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60147140A (en) * 1984-01-11 1985-08-03 Hitachi Ltd Mounting process of semiconductor element chip
JPH0315337B2 (en) * 1984-01-11 1991-02-28 Hitachi Ltd
EP1246241A3 (en) * 2001-03-30 2005-05-18 Kabushiki Kaisha Toshiba Semiconductor package
US7148529B2 (en) 2001-03-30 2006-12-12 Kabushiki Kaisha Toshiba Semiconductor package

Also Published As

Publication number Publication date
JPS6364899B2 (en) 1988-12-14

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