JPH04206683A - Manufacture of printed circuit board - Google Patents
Manufacture of printed circuit boardInfo
- Publication number
- JPH04206683A JPH04206683A JP33466190A JP33466190A JPH04206683A JP H04206683 A JPH04206683 A JP H04206683A JP 33466190 A JP33466190 A JP 33466190A JP 33466190 A JP33466190 A JP 33466190A JP H04206683 A JPH04206683 A JP H04206683A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- conductor pattern
- electrode region
- pattern
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 229910000679 solder Inorganic materials 0.000 claims abstract description 30
- 239000004020 conductor Substances 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 12
- 238000005476 soldering Methods 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 7
- 239000000919 ceramic Substances 0.000 abstract description 4
- 239000006071 cream Substances 0.000 abstract description 2
- 239000000463 material Substances 0.000 abstract 4
- 239000011521 glass Substances 0.000 description 6
- 230000001681 protective effect Effects 0.000 description 5
- 230000007423 decrease Effects 0.000 description 3
- 230000002265 prevention Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
[発明の目的]
〈産業上の利用分野〉
本発明は、基板表面に電極部領域を有する導体パターン
を形成し、この電極部領域にはんだを盛り、リフローに
より部品等をはんだ付けする配線基板の製造方法に関す
る。[Detailed Description of the Invention] [Objective of the Invention] <Industrial Application Field> The present invention involves forming a conductor pattern having an electrode region on the surface of a substrate, applying solder to the electrode region, and attaching parts, etc. by reflow. The present invention relates to a method of manufacturing a wiring board to which a wiring board is soldered.
〈従来の技術〉
従来から、ハイブリッドIC等に於て、セラミック等か
らなる基板表面に所望のパターンに導体膜を形成し、更
に抵抗体膜を形成し、上記導体パターンの電極部領域に
例えば印刷によりはんだを盛り、リフローにより部品等
をはんだ付けする配線基板の製造方法が行われている。<Prior art> Conventionally, in hybrid ICs and the like, a conductor film is formed in a desired pattern on the surface of a substrate made of ceramic or the like, a resistor film is further formed, and the electrode area of the conductor pattern is printed, for example. A method of manufacturing a wiring board is used in which solder is applied using a method of soldering, and components and the like are soldered by reflow.
しかしながら、リフロー時に電極部領域に連続する例え
ば配線部領域に電極部領域から溶融はんだが流れ込む虞
れがあった。However, during reflow, there is a risk that molten solder may flow from the electrode region into, for example, a wiring region that is continuous with the electrode region.
一方、このような配線基板に於て、導体パターンや抵抗
体パターンを外乱から保護する目的でガラス保護膜によ
り覆う構造があり、この構造によればガラス保護膜によ
り覆わない窓を上記電極部領域に設けることから、上記
溶融はんだがこの窓の境界部にて流れ止めされ、電極部
領域から導体パターンの他の部分に流れ込む心配がない
。On the other hand, in such a wiring board, there is a structure in which the conductor pattern and the resistor pattern are covered with a glass protective film for the purpose of protecting them from external disturbances. According to this structure, the window not covered with the glass protective film is covered with the electrode area. Since the molten solder is provided in the window, the flow of the molten solder is stopped at the border of the window, and there is no fear that the molten solder will flow from the electrode area to other parts of the conductor pattern.
しかしながら、上記したようなガラス保護膜は、ガラス
ペーストを塗布した後焼成することにより形成するが、
焼成過程で導体の拡散などを理由として抵抗体膜の抵抗
値が低下するため、その低下を見込んで抵抗体パターン
を設計しなければならない問題があった。また、部品搭
載後に基板全体を樹脂モールドすれば、基板保護上は上
記したガラス保護膜は場合によっては必ずしも必要では
ない。However, the glass protective film as described above is formed by applying glass paste and then baking it.
Since the resistance value of the resistor film decreases due to conductor diffusion during the firing process, there is a problem in that the resistor pattern must be designed with this decrease in mind. Furthermore, if the entire board is resin-molded after mounting the components, the above-mentioned glass protective film is not necessarily necessary in terms of protecting the board.
〈発明が解決しようとする課題〉
このような従来技術の問題点に鑑み、本発明の主な目的
は、配線基板の導体パターンに於ける電極部領域にはん
だ溶融したはんだが流れ込むことがなく、かつ配線基板
の設計が煩雑化することのない配線基板の製造方法を提
供することにある。<Problems to be Solved by the Invention> In view of the problems of the prior art, the main object of the present invention is to prevent molten solder from flowing into the electrode region of the conductor pattern of the wiring board. Another object of the present invention is to provide a method for manufacturing a wiring board in which the design of the wiring board does not become complicated.
[発明の構成]
〈課題を解決するための手段〉
このような目的は、本発明によれば、基板表面に部品等
をはんだ付けするための電極部領域を有する導体パター
ンを形成する過程と、形成された前記導体パターンに応
じて抵抗体パターンを形成する過程と、前記電極部領域
上にはんだを盛る過程と前記部品をリフローにより取付
ける過程とを有する配線基板の製造方法であって、前記
抵抗体パターン形成時に、前記導体パターンに於ける前
記電極部領域と該電極部領域から連続する他の部分との
境界部に抵抗体からなる前記はんだの流れ止め部を形成
することを特徴とする配線基板の製造方法を提供するこ
とにより達成される。[Structure of the Invention] <Means for Solving the Problems> According to the present invention, these objects include a process of forming a conductor pattern having an electrode region for soldering components, etc. on the surface of a substrate; A method for manufacturing a wiring board, comprising: forming a resistor pattern according to the formed conductor pattern; applying solder on the electrode area; and attaching the component by reflow. Wiring characterized in that, when forming a body pattern, a solder flow stopper made of a resistor is formed at a boundary between the electrode region and another portion continuous from the electrode region in the conductor pattern. This is achieved by providing a method for manufacturing a substrate.
〈作用〉
このように、抵抗体パターン形成時に、導体パターンの
電極部領域と他の部分との境界部に抵抗体からなるはん
だの流れ止め部分を形成することにより、溶融したはん
だが電極部領域から他の部分に流れ込むことがなくなり
、かつ製造工程が簡略化される。<Function> In this way, when forming a resistor pattern, by forming a solder stopper made of a resistor at the boundary between the electrode area and other parts of the conductor pattern, molten solder is prevented from flowing into the electrode area. This prevents the liquid from flowing into other parts, and the manufacturing process is simplified.
〈実施例〉
以下に添付の図面を参照して本発明を特定の実施例につ
いて詳細に説明する。Embodiments The present invention will now be described in detail with reference to specific embodiments with reference to the accompanying drawings.
第1図は本発明に基づく保護構造が適用されたハイブリ
ッドICの要部平面図を示す。FIG. 1 shows a plan view of essential parts of a hybrid IC to which a protection structure according to the present invention is applied.
セラミック基板1の表面には導体パターン2及び抵抗体
パターン3が形成されている。導体パターン2は、チッ
プ部品等が搭載される電極部領域4及びこの電極部領域
4に連続する配線部領域5を有している。A conductor pattern 2 and a resistor pattern 3 are formed on the surface of the ceramic substrate 1. The conductor pattern 2 has an electrode region 4 on which a chip component or the like is mounted, and a wiring region 5 continuous to the electrode region 4.
第2図及び第3図に良く示すように、電極部領域4と配
線部領域5との境界部には抵抗体膜からなるはんだ流れ
止め部6が形成されている。電極部領域4上にははんだ
7をもって部品8が取付けられている。As clearly shown in FIGS. 2 and 3, a solder flow stopper 6 made of a resistor film is formed at the boundary between the electrode region 4 and the wiring region 5. A component 8 is attached onto the electrode region 4 with solder 7.
以下に、このようなハイブリッドICの要部の製造手順
を説明する。まず、セラミック基板1の表面に導体パタ
ーン2を例えばスクリーン印刷により形成する。The manufacturing procedure of the main parts of such a hybrid IC will be explained below. First, the conductor pattern 2 is formed on the surface of the ceramic substrate 1 by, for example, screen printing.
次に、抵抗体パターン3を上記同様例えばスクリーン印
刷により形成する。このとき、導体パターン2に於ける
電極部領域4と配線部領域5との境界部に抵抗体膜から
なるはんだ流れ止め部6を同時に形成する。Next, the resistor pattern 3 is formed by screen printing, for example, as described above. At this time, a solder flow prevention part 6 made of a resistor film is simultaneously formed at the boundary between the electrode part region 4 and the wiring part region 5 in the conductor pattern 2.
次に、電極部領域4上にクリームはんだ7を印刷により
盛る。Next, cream solder 7 is applied onto the electrode area 4 by printing.
次に、はんだ7が盛られた電極部領域4に部品8を搭載
してリフローによりはんだ付けする。このとき、はんだ
流れ止め部6か形成されていることから電極部領域4か
ら配線部領域5に溶融したはんだ7が流れ込むことがな
い。Next, the component 8 is mounted on the electrode area 4 covered with the solder 7 and soldered by reflow. At this time, since the solder flow prevention part 6 is formed, the molten solder 7 does not flow from the electrode part area 4 to the wiring part area 5.
そして、この状態でこれら導体パターン2、抵抗体パタ
ーン3、はんだ7及び部品8等を含む基板全体が樹脂モ
ールドされることとなる。In this state, the entire board including the conductor pattern 2, resistor pattern 3, solder 7, components 8, etc. is resin molded.
[発明の効果]
このように本発明によれば、抵抗体パターンの形成時に
、導体パターンの電極部領域と他の部分との境界部に抵
抗体からなるはんだの流れ止め部分を形成することによ
り、溶融したはんだが電極部領域から他の部分に流れ込
むことを防止でき、かつ配線基板の製造工程が簡略化さ
れる。そして、ガラス保護膜の塗布、焼成工程を不要と
することができ、抵抗体膜の抵抗値の低下を防止するこ
とができる。以上のことから本発明の効果は大である。[Effects of the Invention] As described above, according to the present invention, when forming a resistor pattern, by forming a solder flow prevention part made of a resistor at the boundary between the electrode area and other parts of the conductor pattern, In addition, it is possible to prevent molten solder from flowing from the electrode region to other parts, and the manufacturing process of the wiring board is simplified. Further, it is possible to eliminate the need for applying and baking a glass protective film, and it is possible to prevent a decrease in the resistance value of the resistor film. From the above, the effects of the present invention are significant.
第1図は、本発明が適用されたハイブリッドICの要部
平面図である。
第2図は、第1図の部分拡大図である。
第3図は、第2図の■−■線について見た断面図である
。FIG. 1 is a plan view of essential parts of a hybrid IC to which the present invention is applied. FIG. 2 is a partially enlarged view of FIG. 1. FIG. 3 is a sectional view taken along the line ■--■ in FIG. 2.
Claims (1)
を有する導体パターンを形成する過程と、形成された前
記導体パターンに応じて抵抗体パターンを形成する過程
と、前記電極部領域上にはんだを盛る過程と前記部品を
リフローにより取付ける過程とを有する配線基板の製造
方法であって、前記抵抗体パターン形成時に、前記導体
パターンに於ける前記電極部領域と該電極部領域から連
続する他の部分との境界部に抵抗体からなる前記はんだ
の流れ止め部を形成することを特徴とする配線基板の製
造方法。A process of forming a conductor pattern having an electrode area for soldering parts etc. on the surface of the board, a process of forming a resistor pattern according to the formed conductor pattern, and a process of applying solder on the electrode area. A method for manufacturing a wiring board, comprising a step of mounting the component and a step of attaching the component by reflow, the method comprising: forming the resistor pattern; A method of manufacturing a wiring board, comprising forming a solder flow stopper made of a resistor at a boundary between the solder and the solder.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP33466190A JPH04206683A (en) | 1990-11-30 | 1990-11-30 | Manufacture of printed circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP33466190A JPH04206683A (en) | 1990-11-30 | 1990-11-30 | Manufacture of printed circuit board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04206683A true JPH04206683A (en) | 1992-07-28 |
Family
ID=18279852
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP33466190A Pending JPH04206683A (en) | 1990-11-30 | 1990-11-30 | Manufacture of printed circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04206683A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6881278B2 (en) | 1998-06-10 | 2005-04-19 | Showa Denko K.K. | Flux for solder paste |
JP2010067850A (en) * | 2008-09-11 | 2010-03-25 | Sanyo Electric Co Ltd | Circuit device |
JPWO2011040480A1 (en) * | 2009-09-30 | 2013-02-28 | 株式会社村田製作所 | Circuit board |
JP2022014122A (en) * | 2020-07-06 | 2022-01-19 | 日本特殊陶業株式会社 | Wiring board |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6310582B2 (en) * | 1982-11-30 | 1988-03-08 | Nippon Denki Hoomu Erekutoronikusu Kk | |
JPS63302595A (en) * | 1987-06-02 | 1988-12-09 | Murata Mfg Co Ltd | Mounting structure of chip component |
JPH0224570B2 (en) * | 1985-05-29 | 1990-05-30 | Masatoshi Nakano |
-
1990
- 1990-11-30 JP JP33466190A patent/JPH04206683A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6310582B2 (en) * | 1982-11-30 | 1988-03-08 | Nippon Denki Hoomu Erekutoronikusu Kk | |
JPH0224570B2 (en) * | 1985-05-29 | 1990-05-30 | Masatoshi Nakano | |
JPS63302595A (en) * | 1987-06-02 | 1988-12-09 | Murata Mfg Co Ltd | Mounting structure of chip component |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6881278B2 (en) | 1998-06-10 | 2005-04-19 | Showa Denko K.K. | Flux for solder paste |
JP2010067850A (en) * | 2008-09-11 | 2010-03-25 | Sanyo Electric Co Ltd | Circuit device |
JPWO2011040480A1 (en) * | 2009-09-30 | 2013-02-28 | 株式会社村田製作所 | Circuit board |
JP2022014122A (en) * | 2020-07-06 | 2022-01-19 | 日本特殊陶業株式会社 | Wiring board |
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