JPS62291128A - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device

Info

Publication number
JPS62291128A
JPS62291128A JP61136682A JP13668286A JPS62291128A JP S62291128 A JPS62291128 A JP S62291128A JP 61136682 A JP61136682 A JP 61136682A JP 13668286 A JP13668286 A JP 13668286A JP S62291128 A JPS62291128 A JP S62291128A
Authority
JP
Japan
Prior art keywords
wire
bonded
integrated circuit
substrate
insulating substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61136682A
Other languages
Japanese (ja)
Inventor
Kenichi Ishii
石井　研一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61136682A priority Critical patent/JPS62291128A/en
Publication of JPS62291128A publication Critical patent/JPS62291128A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To form electronic circuits which has semiconductor chips on both side surfaces of an insulating substrate by containing the chips so wire bonded as to conceal the upper edges of wire loops in a deep recess region formed on both side surfaces of the substrate. CONSTITUTION:Semiconductor chips 4 are secured in the recess regions 2 of an insulating substrate 1, bonded by gold or aluminum wirings 5, the substrate 1 is overturned, chips 4 are similarly secured in the regions 2, and bonded by ordinary means. Then, to protect the chips 4 and the wirings 5, they are coated with protective resin films 6, capacitor elements 7 and resistance elements 8 are mounted, and secured with solders 9. Thus, semiconductor elements can be mounted by normal wire bonding technique on both side surfaces of the substrate.

Description

【発明の詳細な説明】 ３、発明の詳細な説明 〔産業上の利用分野〕 本発明は混成集積回路装置に関する。[Detailed description of the invention] 3. Detailed description of the invention [Industrial application field] The present invention relates to hybrid integrated circuit devices.

〔従来の技術〕[Conventional technology]

従来の混成集積回路装置は、通常、セラミック基板の片
面にのみ電子回路が形成される。すなわち、セラミック
基板の片面に受動素子および配線パターンを厚膜または
薄膜技術を用いて形成し、その電極パターンに半導体チ
ップ或いはモールドＩＣの能動素子をデイスクリートの
抵抗およびコンデンサの各回路素子と共に搭載して電子
回路を構成している。Conventional hybrid integrated circuit devices typically have electronic circuitry formed on only one side of a ceramic substrate. That is, passive elements and wiring patterns are formed on one side of a ceramic substrate using thick film or thin film technology, and active elements of semiconductor chips or molded ICs are mounted on the electrode patterns along with circuit elements such as discrete resistors and capacitors. constitutes an electronic circuit.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし、最近の技術動向は混成集積回路装置に対しても
その実装密度の向上を要求して来ており、これを受けて
多数の提案がなされている。これらのうち最も実施し易
い提案の一つは基板の両面に電子回路をそれぞれ形成す
る方法である。ｊ〜かしながら、この方法では搭載する
回路素子が全てディスクリート部品として取扱い得るも
のであればよいが、能動素子が半導体チップのままでは
実施することができないので高密度化が制約される。However, recent technological trends have required improvements in the packaging density of hybrid integrated circuit devices, and in response to this demand, numerous proposals have been made. Among these proposals, one of the proposals that is easiest to implement is a method of forming electronic circuits on both sides of the substrate. However, although this method suffices as long as all the circuit elements to be mounted can be handled as discrete components, it cannot be implemented if the active elements are semiconductor chips, which limits high density.

すなわち、半導体チップは基板の片面の配線とは容易に
ワイヤ・ボンディング接続できるが、これを更に裏返し
て再びワイヤ・ボンダーのステージに載せ再度ワイヤ・
ボンディング作業を行うことは既にボンディング済みの
片面のボンディング・ワイヤを傷め使用し得ない状態に
置くこととなるので、半導体チップを両面釦載置するこ
とができずこのままでは混成集積回路装置の高密度実装
を達成することができない。In other words, a semiconductor chip can be easily wire-bonded to the wiring on one side of the board, but it is then turned over and placed on the wire bonder stage again.
Performing the bonding process damages the bonding wire on one side that has already been bonded, making it unusable. Therefore, it is not possible to mount semiconductor chips on double-sided buttons, and if this continues, the high density of the hybrid integrated circuit device will be reduced. Unable to achieve implementation.

本発明の目的は、上記の情況に鑑み、半導体チップを含
む電子回路を絶縁基板の両面に形成し得るようにした混
成集積回路装置を提供することである。SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a hybrid integrated circuit device in which electronic circuits including semiconductor chips can be formed on both sides of an insulating substrate.

〔問題点を解決するだめの手段〕[Failure to solve the problem]

本発明の混成集積回路装置は、絶縁基板と、前記絶縁基
板の両面にそれぞれ形成される配線パターンおよび凹部
領域と、前記凹部領域内にワイヤーループの上縁が絶縁
基板の表面を超えない深さに収納され前記配線パターン
とそれぞれワイヤΦボンディングされる半導体チップと
を含む。The hybrid integrated circuit device of the present invention includes an insulating substrate, a wiring pattern and a recessed region formed on both sides of the insulating substrate, and a depth within the recessed region such that the upper edge of the wire loop does not exceed the surface of the insulating substrate. A semiconductor chip is housed in the wiring pattern and is wire-bonded to the wiring pattern.

すなわち、本発明によれば、絶縁基板の両面には深い凸
部領域が設けられ、この凹部領域内にワイヤ・ループの
上縁が隠れるようにワイヤ・ボンディングされた半導体
チップが収納される。That is, according to the present invention, deep convex regions are provided on both sides of the insulating substrate, and the wire-bonded semiconductor chip is housed in the concave regions so that the upper edges of the wire loops are hidden.

この場合、配線パターンを凹部領域の底面にまで延ばし
半導体チップがこの配線パターンと凹部領域内でワイヤ
・ボンディングされるようにしてもよいし、或いは半導
体チップを少し浅く収納してボンディング・ワイヤのス
ティッチ側が凹部縁端上で配線パターンとワイヤ・ボン
ディングされるようにしてもよい。In this case, the wiring pattern may be extended to the bottom of the recessed area and the semiconductor chip may be wire-bonded to this wiring pattern within the recessed area, or the semiconductor chip may be retracted slightly shallowly and the bonding wires may be stitched. The sides may be wire bonded to the wiring pattern on the edges of the recess.

この構造をとらせる場合には裏面のボンディング作業を
行う際、既にボンディングが完了した他面のボンディン
グ接続面をボリミイド樹脂などの可撓性物質で保護する
必要が生じるが、凹部領域の横幅を狭くすることができ
るので、実装密度をより一層向上せしめ得る。If this structure is used, when performing bonding work on the back side, it is necessary to protect the bonding connection surface on the other side, which has already been bonded, with a flexible material such as bolimide resin, but the width of the recessed area must be narrowed. Therefore, the packaging density can be further improved.

〔実施例〕〔Example〕

以下図面を参照して本発明の詳細な説明する。 The present invention will be described in detail below with reference to the drawings.

第１図は本発明の一実施例を示す断面構造図である。本
実施例によれば、本発明の混成集積回路装置は、セラミ
ック絶縁基板１と、絶縁基板１の両面にそれぞれ形成さ
れた凹部領域２およびこの凹部領域２の底面にまで延び
る配線パターン３と凹部領域２内に隠れるように収納さ
れた半導体チップ４およびボンディング・ワイヤ５のル
ープと、半導体チップ４およびボンディング・ワイヤ５
を被覆する保護樹脂膜６と、コンデンサ素子７および抵
抗素子８とを含む。ここで、９は固定用半田材である。FIG. 1 is a cross-sectional structural diagram showing one embodiment of the present invention. According to this embodiment, the hybrid integrated circuit device of the present invention includes a ceramic insulating substrate 1, a recessed region 2 formed on both sides of the insulating substrate 1, a wiring pattern 3 extending to the bottom of the recessed region 2, and a recessed portion. A loop of the semiconductor chip 4 and the bonding wire 5 housed so as to be hidden in the region 2, and a loop of the semiconductor chip 4 and the bonding wire 5
, a capacitor element 7 and a resistor element 8 . Here, 9 is a fixing solder material.

この組立はつぎのように行われる。まず、絶縁基板１の
凹部領域２内に半導体チップ４を固定し、金線またはア
ルミ線のワイヤ５でボンディングを行い、ついで基板１
を裏返しにしてこの凹部領域２内に半導体チップ４を同
様に固定し通常手段によるボンディングが行われる。つ
ぎに半導体チップ４およびワイヤ５の保護のために、保
護用樹脂膜６を塗布し、さらにコンデンサ素子７および
抵抗素子８をそれぞれ搭載して半田材９で固定すればよ
い。すなわち、全く通常のボンディング技術によって組
立てることができる。この際、必要があれば、クリップ
端子または全体に外装保護樹脂を施してもよい。This assembly is performed as follows. First, the semiconductor chip 4 is fixed in the recessed area 2 of the insulating substrate 1, and bonding is performed with a gold wire or aluminum wire 5.
The semiconductor chip 4 is similarly fixed within this concave region 2 by turning it over, and bonding is performed by conventional means. Next, in order to protect the semiconductor chip 4 and the wires 5, a protective resin film 6 is applied, and a capacitor element 7 and a resistor element 8 are respectively mounted and fixed with a solder material 9. That is, it can be assembled using completely conventional bonding techniques. At this time, if necessary, an exterior protective resin may be applied to the clip terminal or the whole.

第２図は本発明の他の実施例を示す断面構造図で、第１
図と同一符号で表わしたものでおる。FIG. 2 is a cross-sectional structural diagram showing another embodiment of the present invention.
They are indicated by the same symbols as in the figure.

本実施例では、半導体チップ４は凹部領域２の縁端上で
配線パターン３とワイヤ寺ボンディングされる。すなわ
ち、従来性われていたと同じようにボンディング・ワイ
ヤ５は基板１上でボンディングされる。但しこの場合で
もワイヤ・ループの上縁が基板１の表面を超えないよう
に注意する。In this embodiment, the semiconductor chip 4 is wire-bonded to the wiring pattern 3 on the edge of the recessed region 2. That is, the bonding wire 5 is bonded on the substrate 1 in the same manner as conventionally done. However, even in this case, care must be taken to ensure that the upper edge of the wire loop does not exceed the surface of the substrate 1.

また、裏返しのボンディング作業を行う際には、既にボ
ンディングが完了した他面のボンディング接続面をポリ
ミイド系樹脂の如き可撓性被膜で保護する必要があるが
、凹部領域２が小形化できるので、高密度実装はより一
層促進される。Furthermore, when performing reverse bonding work, it is necessary to protect the other bonding connection surface on which bonding has already been completed with a flexible coating such as polyimide resin, but since the recessed region 2 can be made smaller, High-density packaging will be further promoted.

〔発明の効果〕〔Effect of the invention〕

以上、詳細に説明したように、本発明によれば、絶縁基
板の両面に半導体素子を通常のワイヤ・ボンディング技
術で搭載することができるので混成集積回路装置の高密
度実装に顕著なる効果を奏し得る。As described in detail above, according to the present invention, semiconductor elements can be mounted on both sides of an insulating substrate using ordinary wire bonding technology, which is extremely effective in high-density packaging of hybrid integrated circuit devices. obtain.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例を示す断面構造図、第２図は
本発明の他の実施例を示す断面構造図である。 １・・・・・・絶縁基板（セラミック）、２・・・・・
・凹部領域、３・・・・・・配線パターン、４・・・・
・・半導体チップ、５・・・・・・ボンディング・ワイ
ヤ、６・・・・・・保護樹脂膜、７・・・・・・コンデ
ンサ素子、８・・・・・・抵抗素子、９・・・・・・固
定用半田材。 代理人　弁理士　　内　原　　　晋、　　；△第７図FIG. 1 is a cross-sectional structural diagram showing one embodiment of the present invention, and FIG. 2 is a cross-sectional structural diagram showing another embodiment of the present invention. 1...Insulating substrate (ceramic), 2...
・Concave area, 3...Wiring pattern, 4...
... Semiconductor chip, 5 ... Bonding wire, 6 ... Protective resin film, 7 ... Capacitor element, 8 ... Resistance element, 9 ... ...Fixing solder material. Agent: Susumu Uchihara, patent attorney; △Figure 7

Claims (3)

【特許請求の範囲】[Claims] （１）絶縁基板と、前記絶縁基板の両面にそれぞれ形成
される配線パターンおよび凹部領域と、前記凹部領域内
にワイヤ・ループの上縁が絶縁基板の表面を超えない深
さに収納され前記配線パターンとそれぞれワイヤ・ボン
ディングされる半導体チップとを含むことを特徴とする
混成集積回路装置。(1) an insulating substrate, a wiring pattern and a recessed region formed on both sides of the insulating substrate, and a wire loop housed in the recessed region at a depth such that the upper edge of the wire loop does not exceed the surface of the insulating substrate; A hybrid integrated circuit device comprising a pattern and a semiconductor chip each wire-bonded. （２）前記配線パターンが凹部領域の底面にまで延びて
形成され前記半導体チップが凹部領域内でワイヤ・ボン
ディングされることを特徴とする特許請求の範囲第（１
）項記載の混成集積回路装置。(2) The wiring pattern is formed to extend to the bottom surface of the recessed region, and the semiconductor chip is wire-bonded within the recessed region.
) The hybrid integrated circuit device described in item 2. （３）前記半導体チップのボンディング・ワイヤのステ
ィッチ側が凹部縁端上で配線パターンとワイヤ・ボンデ
ィングされることを特徴とする特許請求の範囲第（１）
項記載の混成集積回路装置。(3) Claim (1) characterized in that the stitch side of the bonding wire of the semiconductor chip is wire-bonded to the wiring pattern on the edge of the recess.
The hybrid integrated circuit device described in Section 1.
JP61136682A 1986-06-11 1986-06-11 Hybrid integrated circuit device Pending JPS62291128A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61136682A JPS62291128A (en) 1986-06-11 1986-06-11 Hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61136682A JPS62291128A (en) 1986-06-11 1986-06-11 Hybrid integrated circuit device

Publications (1)

Publication Number Publication Date
JPS62291128A true JPS62291128A (en) 1987-12-17

Family

ID=15181008

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61136682A Pending JPS62291128A (en) 1986-06-11 1986-06-11 Hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPS62291128A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5811880A (en) * 1996-03-28 1998-09-22 Intel Corporation Design for mounting discrete components inside an integrated circuit package for frequency governing of microprocessors
WO2004032223A1 (en) * 2002-09-30 2004-04-15 Renesas Technology Corp. Semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5379464A (en) * 1976-12-24 1978-07-13 Nitto Electric Ind Co Method of producing circuit
JPS60245291A (en) * 1984-05-21 1985-12-05 沖電気工業株式会社 Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5379464A (en) * 1976-12-24 1978-07-13 Nitto Electric Ind Co Method of producing circuit
JPS60245291A (en) * 1984-05-21 1985-12-05 沖電気工業株式会社 Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5811880A (en) * 1996-03-28 1998-09-22 Intel Corporation Design for mounting discrete components inside an integrated circuit package for frequency governing of microprocessors
WO2004032223A1 (en) * 2002-09-30 2004-04-15 Renesas Technology Corp. Semiconductor device

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