JPH02150042A - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JPH02150042A JPH02150042A JP63303607A JP30360788A JPH02150042A JP H02150042 A JPH02150042 A JP H02150042A JP 63303607 A JP63303607 A JP 63303607A JP 30360788 A JP30360788 A JP 30360788A JP H02150042 A JPH02150042 A JP H02150042A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- substrate
- circuit
- film
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 239000004020 conductor Substances 0.000 claims abstract description 16
- 239000000463 material Substances 0.000 claims abstract description 16
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 230000001681 protective effect Effects 0.000 abstract description 14
- 238000007747 plating Methods 0.000 abstract description 10
- 230000002093 peripheral effect Effects 0.000 abstract 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 12
- 229910052802 copper Inorganic materials 0.000 description 11
- 239000010949 copper Substances 0.000 description 11
- 239000012528 membrane Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 239000011347 resin Substances 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 3
- 239000000155 melt Substances 0.000 description 3
- 239000008188 pellet Substances 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 230000003014 reinforcing effect Effects 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000035939 shock Effects 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 235000017166 Bambusa arundinacea Nutrition 0.000 description 1
- 235000017491 Bambusa tulda Nutrition 0.000 description 1
- 241001330002 Bambuseae Species 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 235000015334 Phyllostachys viridis Nutrition 0.000 description 1
- 239000011425 bamboo Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 229910052878 cordierite Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- JSKIRARMQDRGJZ-UHFFFAOYSA-N dimagnesium dioxido-bis[(1-oxido-3-oxo-2,4,6,8,9-pentaoxa-1,3-disila-5,7-dialuminabicyclo[3.3.1]nonan-7-yl)oxy]silane Chemical compound [Mg++].[Mg++].[O-][Si]([O-])(O[Al]1O[Al]2O[Si](=O)O[Si]([O-])(O1)O2)O[Al]1O[Al]2O[Si](=O)O[Si]([O-])(O1)O2 JSKIRARMQDRGJZ-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000013035 low temperature curing Methods 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0094—Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は半導体素子及び受動部品が搭載される混成集積
回路に関し、特に、フリップチップを搭載するのに好適
の混成集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hybrid integrated circuit on which a semiconductor element and a passive component are mounted, and particularly to a hybrid integrated circuit suitable for mounting a flip chip.
［従来の技術］
従来、この種の混成集積回路は、第３図に示すように基
板１の片面又は両面に銀箔又はめっき銅を用いた膜回路
２が形成され、両面の回路２は基板に形成されたスルー
ホール３を介して電気的に接続されている。各回路２は
半田保護膜４により被覆されているが、部品の搭載電極
及び外部端子接・続用電極は半田保護膜４により被覆さ
れず、従って、銅が露出したままか、又は半田５のめっ
きが施されている。また、スルーホール３に形成された
銅膜２ａもめっき半田５ａにより覆われ、この半田５ａ
が基板両面、即ち、回路面にまで延出している。これに
よりスルーホールランド６が形成されている。[Prior Art] Conventionally, in this type of hybrid integrated circuit, as shown in FIG. 3, a film circuit 2 using silver foil or plated copper is formed on one or both sides of a substrate 1, and the circuit 2 on both sides is formed on the substrate. It is electrically connected via the formed through hole 3. Each circuit 2 is covered with a solder protective film 4, but the component mounting electrodes and external terminal connection/connection electrodes are not covered with the solder protective film 4, so the copper remains exposed or the solder 5 Plated. Further, the copper film 2a formed in the through hole 3 is also covered with the plated solder 5a, and this solder 5a
extends to both sides of the board, that is, to the circuit surface. Through-hole lands 6 are thereby formed.
従来の混成集積回路においては、基板１がガラスエポキ
シ樹脂等によりつくられており、このガラスエポキシ樹
脂が膜回路２又は銅膜２ａを構成する銅より熱膨張係数
が大きいので、基板の厚さ方向の熱膨張に起因して接続
不良を起こす可能性が高い、そこで、スルーホール３の
内面の銅膜２ａに対し、半田５ａをめっきしてスルーホ
ールランド６を形成することにより、スルーホール３の
内面の導体部分を厚くし、熱膨張に対する信頼性を向上
させている。In conventional hybrid integrated circuits, the substrate 1 is made of glass epoxy resin or the like, and since this glass epoxy resin has a larger coefficient of thermal expansion than the copper constituting the membrane circuit 2 or the copper film 2a, Therefore, by plating the copper film 2a on the inner surface of the through hole 3 with solder 5a to form a through hole land 6, the through hole 3 is The inner conductor part is made thicker to improve reliability against thermal expansion.
上述した従来の混成集積回路にフリップチップを搭載す
る場合は、第４図に示すように、半田保護膜４に開口し
たフリップチップ搭載部の孔４ａに予め半田５ｂを充填
しておき、ＬＳＩのベレットであるフリップチップ７を
搭載した後にこの半田５ｂを加熱してフリップチップ７
の半田バンブ９と溶融接合させる。この充填用の半田５
ｂはめっきで形成するのが一般的であり、工程上、スル
ーホールランド６の半田５ａのめっき処理と同時に行わ
れることが多い。また、ベレット７と半田保護膜４との
間は充填樹脂１１により充填されている。When mounting a flip chip on the above-mentioned conventional hybrid integrated circuit, as shown in FIG. After mounting the flip chip 7, which is a pellet, this solder 5b is heated to make the flip chip 7
The solder bumps 9 are melt-bonded. This solder for filling 5
b is generally formed by plating, and is often performed at the same time as the plating of the solder 5a of the through-hole land 6 due to the process. Further, the space between the pellet 7 and the solder protection film 4 is filled with a filling resin 11.
ところで、フリップチップ７を基板１に搭載する場合、
基板１とフリップチップ７との間の間隙８は約１００μ
ｍにするのが一般的である。この間隙８を広げるために
は、半田バンブ９の体積（換言すれば直径）を大きくす
る必要があるので、半田パン１間のショート防止のため
にＬＳＩのパッド間隔を広くする必要が生じる。このた
め、前記間隔を大きくすることは、実用上好ましくない
。By the way, when mounting the flip chip 7 on the substrate 1,
The gap 8 between the substrate 1 and the flip chip 7 is approximately 100μ
It is common to set it to m. In order to widen this gap 8, it is necessary to increase the volume (in other words, the diameter) of the solder bump 9, and therefore, to prevent short circuits between the solder pans 1, it is necessary to widen the pad spacing of the LSI. For this reason, it is practically undesirable to increase the distance.
また、間隙を小さくすると、基板１とフリップチップ７
との間に充填できる樹脂１１の層厚が薄くなるので、基
板１からのα線１０を充分に遮蔽できなくなり、α線対
策を必要とする半導体素子には不利なことになる。Also, if the gap is made smaller, the substrate 1 and the flip chip 7
Since the layer thickness of the resin 11 that can be filled between the substrate 1 and the substrate 1 becomes thinner, the alpha rays 10 from the substrate 1 cannot be sufficiently shielded, which is disadvantageous for semiconductor devices that require countermeasures against alpha rays.
［発明が解決しようとする課題〕
しかしながら、従来の混成集積回路においては、基板１
に設けられたスルーホールランド６の幅は３００μｍ以
上とするのが一般的であり、フリップチップ接続部と比
較してめっき面積が著しく異なる。従って、めっき工程
において形成されためっき層の厚さはスルーホールラン
ド６と孔４ａとで同じであるが、半田溶融時の表面張力
で盛り上がったスルーホールランド６の半田５ａの高さ
が、半田バンブ９より高くなることがある。もし、フリ
ップチップ搭載領域の中にスルーホールランド６が配置
された場合、半田溶融時に盛り上がったスルーホールラ
ンド６の半田５ａがフリップチップ７を持ち上げるか、
又はフリップチップ７と基板１の間に広がって半田パン
１９間をショートさせることになる。従って、スルーホ
ール６はフリップチップ搭載領域から離して配置する必
要があり、これにより従来の混成集積回路では基板の配
線密度及び部品の実装密度が制限されるという欠点があ
る。[Problem to be solved by the invention] However, in the conventional hybrid integrated circuit, the substrate 1
Generally, the width of the through-hole land 6 provided in the through-hole land 6 is 300 μm or more, and the plating area is significantly different from that of a flip-chip connection. Therefore, the thickness of the plating layer formed in the plating process is the same on the through-hole land 6 and the hole 4a, but the height of the solder 5a on the through-hole land 6, which swells due to the surface tension during solder melting, is It may be higher than Bamboo 9. If the through-hole land 6 is placed in the flip-chip mounting area, the solder 5a of the through-hole land 6 that bulges when the solder melts will lift the flip chip 7, or
Alternatively, it may spread between the flip chip 7 and the substrate 1, causing a short circuit between the solder pans 19. Therefore, the through hole 6 needs to be placed away from the flip chip mounting area, which has the disadvantage that the conventional hybrid integrated circuit has a limitation in the wiring density of the board and the mounting density of components.
本発明はかかる問題点に鑑みてなされたものであって、
フリップチップ等のチップ搭載領域にもスルーホールを
配置することができ、回路の配線密度及び実装密度を向
上させることができる混成集積回路を提供することを目
的とする。The present invention has been made in view of such problems, and includes:
An object of the present invention is to provide a hybrid integrated circuit in which through-holes can be arranged even in a chip mounting area such as a flip chip, and the wiring density and packaging density of the circuit can be improved.
［課題を解決するための手段］
本発明に係る混成集積回路は、所定の導体配線材料より
熱膨張係数が小さい基板と、この基板の表面及び裏面で
構成される回路面に前記導体配線材料によりパターン形
成された膜回路と、前記基板に形成されたスルーホール
の内面に前記導体配線材料により形成され基板の表裏両
面の膜回路を電気的に接続する導体膜と、所定の電極形
成領域を除く前記基板の回路面に前記膜回路を被覆して
形成された保護膜と、前記電極形成領域及び前記スルー
ホールの内面にて夫々前記膜回路及び前記導体膜上にめ
っきされた半田層とを有することを特徴とする。[Means for Solving the Problems] A hybrid integrated circuit according to the present invention includes a substrate having a coefficient of thermal expansion smaller than that of a predetermined conductor wiring material, and a circuit surface composed of the front and back surfaces of this substrate using the conductor wiring material. Excluding the patterned film circuit, a conductor film formed of the conductor wiring material on the inner surface of the through hole formed in the substrate and electrically connecting the film circuits on both the front and back sides of the board, and a predetermined electrode formation area. A protective film is formed on the circuit surface of the substrate to cover the membrane circuit, and a solder layer is plated on the membrane circuit and the conductor film in the electrode formation region and the inner surface of the through hole, respectively. It is characterized by
［作用］
本発明においては、基板表裏面の回路面に形成される膜
回路及びスルーホール内面に形成される導体膜の構成材
料である導体配線材料よりも熱膨張係数が小さい材料で
基板を形成している。このため、従来のように基板の厚
さ方向の熱膨張に起因して接続不良が発生するという不
都合が解消される。従って、基板表裏面の膜回路を被覆
する保護膜を、電極形成領域を除く基板表裏面の回路面
の全体を覆うように、即ち保護膜がスルーホールの縁部
に至るように形成して、スルーホール部のめっき半田層
を基板表裏面の回路面まで延在しないようにすることが
できる。[Function] In the present invention, the substrate is formed of a material having a smaller coefficient of thermal expansion than the conductor wiring material that is the constituent material of the film circuit formed on the circuit surfaces of the front and back surfaces of the substrate and the conductor film formed on the inner surface of the through hole. are doing. Therefore, the conventional problem of connection failure caused by thermal expansion in the thickness direction of the substrate is eliminated. Therefore, a protective film covering the membrane circuits on the front and back surfaces of the substrate is formed so as to cover the entire circuit surface on the front and back surfaces of the substrate except for the electrode formation area, that is, the protective film extends to the edge of the through hole. The plated solder layer in the through-hole portion can be prevented from extending to the circuit surfaces on the front and back surfaces of the board.
これにより、チップ搭載時に、スルーホールのめっき半
田層が溶融して膜形成面上に盛り上がり、搭載されたフ
リップチップ等を持ち上げてしまうという事態が解消さ
れる。This eliminates the situation in which the plated solder layer of the through hole melts and bulges on the film formation surface during chip mounting, lifting the mounted flip chip or the like.
従って、熱衝撃に対するスルーホール部の配線接続信頼
性を確保しつつ、混成集積回路の配線密度を高めること
かできる。Therefore, the wiring density of the hybrid integrated circuit can be increased while ensuring the wiring connection reliability of the through-hole portion against thermal shock.
［実施例］
次に、本発明の実施例について添付の図面を参照して説
明する。[Example] Next, an example of the present invention will be described with reference to the accompanying drawings.
第１図は、本発明の第１の実施例に係る混成集積回路を
示す縦断面図である。基板１２はコージェライト多孔体
にエポキシ樹脂を含浸させ、熱膨張係数をシリコンと略
々同じにしたものである。FIG. 1 is a longitudinal sectional view showing a hybrid integrated circuit according to a first embodiment of the present invention. The substrate 12 is made of a cordierite porous body impregnated with an epoxy resin and has a coefficient of thermal expansion approximately the same as that of silicon.
この基板の表面及び裏面には補強層１３が貼付されてお
り、この補強層１３上に更に厚さが１０μｍの銀箔を貼
付し、ドリルを用いて直径が例えば０．５ｍｍのスルー
ホール３を穿設した後、スルーホール３内及び前記銅箔
上に１５μｍの厚さのめっき銅を電着させる。そして、
公知のフォトエツチング法により前記めっき銅をエツチ
ングすることにより、基板１２の表面及び裏面には膜回
路２がパターン形成され、またスルーホール３内面には
銅膜２ａが形成されている。その後、基板１２の表面及
び裏面にエポキシ系感光性の半田保護膜１４を５０μｍ
の厚さで印刷し、フォトエツチング法によりフリップチ
ップ搭載部１５及び部品搭載部１６の半田保護膜１４を
局部的に除去することにより、スルーホール３の周縁に
まで延在する半田保護膜１４を基板１２の表面及び裏面
上に形成する。そして、この半田保護膜１４が除去され
た部分のフリップチップ搭載部１５及び部品搭載部１６
並びに外部端子接続部（図示せず）及びスルーホール３
内面の銅膜２ａ上に半田（Ｓｎ６０Ｐｂ４０）を約６０
μｍの厚さにめっきすることによりめっき半田層２１が
形成されている。A reinforcing layer 13 is pasted on the front and back surfaces of this substrate, and a silver foil with a thickness of 10 μm is further pasted on this reinforcing layer 13, and a through hole 3 with a diameter of, for example, 0.5 mm is drilled using a drill. After that, plated copper with a thickness of 15 μm is electrodeposited inside the through hole 3 and on the copper foil. and,
By etching the plated copper using a known photoetching method, film circuits 2 are patterned on the front and back surfaces of the substrate 12, and a copper film 2a is formed on the inner surface of the through hole 3. After that, a 50 μm thick epoxy photosensitive solder protective film 14 is applied to the front and back surfaces of the substrate 12.
The solder protective film 14 extending to the periphery of the through hole 3 is printed to a thickness of It is formed on the front and back surfaces of the substrate 12. Then, the flip chip mounting portion 15 and the component mounting portion 16 are located in the portion where the solder protective film 14 is removed.
and external terminal connection part (not shown) and through hole 3
Approximately 60% of solder (Sn60Pb40) is applied on the inner copper film 2a.
A plated solder layer 21 is formed by plating to a thickness of μm.
このように各層を形成した後、最後に基板を分割するこ
とにより、混成集積回路が作製される。After forming each layer in this manner, the substrate is finally divided to produce a hybrid integrated circuit.
そして、フリップチップ７及びチップ型部品１７を搭載
接続し、ペレットと基板との間に樹脂１１を充填する。Then, the flip chip 7 and the chip type component 17 are mounted and connected, and the resin 11 is filled between the pellet and the substrate.
上述の如く構成された混成集積回路においては、基板１
２の表面及び裏面が、膜回路２の形成領域からスルーホ
ール３の周縁に至る領域にて保護膜１４により被覆され
ている。このため、スルーホール３内のめっき半田層２
１が基板１２の回路面まで延在していないので、チップ
搭載時に半田層２１が溶融して搭載チップを押し上げて
しまう等の事態は発生しない。このため、フリップチッ
プ搭載領域内にスルーホール３を配置して配線密度及び
実装密度を高めることができる。In the hybrid integrated circuit configured as described above, the substrate 1
The front and back surfaces of 2 are covered with a protective film 14 in a region from the region where the membrane circuit 2 is formed to the periphery of the through hole 3 . Therefore, the plated solder layer 2 inside the through hole 3
Since the solder layer 21 does not extend to the circuit surface of the substrate 12, a situation such as the solder layer 21 melting and pushing up the mounted chip does not occur when the chip is mounted. Therefore, by arranging the through holes 3 within the flip chip mounting area, wiring density and packaging density can be increased.
第２図は、本発明の第２の実施例を示す縦断面図である
。符号１８は、アルミナセラミック基板であり、スルー
ホール３はグリーンシートのときにパンチングで穿孔さ
れたものである。この基板１８にスルーホール３を含め
て銅及びクロムを積層めっきし、公知のフォトエツチン
グ法により、前記積層めっき層をエツチングすることに
より膜回路２をパターン形成する。これに、２５０℃で
最終硬化できる低温硬化型感光性ポリイミドを塗布して
半田保護膜１９とする。公知のフォトエツチング法でフ
リップチップ搭載部２０、部品搭載部及び端子部等のポ
リイミド半田保護膜１つを除去した後、残存する半田保
護膜１９を２５０’Ｃに加熱して硬化させる。次に、ク
ロム膜をエツチング除去して除去した電極上及びスルー
ホール内面に半田層（Ｓ ｎｌ、）Ｐ ｂ９ｏ） ２２
をめっきする。FIG. 2 is a longitudinal sectional view showing a second embodiment of the invention. Reference numeral 18 denotes an alumina ceramic substrate, and the through holes 3 are punched in the green sheet. This substrate 18, including the through holes 3, is laminated with copper and chromium plated, and the laminated plating layer is etched using a known photoetching method to form a pattern of the film circuit 2. A low-temperature curing type photosensitive polyimide which can be finally cured at 250° C. is coated on this to form the solder protective film 19. After removing one polyimide solder protective film from the flip chip mounting area 20, component mounting area, terminal area, etc. by a known photoetching method, the remaining solder protective film 19 is heated to 250'C and hardened. Next, a solder layer (Snl, )Pb9o) 22 is placed on the removed electrode and the inner surface of the through hole by etching the chromium film.
Plate.
この実施例では、基板１８及び半田保護膜１９の耐熱性
が高いので、５ｎｌＯｐｂ９０のように３゜０℃の高温
で融解する高温半田バンプを適用できるという利点があ
る。In this embodiment, since the substrate 18 and the solder protection film 19 have high heat resistance, there is an advantage that a high temperature solder bump that melts at a high temperature of 3.degree. 0.degree. C., such as 5nlOpb90, can be applied.
［発明の効果コ
以上説明したように、本発明は導体配線材料より熱膨張
係数が小さい基板に、この導体配線材料により膜回路を
形成し、スルーホールの導体膜を被覆するめっき半田層
が回路面内に延在しないように構成することにより、熱
衝撃に対するスルーホール部の配線接続信頼性を確保す
ると共に、フリップチップ等を搭載する混成集積回路の
配線密度及び部品実装密度を高めることができる。[Effects of the Invention] As explained above, the present invention forms a film circuit using a conductor wiring material on a substrate whose coefficient of thermal expansion is smaller than that of the conductor wiring material, and the plated solder layer covering the conductor film of the through hole forms the circuit. By configuring it so that it does not extend in-plane, it is possible to ensure the reliability of wiring connections in the through-hole section against thermal shock, and to increase the wiring density and component mounting density of hybrid integrated circuits equipped with flip chips, etc. .
ところで、フリップチップと基板との間の接続信頼性に
ついては、チップサイズ及び基板の熱膨張係数により異
なるが、チップと基板との間に接続補強用樹脂を充填す
ることにより、この接続信頼性を確保できることが知ら
れている。従って、本発明により、フリップチップを信
頼性良く、高密度で実装できる混成集積回路を提供でき
る。By the way, the connection reliability between the flip chip and the board varies depending on the chip size and the coefficient of thermal expansion of the board, but this connection reliability can be improved by filling a connection reinforcing resin between the chip and the board. It is known that it can be secured. Therefore, according to the present invention, it is possible to provide a hybrid integrated circuit in which flip chips can be mounted with high reliability and high density.
第１図は本発明の第１の実施例を示す断面図、第２図は
本発明の第２の実施例を示す断面図、第３図及び第４図
は従来の混成集積回路を示す断面図である。
１．１２，１８；基板、２；膜回路、３；スルーホール
、４，１４，１９．半田保護膜、５；半田、６；スルー
ホールランド、７；フリップチップ、９：半田バンプ、
１１；充填樹脂、１３；補強層、１５．２０．フリップ
チップ搭載部、１６；電気部品搭載部、１７；チップ型
電気部品、２１．２２；半田層FIG. 1 is a sectional view showing a first embodiment of the invention, FIG. 2 is a sectional view showing a second embodiment of the invention, and FIGS. 3 and 4 are sectional views showing a conventional hybrid integrated circuit. It is a diagram. 1.12, 18; Substrate, 2; Membrane circuit, 3; Through hole, 4, 14, 19. solder protective film, 5; solder, 6; through-hole land, 7; flip chip, 9: solder bump,
11; Filled resin, 13; Reinforcement layer, 15.20. Flip chip mounting section, 16; Electrical component mounting section, 17; Chip type electrical component, 21.22; Solder layer
Claims (1)
と、この基板の表面及び裏面で構成される回路面に前記
導体配線材料によりパターン形成された膜回路と、前記
基板に形成されたスルーホールの内面に前記導体配線材
料により形成され基板の表裏両面の膜回路を電気的に接
続する導体膜と、所定の電極形成領域を除く前記基板の
回路面に前記膜回路を被覆して形成された保護膜と、前
記電極形成領域及び前記スルーホールの内面にて夫々前
記膜回路及び前記導体膜上にめっき形成された半田層と
を有することを特徴とする混成集積回路。(1) A substrate with a thermal expansion coefficient smaller than that of a predetermined conductive wiring material, a film circuit patterned with the conductive wiring material on the circuit surface consisting of the front and back surfaces of this substrate, and a through hole formed on the substrate. A conductive film is formed on the inner surface of the hole using the conductive wiring material and electrically connects the film circuits on both the front and back surfaces of the substrate, and the circuit surface of the board excluding a predetermined electrode formation area is covered with the film circuit. and a solder layer plated on the film circuit and the conductor film in the electrode formation region and the inner surface of the through hole, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63303607A JPH02150042A (en) | 1988-11-30 | 1988-11-30 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63303607A JPH02150042A (en) | 1988-11-30 | 1988-11-30 | Hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02150042A true JPH02150042A (en) | 1990-06-08 |
Family
ID=17923030
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63303607A Pending JPH02150042A (en) | 1988-11-30 | 1988-11-30 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02150042A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5478007A (en) * | 1993-04-14 | 1995-12-26 | Amkor Electronics, Inc. | Method for interconnection of integrated circuit chip and substrate |
| EP0693777A1 (en) * | 1994-07-21 | 1996-01-24 | STMicroelectronics S.A. | Injection moulded BGA-package |
| US5795818A (en) * | 1996-12-06 | 1998-08-18 | Amkor Technology, Inc. | Integrated circuit chip to substrate interconnection and method |
| CN1293793C (en) * | 2003-06-13 | 2007-01-03 | 威盛电子股份有限公司 | Line baseplate |
-
1988
- 1988-11-30 JP JP63303607A patent/JPH02150042A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5478007A (en) * | 1993-04-14 | 1995-12-26 | Amkor Electronics, Inc. | Method for interconnection of integrated circuit chip and substrate |
| EP0693777A1 (en) * | 1994-07-21 | 1996-01-24 | STMicroelectronics S.A. | Injection moulded BGA-package |
| US5841192A (en) * | 1994-07-21 | 1998-11-24 | Sgs-Thomson Microelectronics S.A. | Injection molded ball grid array casing |
| US5795818A (en) * | 1996-12-06 | 1998-08-18 | Amkor Technology, Inc. | Integrated circuit chip to substrate interconnection and method |
| US6163463A (en) * | 1996-12-06 | 2000-12-19 | Amkor Technology, Inc. | Integrated circuit chip to substrate interconnection |
| CN1293793C (en) * | 2003-06-13 | 2007-01-03 | 威盛电子股份有限公司 | Line baseplate |
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