JPH0722735A - Printed wiring board - Google Patents

Abstract

PURPOSE:To improve a bonding strength between an adhesive layer and a plated layer, to prevent insulation resistance from decreasing when a conductor pattern is made into a fine pattern, or to prevent a tombstone phenomenon from occurring when chip components are packaged. CONSTITUTION:Pad forming openings 4a and the like corresponding to a first and a second plating resist layers 4 and 5, respectively, are formed as wide as the first plating resist layer 4 close to an adhesive layer 2 to provide a bond strength between the adhesive layer 2 and a pad 6. Openings for wiring corresponding to respective first and second plating resist layers 4 and 5 are formed in such a way that the farther the plating resist layer is from the adhesive layer, the narrower the width of the plating resist layer becomes, to prevent insulation resistance from decreasing when the wiring is made into a fine pattern. The first plating resist layer 4 has an opening for land forming, the second plating resist layer 5 has an opening as if crossing from one opening for land forming to another, and the land is formed at the same height as the first plating resist layer 4 to prevent a tombstone phenomenon from occurring when chip components are packaged.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board having a conductor pattern formed by an additive method.

[0002]

2. Description of the Related Art In recent years, electronic devices have been downsized, improved in performance and multifunctional, and printed wiring boards used therein have been required to have high density and high reliability by fine patterns. There is.

Conventionally, as a method of forming a conductor circuit on a printed wiring board, a subtractive method in which a copper foil is laminated on an insulating substrate and then a conductor pattern is formed by photoetching has been widely used. According to this method, it is possible to form a conductor pattern having excellent adhesion to an insulating substrate, but so-called undercut occurs because the etching depth required when forming a pattern by etching is large. Therefore, there is a problem that it is difficult to obtain a highly accurate fine pattern and it is difficult to cope with high density. Therefore, as an alternative method to the subtractive method, a full additive method, in which a conductor pattern is formed only by electroless copper plating, is drawing attention.

In the conventional full-additive method, the adhesive layer formed on the surface of the substrate (base material) is roughened, and the nuclear catalyst necessary for the first deposition of electroless plating (copper) on the roughened adhesive layer ( (Palladium) is added. Next, a photo-curable plating resist is applied to the entire surface of the adhesive layer, and then exposure / development processing is performed to form a plating resist layer on a portion other than the portion where the conductor pattern is to be formed. Then, the substrate is immersed in a plating solution to form an electroless copper plating layer at a predetermined position.

[0005]

However, the conductor pattern formed by the above-mentioned full additive method has the following problems.

When a connection terminal (pad) for mounting a surface mounting component such as QFP is formed, there is a problem that peeling easily occurs when heat or external force is applied by soldering or the like when mounting the component. This is because in the full additive method, the roughened surface of the adhesive layer is filled with plating to obtain the adhesive force between the adhesive layer and the plated layer. With the roughening method of the adhesive layer, it is difficult to obtain sufficient adhesion strength at high temperature.

When the pitch of the conductor pattern is narrowed (for example, 100 μm) by fine patterning, there is a problem that the insulation resistance value is lowered. That is, the plating resist layer needs to play a role of ensuring insulation between conductor patterns independent of each other. However, a conductive catalyst nucleus (not shown) exists between the plating resist layer and the adhesive layer. Therefore, if the pitch of the conductor patterns is narrowed, the width of the plating resist layer, that is, the insulation distance is shortened, and the insulation resistance value is reduced.

When an electrode (land) for mounting a small chip component is formed, there is a problem that a soldering defect called a tombstone phenomenon in which a component rises when mounting a component using cream solder is likely to occur. is there.
That is, in the full additive method, the plating layer (conductor pattern) formed on the adhesive layer on the base material is lower than the plating resist layer. Therefore, the chip components mounted on the lands are placed on the plating resist layer existing between the lands. Therefore, when melting the cream solder in this state and mounting the chip parts,
If the hardening of the cream solder in each land varies, the chip component loses its balance, tilts toward the land having a lower height, and finally rises.

The present invention has been made in view of the above problems. An object of the present invention is to improve the adhesion strength between an adhesive layer and a plating layer and to form a fine conductor pattern by forming a plurality of plating resist layers. It is an object of the present invention to provide a printed wiring board capable of preventing a decrease in insulation resistance value when patterned or a tombstone phenomenon when mounting a chip component.

[0010]

In order to solve the above problems, the present invention is a printed wiring board in which a conductor pattern is formed by an additive method, in which a plurality of plating resist layers are formed and each of the plating resist layers is formed. The shape of the opening is different.

The corresponding openings of the plating resist layers may be formed wider as the plating resist layer closer to the adhesive layer is formed. Conversely, the openings of the plating resist layers corresponding to each other may be formed wider. The plating resist layer farther from the adhesive layer may be formed narrower. The plating resist layer has a two-layer structure, and the first plating resist layer laminated on the adhesive layer has a land forming opening for mounting a chip component, and is formed on the first plating resist layer. The laminated second plating resist layer may have an opening extending over both the land forming openings, and the plating layer may be formed at the same height as the first plating resist layer.

[0012]

When a plurality of plating resist layers are formed and the corresponding openings of the plating resist layers are formed wider as the plating resist layer is closer to the adhesive layer, the lower part of the plating layer formed on the adhesive layer is Wider than the top. Therefore,
The adhesion between the adhesive layer and the plating layer is improved.

If the openings corresponding to each other of the plating resist layers are formed so as to be narrower as the plating resist layer is farther from the adhesive layer, the plating resist layer formed on the adhesive layer has insulation between the plating layers. A wide shape that can be secured. Therefore, it is possible to prevent a decrease in insulation resistance value when the conductor pattern is formed into a fine pattern.

Further, the first plating resist layer has an opening for forming a land for mounting a chip component, and the second plating resist layer has an opening extending over both the openings for forming a land. Then, the plating layer can be formed at the same height as the first plating resist layer. Therefore,
The chip parts will be placed on the first plating resist layer and both plating layers (lands), and when mounting by soldering, even if the curing of the cream solder varies among the lands, it will tilt. The occurrence of the tombstone phenomenon is prevented.

[0015]

[Embodiment 1] Embodiment 1 in which the present invention is embodied in a printed wiring board on which a conductor pattern is formed by a full additive method will be described in detail with reference to the drawings. In this embodiment, the adhesion strength of a portion such as a pad for mounting a surface mounting component such as QFP, which requires a large adhesion strength with the base material, is increased.

As shown in FIG. 1, an adhesive layer 2 having a roughened surface is formed on an insulating substrate 1 which constitutes a printed wiring board P, and plating resists 3 are equally spaced on the adhesive layer 2. Are laminated. The plating resist 3 is laminated on the adhesive layer 2 and has a first plating resist layer 4 having a pad forming opening 4a and a first plating resist layer 4 having a pad forming opening 5a. It is composed of the second plating resist layer 5. The corresponding pad forming openings 4a and 5a of the first and second plating resist layers 4 and 5 are formed wider toward the adhesive layer 2. On the adhesive layer 2 in the pad forming openings 4a and 5a, a pad 6 forming a conductor pattern is formed.
Are formed. The pad 6 is formed such that its lower portion is wider than its upper portion and has a length and a width (150 μ) necessary for bonding with a lead of a QFP not shown. In this embodiment, the pad 6 has a pitch of 300 μ and a lower width of 250 μ. Further, the width of the first plating resist layer 4 is 15 μm, and the insulation between the adjacent pads 4 is secured.

The printed wiring board P having the above structure
, The pad forming openings 4a,
By forming the pad forming opening 4a close to the adhesive layer 2 in 5a, the lower portion of the pad 6 formed on the adhesive layer 2 becomes wider. Therefore, the area of the pad 6 formed on the adhesive layer 2 is increased and the adhesive layer 2
The adhesion strength between the pad 6 and the pad 6 can be improved. As a result, the pad 6 can obtain sufficient adhesion strength at high temperature when mounting a surface mounting component such as QFP.

Since both lower parts of the pad 6 are located below the second plating resist layer 5, the second plating resist layer 5 exerts a force against peeling of the pad 6. Thus, the peel strength of the pad 6 can be increased.

Further, since the upper surface of the first plating resist layer 4 is formed so as to be covered with the second plating resist layer 5, the portion exposed to the electroless copper plating solution when the pad 6 is formed. Less is. Therefore, the first plating resist layer 4 does not have to have excellent resistance to electroless copper plating solution (alkali resistance), and it is possible to use a material having excellent adhesive followability (adhesion) only. it can.

Next, an example of a method of manufacturing the printed wiring board P will be briefly described. An adhesive containing an epoxy resin as a main component is applied onto the insulating substrate 1 and cured, and the surface thereof is roughened by a conventional method, and then a catalyst nucleus such as palladium is provided. Next, a plating resist made of a photosensitive resin is applied to the entire surface of the adhesive layer 2, and then exposure / development processing is performed to form a first plating resist layer 4 having a pad forming opening 4a (FIG. 2). ).

Next, after a plating resist made of a photosensitive resin is applied on the first plating resist layer 4, exposure / development processing is performed to make the pad forming opening portion 4a narrower in width than the pad forming opening portion 4a. Second plating resist layer 5 having 5a
To form. (Figure 3). Then, electroless copper plating is performed to form pads (conductor patterns) 6 (FIG. 1). After that, a solder resist is applied to the surface of the second plating resist layer 5 and the wiring (not shown) of the conductor pattern, and then the outer shape finish or the like is performed to obtain the printed wiring board P.

[Second Embodiment] Next, a second embodiment will be described. In this embodiment, the insulation resistance value can be prevented from being lowered when the pitch of the wiring portions of the conductor pattern is narrowed.

As shown in FIG. 4, the corresponding wiring forming openings 4 of the first and second plating resist layers 4 and 5 are formed.
The widths b and 5b are formed so as to be farther from the adhesive layer 2. Adhesive layer 2 in wiring formation openings 4b and 5b
Wiring 7 forming a conductor pattern is formed on the top. The wiring 7 is formed such that its lower portion is narrower than its upper portion. In this embodiment, the wiring 7 has a pitch of 100 μ and an upper width of 70 μ. Further, the width of the first plating resist layer 4 is 10 μm, and the insulation between the adjacent wirings 7 is secured.

The printed wiring board P constructed as described above
In the above, since the wiring forming openings 4b and 5b are formed so as to become narrower as they are farther from the adhesive layer 2, the first plating resist layer 4 has a wide shape capable of ensuring insulation between the wirings 7. . Therefore, the insulation distance between the wirings 7 becomes long, and it is possible to prevent the insulation resistance value from decreasing when the wirings 7 are formed into a fine pattern.

The printed wiring board P of Example 1 can be obtained by the same manufacturing method as that of Example 1. [Third Embodiment] Next, a third embodiment will be described. In this embodiment, it is possible to prevent the tombstone phenomenon from occurring when the chip component is mounted.

As shown in FIG. 5, the first plating resist layer 4 is formed to be thicker than the second plating resist layer 5. The first plating resist layer 4 has a pair of land forming openings 4c for mounting chip parts, and the second plating resist layer 5 has an opening 5c that extends between both land forming openings 4c. have. On the adhesive layer 2 in the land forming opening 4c, a chip component mounting land 8 forming a conductor pattern is formed at the same height as the first plating resist layer 4. In this embodiment, the height of the first plating resist layer 4 and the land 8 is 25 μm.

In the above-mentioned printed wiring board P, the land 8 is formed at the same height as the first plating resist layer 4 by having the two-layer structure of the first and second plating resist layers 4 and 5. be able to. Therefore, the chip component (illustrated by the chain double-dashed line) 9 mounted on both lands 8 is placed on the first plating resist layer 4 and both lands 8. Therefore, when the chip component 9 is mounted by soldering, even if the curing of the cream solder (illustrated by the chain double-dashed line) 10 in each land 8 varies, the chip component does not tilt, and the tombstone phenomenon occurs. Can be prevented.

Further, since the chip component 9 is surrounded by the second plating resist 5 during mounting, the chip component 9 is less likely to protrude from the land 8. Also, cream solder 1
It is possible to prevent the extra protrusion of 0.

In the printed wiring board P according to the third embodiment, the first plating resist layer 4 is formed to have a large thickness, and the opening 5c of the second plating resist layer 5 extends across both land forming openings 4c. It is different from the manufacturing method of the first embodiment in that it is formed.

The present invention is not limited to the above embodiment, but may be modified as follows. (1) The plating resist 3 may have three or more layers.

(2) Each of the openings 4a to 4c of the first plating resist layer 4 constituting the plating resist having a two-layer structure,
The size of the width of each opening 5a to 5c of the second plating resist layer 5 may be changed as appropriate. Further, the thickness of the first or second plating resist layers 4 and 5 may be changed appropriately.

(3) For the first or second plating resist layers 4 and 5, for example, a thermosetting resin composition other than the photosensitive resin composition may be used. (4) It may be embodied when the additive is applied to a part of the manufacturing of the multilayer printed wiring board by the subtractive method.

(5) It may be applied when a conductor pattern is formed by electroless plating of a metal other than copper. (6) In the third embodiment, the opening 5c of the second plating resist may be formed to have the same width as the chip part. By doing so, the chip component can be reliably fixed on the land 8 in position.

(7) In the case of manufacturing the printed wiring board P, after forming the first plating resist layer, the plating layer is formed, then the second plating resist layer is formed, and then the plating layer is formed again. May be formed.

[0035]

As described above in detail, according to the printed wiring board of the present invention, the plating layer is formed by forming the openings corresponding to each other in the plating resist layer so as to be wider as the plating resist layer is closer to the adhesive layer. Since the lower part of the is wider than the upper part, it is possible to improve the adhesion strength between the adhesive layer and the plating layer.

Further, by forming openings corresponding to each other in each plating resist layer in the adhesive layer such that the farther the plating resist layer is from the adhesive layer, the plating resist layer formed on the adhesive layer has an insulating property between the plating layers. Since the width of the conductor pattern is wide, it is possible to prevent the insulation resistance value from decreasing when the conductor pattern is formed into a fine pattern.

Further, the plating resist layer has a two-layer structure,
The first plating resist layer laminated on the adhesive layer has an opening for land formation for chip component mounting, and the second plating resist layer has an opening extending over both openings for land formation. If so, the plating layer can be formed at the same height as the first plating resist layer, and the chip component is mounted on the first plating resist layer and both plating layers (lands) during mounting. Therefore, the excellent effect that the occurrence of the tombstone phenomenon can be prevented is achieved.

[Brief description of drawings]

FIG. 1 is a partial schematic view showing a printed wiring board of Example 1 of the present invention.

FIG. 2 is likewise a partial schematic view showing a state in which a first plating resist is formed on a substrate in a manufacturing process of a printed wiring board.

FIG. 3 is also a partial schematic view showing a state in which a second plating resist is formed on the substrate in the manufacturing process of the printed wiring board.

FIG. 4 is a partial schematic view showing a printed wiring board of Example 2.

FIG. 5 is a partial schematic view showing a printed wiring board of Example 3.

[Explanation of symbols]

1 ... Insulating substrate, 2 ... Adhesive layer, 3 ... Plating resist, 4
... first plating resist layer, 5 ... second plating resist layer, 4a, 5a ... pad forming opening, 4b, 5b ... wiring forming opening, 4c ... land forming opening, 5c ... opening, 6 ... Pads forming the conductor pattern, 7 ... Wiring forming the conductor pattern, 8 ... Lands for mounting chip parts forming the conductor pattern, P ... Printed wiring board.

Claims (4)

[Claims] 1. A printed wiring board on which a conductor pattern is formed by an additive method, wherein a plurality of layers of plating resist are formed and the openings of each plating resist layer have different shapes. Board. 2. The printed wiring board according to claim 1, wherein the openings corresponding to each other in each of the plating resist layers are formed wider as the plating resist layer is closer to the adhesive layer. 3. The printed wiring board according to claim 1, wherein the openings corresponding to each other of the plating resist layers are formed so that the width of the plating resist layer farther from the adhesive layer is narrower. 4. The first plating resist layer has a two-layer structure, and the first plating resist layer laminated on the adhesive layer has a land forming opening for mounting a chip component. The second plating resist layer laminated on the layer has an opening extending over both land forming openings, and the plating layer is formed at the same height as the first plating resist layer. The printed wiring board according to claim 1, wherein: