CN1293793C - Line baseplate - Google Patents
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- CN1293793C CN1293793C CNB03142340XA CN03142340A CN1293793C CN 1293793 C CN1293793 C CN 1293793C CN B03142340X A CNB03142340X A CN B03142340XA CN 03142340 A CN03142340 A CN 03142340A CN 1293793 C CN1293793 C CN 1293793C
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Abstract
The present invention provides a line baseplate which is made by using the method that a conductive wall and a conductive column are integrally formed, namely that the electric connection media among three to four conductive layers are once made and completed. Thus, under the condition of same wiring density, the line baseplate can increase the counter point margin between the conductive wall and the conductive column of the line baseplate, or under the condition of same wiring area, the line baseplate can enhance the wiring density. In addition, the technology of the line baseplate can reduce the number of the technological steps of the line baseplate so as to reduce making cost and the technology period of the line baseplate.
Description
Technical field
The relevant a kind of circuit base plate (circuit substrate) of the present invention, and relevant especially a kind of circuit base plate (circuit substrate) with high wiring density (high layout density) and low cost of manufacture.
Background technology
Flip-chip welding technology (Flip Chip Bonding Technology) mainly is the arrangement mode that utilizes face array (areaarray), a plurality of chip mats (die pad) are disposed at the active surface (activesurface) of chip (die), and form projection (bump) on each chip mat, then with chip turn-over (flip) afterwards, electricity (electrically) and machinery (mechanically) are connected to the surperficial pairing joint sheet (bonding pad) of carrier (carrier) respectively to utilize projection on the chip mat of chip.Because the flip-chip welding technology can be applicable to the chip-packaging structure of high pin number (High Pin Count), and have advantages such as the package area of dwindling and shortening signal transmission path, make the flip-chip welding technology be widely used in the Chip Packaging field at present.It should be noted that because circuit base plate can provide high density joint sheet and miniaturization circuit simultaneously, thus circuit base plate become the current chip encapsulation field the carrier used of modal flip-chip.
Please refer to Fig. 1, it illustrates the circuit base plate of existing a kind of four conductive layers by Layer increasing method (build-up process) made, the partial schematic diagram of its internal wiring structure.It should be noted that circuit base plate 100 only illustrates its current-carrying part, but not shown its dielectric part is in figure.Circuit base plate 100 comprises four layers of conductive layer 102 of patterning, i.e. conductive layer 102a, conductive layer 102b, conductive layer 102c and conductive layer 102d all dispose a dielectric layer (not shown) between the wantonly two adjacent conductive layers 102.In order to be electrically connected conductive layer 102b and conductive layer 102c, prior art is normally utilized the technology of plated-through-hole (platingthrough hole), and plated-through-hole (through via) 104 is formed between conductive layer 102b and the conductive layer 102c.In addition, in order to be electrically connected conductive layer 102a and conductive layer 102b, prior art normally utilizes conductive layer 102b to form air ring (ring pad) 106 respectively at the two ends of plated-through-hole 104, in order to allowing an end of via (conductive via) 108 can connect (falling) local surfaces to air ring 106, the other end of via 108 then is connected to by conductive layer 102a and the joint sheet (bonding pad) 110 that constituted.Similarly, also be to utilize above-mentioned vertical winding structure to be electrically connected between conductive layer 102c and the conductive layer 102d.Therefore, the joint sheet 110 of conductive layer 102a can reach top air ring 106 via top via 108 in regular turn and wind the line to conductive layer 102b.Then, again via plated-through-hole 104 and below air ring 106 and wind the line to conductive layer 102c.At last, more can be connected to the joint sheet 110 of conductive layer 102d, and wind the line to conductive layer 102d via following via 108.
Please equally with reference to figure 1, owing to utilize the made circuit base plate of Layer increasing method 100, must use the seizure pad (capture pad) of the bigger air ring 106 of external diameter, make an end of via 108 can be easy to be connected to exactly the local surfaces of air ring 106 as via 108.In addition, with regard to conductive layer 102b.For the phenomenon of preventing air ring 106 and the air ring 106 that is close to or contiguous lead 112 to be short-circuited, a dead ring (isolation ring) 114 must more be designed in the periphery of air ring 106.Yet, because the external diameter of air ring 106 must design greater than a preset value, and the dead ring 114 of the periphery of air ring 106 must exist, thereby cause the spacing of adjacent plated-through-hole 104 effectively to reduce, therefore, when top joint sheet 110 during directly as media circuit base plate 100 and that the inversed-chip lug (not shown) engages, density between these joint sheets 110 can't promote effectively, so existing circuit base plate 100 can't provide higher wiring density (layout density).In other words, the configuration of existing circuit base plate 100 slatterns many wiring space.In addition, because it is lower to utilize Layer increasing method to make the yield of circuit base plate 100 of high-density line (high-density circuit), just must utilize the cost of the made circuit base plate of Layer increasing method 100 higher relatively.
Summary of the invention
In view of this, purpose of the present invention is to provide a kind of circuit base plate exactly, in order to higher wiring density to be provided, so applicable to the Chip Packaging form of high integration (high integrated).
For realizing above-mentioned purpose of the present invention, the present invention proposes a kind of circuit base plate, and it comprises: a dielectric sandwich layer, has one first and corresponding one second, and the dielectric sandwich layer has more a perforation, and it runs through the dielectric sandwich layer, and connects first and second of dielectric sandwich layer; One conduction wall is disposed at the inner face of perforation; One dielectric post is disposed at the conduction cylindrical space that wall surrounded; One first conductive layer of patterning is disposed at first of dielectric sandwich layer; One conductive pole, the one end is connected in first conductive layer, and this conduction wall and this conductive pole are integrated structures; One dielectric layer covers first conductive layer, and is surrounded on the lateral margin of conductive pole; And one second conductive layer of patterning, be disposed on the dielectric layer, and be connected in the other end of conductive pole.
For realizing above-mentioned purpose of the present invention, the present invention also proposes a kind of circuit base plate, and it comprises: a conduction sandwich layer, has one first and corresponding one second, and the conduction sandwich layer has more a perforation, and it runs through the conduction sandwich layer, and connects first and second of conduction sandwich layer; One dielectric wall is disposed at the inner face of perforation; One conduction wall is disposed at the inner face of dielectric wall, and is positioned among the perforation; One dielectric post is disposed at the conduction cylindrical space that wall surrounded; At least one conductive pole, the local surfaces of one end are connected in first side of the contiguous conduction sandwich layer of conduction wall, and this conduction wall and this conductive pole are integrated structures; One dielectric layer is disposed at first of the conduction sandwich layer, and is surrounded on the lateral margin of conductive pole; And a conductive layer of patterning, be disposed on the dielectric layer, and conductive layer having a joint sheet, it is connected in the other end of conductive pole.
Based on above-mentioned, the present invention adopts the conduction wall and the integrated practice of conductive pole, promptly produces once and finishes three to four layers of electrical connection media between the conductive layer.Therefore, under identical wiring density, this circuit base plate can increase the conduction wall of circuit base plate and the contraposition nargin between the conductive pole, or under identical wiring area, this circuit base plate more can improve higher wiring density.In addition, the technology of this circuit base plate more can reduce the number of steps of the technology of circuit base plate, and then reduces the cost of manufacture and the process cycle of circuit base plate.
Description of drawings
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below, wherein:
Fig. 1 illustrates the circuit base plate of existing a kind of four conductive layers by the Layer increasing method made, the partial schematic diagram of its internal wiring structure;
Fig. 2 A～2I illustrates the section flow chart according to the circuit substrate process of the first embodiment of the present invention;
Fig. 3 illustrates the circuit base plate of four conductive layers of first embodiment, the partial schematic diagram of its internal wiring structure;
Fig. 4 A～4J illustrates the section flow chart according to the circuit substrate process of second embodiment of the invention;
Fig. 5 illustrates the circuit base plate of three conductive layers of second embodiment, the partial schematic diagram of its internal wiring structure; And
Fig. 6 A, 6B illustrate the circuit base plate of Fig. 5 respectively, the partial schematic diagram of the internal wiring structure of its two kinds of various wirings designs.
Embodiment
First embodiment
Please in regular turn with reference to figure 2A～2I, it illustrates the section flow chart according to the circuit substrate process of first embodiment of the invention.The first embodiment of the present invention is to be example with the circuit base plate of making four conductive layers.
Please refer to Fig. 2 A, one dielectric sandwich layer (dielectric core layer) 202, conductive layer 204 and conductive layer 206 are provided, wherein dielectric sandwich layer 202 has one first 202a and one second corresponding 202b, and conductive layer 204 is disposed at first 202a of dielectric sandwich layer 202, and another conductive layer 206 then is disposed at second 202b of dielectric sandwich layer 202.Therefore, the composition of dielectric sandwich layer 202, conductive layer 204 and conductive layer 206 can be considered general common double sided board, and the initiation layer that more begins as technology of the composition of dielectric sandwich layer 202, conductive layer 204 and conductive layer 206.
Please refer to Fig. 2 B, for example in the mode of machine drilling (mechanical drilling) or laser drill (1aserdrilling), form a plurality of perforations 208 on dielectric sandwich layer 202, conductive layer 204 and conductive layer 206, and these perforations 208 distribute all and run through dielectric sandwich layer 202, conductive layer 204 and conductive layer 206.
Please refer to Fig. 2 C, for example in the mode of photoetching (photolithography) and etching (etching), patterned conductive layer 204 and conductive layer 206 make that conductive layer 204 and the conductive layer 206 behind the patterning will form at least one joint sheet 205 and at least one joint sheet 207 separately.
Please refer to Fig. 2 D, electroplate the step of (electrical plating) in order to help the follow-up electricity that has, for example in the mode of electroless plating (being electroless-plating), form a plating seed layer (plating seedlayer) 210 in the surface that dielectric sandwich layer 202, conductive layer 204 and conductive layer 206 are exposed, wherein plating seed layer 210 more is formed at the inner face of these perforations 208 comprehensively.It should be noted that the thickness of the thickness of plating seed layer 210 much smaller than conductive layer 204 (or conductive layer 206).
Please refer to Fig. 2 E, the photoresist layer 212 that forms patterning is in the surface of conductive layer 204, and the photoresist layer 214 that forms patterning is in the surface of conductive layer 206, wherein photoresist layer 212 has a plurality of openings 216, in order to the local surfaces (surface that comprises joint sheet 205) that exposes conductive layer 204, promptly expose local plating seed layer 210, and photoresist layer 214 also has a plurality of openings 216, in order to the local surfaces (surface that comprises joint sheet 207) that exposes conductive layer 206, promptly expose local plating seed layer 210.In addition, the photoresist layer 212 of patterning and photoresist layer 214 have a plurality of openings 217 more respectively, and it also exposes local plating seed layer 210 respectively.It should be noted that, when photoresist layer 212 when utilizing exposure and step of developing to form opening 216, because when photoresist layer 212 is developed, still can remove the local photoresist layer 212 that has exposed, so when photoresist layer 212 is exposed, can in advance the exposure area be extended in the predeterminated position of opening 216 slightly, make follow-up when photoresist layer 212 is developed, can allow the final cross-sectional area of opening 216 less, and meet a preset value.
Please refer to Fig. 2 F, in the mode of electroplating, via plating seed layer 210, with the inner face of plated with conductive material in perforation 208, and form conduction wall 220, and the local surfaces (surface that comprises joint sheet 205) of the conductive layer 204 that simultaneously plated with conductive material is exposed in photoresist layer 212.Simultaneously, the local surfaces (surface that comprises joint sheet 207) of the conductive layer 206 that plated with conductive material is exposed in photoresist layer 214 more is in order to form a plurality of conductive poles 218 respectively.In addition, more simultaneously with plated with conductive material on the parcel plating Seed Layer 210 of a plurality of openings 217 of photoresist layer 212 and photoresist layer 214, and form a plurality of conductive poles 219.In addition, more visual actual needs, and plate barrier metal layer (barrier metal layer) (not shown) on the surface of conductive pole 218,219 are in order to the protection as the subsequent etch technology of conductive pole 218,219.
Please refer to Fig. 2 G, after forming these conductive poles 218 and conduction wall 220, then remove photoresist layer 212 and the photoresist layer 214 of Fig. 2 F, and expose plating seed layer 210, conductive layer 204 and conductive layer 206, and utilize the mode of fast-etching (flash etching), remove plating seed layer 210, be electrically connected to each other via plating seed layer 210 by conductive layer 204 or lead that conductive layer 206 was constituted avoiding.
Please refer to Fig. 2 H, dielectric material is inserted the cylindrical space that these conduction walls 220 are surrounded, in order to form a dielectric post 226 respectively, and can be when forming dielectric post 226, simultaneously dielectric layer 222 and dielectric layer 224 are formed at the two sides of dielectric sandwich layer 202 respectively, and be covered in the surface of conductive layer 204 and conductive layer 206 respectively, and respectively around the lateral margin of these conductive poles 218 and conductive pole 219.It should be noted that, when dielectric material in a single day residue in conductive pole 218 away from the end face of dielectric sandwich layer 202 time, can utilize the mode of grinding (polish) or plasma etching (plasma etching), remove residual dielectric material, and the surface of while planarization dielectric layer 222 (or dielectric layers 224), so will help follow-up processing step.
Please refer to Fig. 2 I, after forming dielectric layer 222, dielectric layer 224 and dielectric post 226, form the conductive layer 228 of patterning and conductive layer 230 more respectively on dielectric layer 222 and dielectric layer 224, wherein conductive layer 228 is more via joint sheet 232 that it constituted, and be connected in the end of conductive pole 218a, and conductive layer 230 is more via the joint sheet 234 that it constituted, and is connected in the end of conductive pole 218b indirectly.Therefore, the joint sheet 232 that is made of conductive layer 228 can be in regular turn via conductive pole 218a, conduction wall 220 and conductive pole 218b, and is electrically connected to the joint sheet 234 that conductive layer 230 is constituted.
Please refer to Fig. 3, it illustrates the circuit base plate of four conductive layers of first embodiment, the partial schematic diagram of its internal wiring structure.Circuit base plate 300 only illustrates its current-carrying part, but not shown its dielectric part is in figure.Circuit base plate 300 comprises four layers of conductive layer 302, be conductive layer 302a, conductive layer 302b, conductive layer 302c and conductive layer 302d, all dispose a dielectric layer (not shown) between the two adjacent conductive layers 302, wherein the joint sheet 308a of conductive layer 302a can be in regular turn via conductive pole 306a, joint sheet 307a, conduction wall 304, joint sheet 307b and conductive pole 306b, and be electrically connected on the joint sheet 308b of conductive layer 302d, and lead 310 is between two joint sheet 308a.
In order more clearly to compare circuit base plate and the difference of existing circuit base plate on wiring density of first embodiment, please refer to Fig. 1,3.At first, as shown in Figure 1, with regard to existing technology of making circuit base plate 100 with Layer increasing method, because the Production Time of plated-through-hole 104 is early than the Production Time of via 108, contraposition nargin when making via 108 in order to be provided at, the landing surface of via 108 can't directly be provided with the annular end face of plated-through-hole 104, make the two ends of plated-through-hole 104 must form air ring 106 extraly, so will increase the spacing of two adjacent plated-through-holes 104 relatively.Yet, as shown in Figure 3, during the technology of the circuit base plate 300 of first embodiment, because conduction wall 304 and conductive pole 306 (being conductive pole 306a and conductive pole 306b) are to complete simultaneously, make that the aligning accuracy between conduction wall 304 and the conductive pole 306 only involves the single photoresist layer 212 of Fig. 2 E and the aligning accuracy of photoresist layer 214.Therefore, the distance of two adjacent conductive walls 304 can reduce further, make the spacing of two bond pad adjacent 308 (particularly joint sheet 308a) to reduce further relatively.
With regard to the first embodiment of the present invention, compared to existing circuit base plate, first embodiment can provide the circuit base plate of high wiring density.In addition, compared to existing technology of making circuit base plate with Layer increasing method, first embodiment can reduce the number of steps of the technology of circuit base plate, thereby reduces the cost of manufacture and the process cycle of circuit base plate.
Second embodiment
First embodiment is with the initiation layer of double sided board (promptly the two sides of a dielectric sandwich layer disposes the structure of a conductive layer respectively) as technology.Yet second embodiment is with the initiation layer of conduction sandwich layer (conductive corelayer) as technology.
Please in regular turn with reference to figure 4A～4J, it illustrates the section flow chart according to the circuit substrate process of the second embodiment of the present invention.The second embodiment of the present invention is to be example with the circuit base plate of making three conductive layers.
Please refer to Fig. 4 A, a conduction sandwich layer 402 is provided, its material for example is the material of good conductivity, for example copper.Conduction sandwich layer 402 has one first 402a and one second corresponding 402b.
Please refer to Fig. 4 B,, form a plurality of perforations 404 on conduction sandwich layer 402, and these perforations 404 run through conduction sandwich layer 402 more respectively, and connect first 402a and second 402b of conduction sandwich layer 402 for example in the mode of photoetching etching or machine drilling.
Please refer to Fig. 4 C, insert dielectric material within these perforations 404, in order to forming these dielectric post 406, or insert in these perforations 404 these dielectric post that have been shaped 406 are corresponding respectively.Wherein, the both ends of the surface of these dielectric post 406 trim respectively in first 402a and second 402b of conduction sandwich layer 402, and the material of these dielectric post 406 for example is a resin (resin).
Please refer to Fig. 4 D, for example in the mode of machine drilling or laser drill, form another perforation 408 respectively on these dielectric post 406, similarly, these perforations 408 run through these dielectric post 406 respectively, and connect the both ends of the surface of these dielectric post 406.
Please refer to Fig. 4 E, in order to help the step of follow-up plating, for example in the mode of electroless plating (being electroless-plating), form a plating seed layer 410 in the surface that conduction sandwich layer 402 and dielectric post 406 are exposed comprehensively, wherein the thickness of plating seed layer 410 is considerably thin.
Please refer to Fig. 4 F, the photoresist layer 412 that forms patterning is in first 402a of conduction sandwich layer 402, wherein the photoresist layer 412 of patterning has a plurality of openings 416, in order to the local side (promptly exposing local plating seed layer 410) of the end that exposes these dielectric post 406.In addition, the photoresist layer 414 that forms patterning more simultaneously is in second 402b of conduction sandwich layer 402, wherein the photoresist layer 414 of patterning has a plurality of openings 416 equally, in order to the local side (promptly exposing local plating seed layer 410) of the other end that exposes these dielectric post 406.In addition, the photoresist layer 412 of patterning and photoresist layer 414 have a plurality of openings 417 more respectively, and it also exposes local plating seed layer 410 respectively.It should be noted that, when photoresist layer 412 when utilizing exposure and step of developing to form opening 416, because when photoresist layer 412 is developed, still can remove the local photoresist layer 412 that has exposed, so when photoresist layer 412 is exposed, can in advance the exposure area be extended in the predeterminated position of opening 416 slightly, make follow-up when photoresist layer 412 is developed, can allow the final cross-sectional area of opening 416 less, and meet a preset value.
Please refer to Fig. 4 G, in the mode of electroplating, via plating seed layer, with the inner face of plated with conductive material in perforation 408, and formation conduction wall 420, and simultaneously with plated with conductive material on the local side of first 402a of the contiguous conduction sandwich layer 402 of the dielectric post 406 that a plurality of openings 416 expose of photoresist layer 412 and photoresist layer 414 and second 402b, and form a plurality of conductive poles 418, wherein conductive pole 418 is connected in the ora terminalis of corresponding conduction wall 420.In addition, more simultaneously with plated with conductive material on the parcel plating Seed Layer 410 of a plurality of openings 417 of photoresist layer 412 and photoresist layer 414, and form a plurality of conductive poles 419.In addition, more visual actual needs, and plate the barrier metal layer (not shown) on the surface of conductive pole 418,419 are in order to the protection as the subsequent etch technology of conductive pole 418,419.
Please refer to Fig. 4 H, after forming these conductive poles 418, conductive pole 419 and conduction wall 420, then remove the photoresist layer 412 and the photoresist layer 414 of the patterning shown in Fig. 4 G, and utilize the mode of fast-etching, remove the plating seed layer 410 shown in Fig. 4 G, particularly remove the parcel plating Seed Layer 410 of the both ends of the surface of dielectric post 406.
Please refer to Fig. 4 I, dielectric material is inserted the cylindrical space that these conduction walls 420 are surrounded, in order to form a dielectric post 426 respectively, and can be in formation dielectric post 426, simultaneously dielectric layer 422 and dielectric layer 424 are formed at the two sides of conduction sandwich layer 402 respectively, and respectively around the lateral margin of these conductive poles 418 and conductive pole 419.It should be noted that, when dielectric material in a single day residue in conductive pole 418 or conductive pole 419 away from the conduction sandwich layer 402 end face the time, can utilize the mode of grinding or plasma etching, remove residual dielectric material, and the surface of while planarization dielectric layer 422 (or dielectric layers 424), so will help follow-up processing step.
Please refer to Fig. 4 J, after forming dielectric layer 422, dielectric layer 424 and dielectric post 426, form the conductive layer 428 of patterning and conductive layer 430 more respectively on dielectric layer 422 and dielectric layer 424, wherein conductive layer 428 is more via joint sheet 432 that it constituted, and be connected in the end of conductive pole 418a, and conductive layer 430 is more via the joint sheet 434 that it constituted, and is connected in the end of conductive pole 418b.Therefore, the joint sheet 432 that is made of conductive layer 428 can be in regular turn via conductive pole 418a, conduction wall 420 and conductive pole 418b, and is electrically connected to the joint sheet 434 that conductive layer 430 is constituted.
Please refer to Fig. 5, it illustrates the circuit base plate of three conductive layers of second embodiment, the partial schematic diagram of its internal wiring structure.Circuit base plate 500 only illustrates the dielectric part of its local current-carrying part and part in figure.Circuit base plate 500 comprises three layers of conductive layer 502, be the conductive layer 502b and the conductive layer 502c of conductive layer 502a, part, and conductive layer 502b illustrates the central authorities of its part in figure, and isolated with dielectric post 505 between conduction wall 504 and the conductive layer 502b, wherein the joint sheet 508a of conductive layer 502a can be in regular turn via conductive pole 506a, conduction wall 504 and conductive pole 506b, and be electrically connected on the joint sheet 508b of conductive layer 502d, and lead 510 is between two joint sheet 508a.
In order more clearly to compare circuit base plate and the difference of existing circuit base plate on wiring density of second embodiment, please refer to Fig. 1,5.At first, as shown in Figure 1, with regard to existing technology of making circuit base plate 100 with Layer increasing method, because the Production Time of plated-through-hole 104 is early than the Production Time of via 108, contraposition nargin when making via 108 in order to be provided at, the landing surface of via 108 can't directly be provided with the annular end face of plated-through-hole 104, make the two ends of plated-through-hole 104 must form air ring 106 extraly, so will increase the spacing of two adjacent plated-through-holes 104 relatively.Yet, as shown in Figure 5, during the technology of the circuit base plate 500 of second embodiment, because conduction wall 504 and conductive pole 506 (being conductive pole 506a and conductive pole 506b) are to complete simultaneously, make that the aligning accuracy between conduction wall 504 and the conductive pole 508 only involves the single photoresist layer 412 of Fig. 4 F and the aligning accuracy of photoresist layer 414.Therefore, the distance of two adjacent conductive walls 504 can reduce further, make the spacing of two bond pad adjacent 508 (particularly joint sheet 508a) to reduce further relatively.
Please in regular turn with reference to figure 6A, 6B, it illustrates the circuit base plate of Fig. 5 respectively, the partial schematic diagram of the internal wiring structure of its two kinds of various wirings designs.At first, as shown in Figure 6A, during the technology of the circuit base plate 500 of second embodiment, because conduction wall 504 and conductive pole 506 are to complete simultaneously, so need not reserve the contraposition nargin of conductive pole 506 with respect to conduction wall 504, make the distance between the two adjacent conductive walls 504 to reduce further, relatively, make that the distance between the lead 510 that joint sheet 508 is adjacent also can reduce further.In addition, shown in Fig. 6 B, similarly, during the technology of the circuit base plate 500 of second embodiment, because conduction wall 504 and conductive pole 506 are to complete simultaneously,, make that the distance between the two adjacent conductive walls 504 can reduce further so need not reserve the contraposition nargin of conductive pole 506 with respect to conduction wall 504, relatively, make the distance between two bond pad adjacent 508 also can reduce further.
With regard to the second embodiment of the present invention, compared to existing circuit base plate, second embodiment can provide the circuit base plate of high wiring density.In addition, compared to existing technology of making circuit base plate with Layer increasing method, second embodiment can reduce the number of steps of the technology of circuit base plate, thereby reduces the cost of manufacture and the process cycle of circuit base plate.
In sum, circuit base plate of the present invention mainly is to adopt the conduction wall and the integrated practice of conductive pole, promptly produce once electrical connection media between the conductive layer of finishing three to four layers, so under identical wiring density, this circuit base plate can increase the conduction wall of circuit base plate and the contraposition nargin between the conductive pole, or under identical wiring area, this circuit base plate more can improve higher wiring density, comprises high wire density and high joint sheet density.In addition, with the circuit base plates of existing making identical conduction number design layer by layer in comparison, the technology of circuit base plate of the present invention more can reduce the number of steps of the technology of circuit base plate, and then reduces the cost of manufacture and the process cycle of circuit base plate.
Though the present invention with preferred embodiment openly as above; but it is not in order to limit the present invention; under the situation that does not break away from the spirit and scope of the present invention; those skilled in the art can do a little change and retouching, so protection scope of the present invention is when being as the criterion so that appended claim is determined.
Claims (4)
1. circuit base plate comprises:
One initiation layer has one first and corresponding one second, and this initiation layer has more a perforation, and it runs through this initiation layer, and connects this first and this second of this initiation layer;
One conduction wall is disposed at the inner face of this perforation;
One dielectric post is disposed at the cylindrical space that this conduction wall is surrounded;
At least one conductive pole, the local surfaces of one end are connected in this end face of first of this initiation layer of vicinity of this conduction wall, and this conduction wall and this conductive pole are integrated structures;
One dielectric layer be disposed at this first of this initiation layer, and this dielectric layer is surrounded on the lateral margin of this conductive pole; And
One first conductive layer of patterning is disposed on this dielectric layer, and this first conductive layer has one first joint sheet, and it is connected in the other end of this conductive pole.
2. circuit base plate as claimed in claim 1, wherein when this initiation layer was a conduction sandwich layer, this circuit base plate more comprised a dielectric wall, it is disposed between this perforation and this conduction wall.
3. circuit base plate as claimed in claim 1, wherein this initiation layer comprises one second conductive layer of a dielectric sandwich layer, patterning and one the 3rd conductive layer of patterning, and this second conductive layer and the 3rd conductive layer are disposed at the two sides of this dielectric sandwich layer respectively, and this second conductive layer is adjacent to this first of this initiation layer.
4. circuit base plate as claimed in claim 3, wherein this second conductive layer has more one second joint sheet, it is disposed at the local end face of this end of this perforation of vicinity of this conduction wall, and this end of this conductive pole is via this second joint sheet, and is connected in the local end face of this end of this perforation of vicinity of this conduction wall indirectly.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB03142340XA CN1293793C (en) | 2003-06-13 | 2003-06-13 | Line baseplate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB03142340XA CN1293793C (en) | 2003-06-13 | 2003-06-13 | Line baseplate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1479372A CN1479372A (en) | 2004-03-03 |
| CN1293793C true CN1293793C (en) | 2007-01-03 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB03142340XA Expired - Lifetime CN1293793C (en) | 2003-06-13 | 2003-06-13 | Line baseplate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1293793C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI514530B (en) * | 2013-08-28 | 2015-12-21 | Via Tech Inc | Circuit substrate, semiconductor package and process for fabricating a circuit substrate |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101534601B (en) * | 2008-03-10 | 2010-09-22 | 英业达股份有限公司 | Routing carrier for printed circuit board |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02150042A (en) * | 1988-11-30 | 1990-06-08 | Nec Corp | Hybrid integrated circuit |
| CN1084586C (en) * | 1997-06-03 | 2002-05-08 | 国际商业机器公司 | Circuit board with primary and secondary through holes |
-
2003
- 2003-06-13 CN CNB03142340XA patent/CN1293793C/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02150042A (en) * | 1988-11-30 | 1990-06-08 | Nec Corp | Hybrid integrated circuit |
| CN1084586C (en) * | 1997-06-03 | 2002-05-08 | 国际商业机器公司 | Circuit board with primary and secondary through holes |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI514530B (en) * | 2013-08-28 | 2015-12-21 | Via Tech Inc | Circuit substrate, semiconductor package and process for fabricating a circuit substrate |
| US10103115B2 (en) | 2013-08-28 | 2018-10-16 | Via Technologies, Inc. | Circuit substrate and semicondutor package structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1479372A (en) | 2004-03-03 |
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