JPH03206692A - Printed circuit board - Google Patents
Printed circuit boardInfo
- Publication number
- JPH03206692A JPH03206692A JP191890A JP191890A JPH03206692A JP H03206692 A JPH03206692 A JP H03206692A JP 191890 A JP191890 A JP 191890A JP 191890 A JP191890 A JP 191890A JP H03206692 A JPH03206692 A JP H03206692A
- Authority
- JP
- Japan
- Prior art keywords
- electromagnetic shielding
- layer
- shielding layer
- conductor pattern
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004020 conductor Substances 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000005476 soldering Methods 0.000 claims abstract description 14
- 230000002093 peripheral effect Effects 0.000 abstract description 9
- 230000000694 effects Effects 0.000 abstract description 5
- 230000007547 defect Effects 0.000 abstract description 4
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 239000011521 glass Substances 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000005855 radiation Effects 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 229910000859 α-Fe Inorganic materials 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003779 heat-resistant material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0094—Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Structure Of Printed Boards (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
この発明は、電磁遮蔽構造を有する印刷回路基板に関す
る。DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field This invention relates to a printed circuit board having an electromagnetic shielding structure.
（ロ）従来の技術
第６図は、従来の電磁遮蔽構造を有する印刷回路基板を
示し、そのｒｃ１９搭載位置での要部断面を示している
。１２は、例えばセラξツクからなる絶縁基板であり、
ＩＣ１９直下の位置にスルーホール１２ａが穿設されて
いる。絶縁基板１２上には、第１の電磁遮蔽層１３が形
成されており、その周縁１３ａは、ＩＣ１９のリード１
９ａより外方にまで達している。この第１の電磁遮蔽層
１３は、フエライト等を含むペーストを絶縁基板１２上
に印刷して、焼威してなるものである。(b) Prior Art FIG. 6 shows a printed circuit board having a conventional electromagnetic shielding structure, and shows a cross section of the main part thereof at the mounting position of the RC19. 12 is an insulating substrate made of, for example, ceramics;
A through hole 12a is bored at a position directly below the IC 19. A first electromagnetic shielding layer 13 is formed on the insulating substrate 12, and its peripheral edge 13a is connected to the lead 1 of the IC 19.
It reaches outward from 9a. This first electromagnetic shielding layer 13 is formed by printing a paste containing ferrite or the like on the insulating substrate 12 and burning it out.
絶縁基板１２の裏面１２ｃには、裏面導体パターンｌ４
が、表面１２ｂには導体パターン１５がそれぞれ形成さ
れる。導体パターン１５は、スルーホール１２ａ内面を
通って、裏面導体パターン１４に導通している。On the back surface 12c of the insulating substrate 12, there is a back conductor pattern l4.
However, conductive patterns 15 are formed on the surface 12b. The conductor pattern 15 passes through the inner surface of the through hole 12a and is electrically connected to the back conductor pattern 14.
この導体パターン１５上には、さらに第２の電磁遮蔽層
１６が形成される。この第２の電磁遮蔽Ｎｌ６は、第１
の電磁遮蔽層１３と同様に形成され、概ねＩＣ１９のパ
ッケージ１９ｂと同じ大きさに広がっている。A second electromagnetic shielding layer 16 is further formed on this conductive pattern 15. This second electromagnetic shielding Nl6
It is formed in the same manner as the electromagnetic shielding layer 13 of , and extends to approximately the same size as the package 19b of the IC 19.
絶縁基板ｌ２上には、さらにオーバーガラス層１８が形
成され、導体パターン１５のはんだ付けランドＬの部分
を除いて、導体パターン１５、第２の電磁遮蔽層１６が
被覆・絶縁される。ランドＬの部分には、ＩＣ１９のリ
ード１９ａ先端がはんだＳによりはんだ付けされる。An overglass layer 18 is further formed on the insulating substrate l2, and the conductor pattern 15 and the second electromagnetic shielding layer 16 are covered and insulated except for the soldering land L portion of the conductor pattern 15. The ends of the leads 19a of the IC 19 are soldered to the lands L with solder S.
湛体パターン１５の、スルーホール１２ａよりランドＬ
に至る部分は、第ｌの電磁遮蔽層ｌ３と第２の電磁遮蔽
層１６とで挾まれているから、この部分を流れる信号か
らの不要輻射を遮蔽することができる。また、ＩＣ１９
が２つの電磁遮蔽層１３、ｌ６上にあるため、絶縁基板
ｌ２の裏面側とＩＣ１９とを電磁遮蔽することができる
。The land L from the through hole 12a of the full body pattern 15
Since the portion leading to is sandwiched between the first electromagnetic shielding layer l3 and the second electromagnetic shielding layer 16, unnecessary radiation from the signal flowing through this portion can be shielded. Also, IC19
are on the two electromagnetic shielding layers 13 and l6, so that the back side of the insulating substrate l2 and the IC 19 can be electromagnetically shielded.
（ハ）発明が解決しようとする課題
上記従来の印刷回路基板では、導体パターン１５のラン
ドＬと、ＩＣｌ９のリード１９ａとの高さが合わず、は
んだ付けの不良が発生しやすい問題点があった。また、
ランドＬを設けるた−め、第２の電磁３！！蔽層ｌ６の
面積が限られ、電磁遮蔽効果が半減してしまう問題点も
あった。(c) Problems to be Solved by the Invention In the conventional printed circuit board described above, there is a problem in that the heights of the lands L of the conductor pattern 15 and the leads 19a of the ICl 9 do not match, which tends to cause soldering defects. Ta. Also,
In order to provide the land L, the second electromagnetic 3! ! There was also a problem that the area of the shielding layer l6 was limited and the electromagnetic shielding effect was halved.
この発明は上記に鑑みなされたものであり、はんだ付け
が良好に行え、電磁遮蔽効果に優れた印刷回路基板の提
供を目的としている。This invention has been made in view of the above, and aims to provide a printed circuit board that can be easily soldered and has an excellent electromagnetic shielding effect.
（二）課題を解決するための手段及び作用この発明の印
刷回路基板の構戒を、一実施例に対応する第１図を用い
て説明すると、絶縁基板２と、この絶縁基板２上の電子
部品９搭載位置に形成される第ｌの電磁遮蔽Ｎ３と、前
記絶縁基板２上に形成され、その一部が第１の電磁ＺＭ
層３上に重なる導体パターン５と、前記第１の電磁遮蔽
層３上に形成され、前記導体パターン５の一部を被覆す
る第２の電磁遮蔽層６とを備えてなるものにおいて、前
記第２の電磁遮蔽層６の周縁６ａを、前記電子部品９の
リード９ａはんだ付け位置Ｌまで延設し、前記導体パタ
ーン５上から、この第２の電磁遮蔽層周縁６ａ上にかけ
て形成され、前記リードはんだ付け位置Ｌまで達する上
層導体パターン７を備えたことを特徴とするものである
。(2) Means and operation for solving the problems The structure of the printed circuit board of the present invention will be explained using FIG. 1 corresponding to one embodiment. a first electromagnetic shield N3 formed at the component 9 mounting position and a first electromagnetic shield N3 formed on the insulating substrate 2, a part of which is
A conductor pattern 5 overlapping the layer 3 and a second electromagnetic shielding layer 6 formed on the first electromagnetic shielding layer 3 and covering a part of the conductor pattern 5, The peripheral edge 6a of the second electromagnetic shielding layer 6 is extended to the soldering position L of the lead 9a of the electronic component 9, and is formed from above the conductive pattern 5 to above the second electromagnetic shielding layer 6a, and the lead It is characterized by having an upper layer conductor pattern 7 that reaches the soldering position L.
この印刷回路基板では、はんだ付け位置Ｌの高さが、従
来に比べて、第２の電磁遮蔽層６と上層導体パターン７
の分だけ高くなって、リード９ａの高さを合わせること
ができ、はんだ付け不良を防止する。また、第２の電磁
遮蔽層６の面積が広がるため、電磁遮蔽効果を向上させ
ることができる。In this printed circuit board, the height of the soldering position L is higher than that of the second electromagnetic shielding layer 6 and the upper layer conductor pattern 7.
This makes it possible to match the height of the leads 9a, thereby preventing poor soldering. Furthermore, since the area of the second electromagnetic shielding layer 6 is increased, the electromagnetic shielding effect can be improved.
（ホ）実施例
この発明の一実施例を第１図乃至第５図に基づいて以下
に説明する。(E) Embodiment An embodiment of the present invention will be described below with reference to FIGS. 1 to 5.
第１図は、実施例印刷回路基板１のＩＣ９の搭載位置に
おける要部断面図であり、第２図乃至第５図は、それぞ
れ順に製造工程を説明する図である。以下、順に製造工
程を追いながら実施例印刷回路基板ｌを説明する。FIG. 1 is a sectional view of the main part of the printed circuit board 1 of the embodiment at the mounting position of the IC 9, and FIGS. 2 to 5 are diagrams each explaining the manufacturing process in order. Hereinafter, an example printed circuit board 1 will be explained while following the manufacturing process in order.
第２図は、セラミノク等の耐熱性の材料よりなる絶縁基
板２の表面２ｂのｒＣ９搭載位置に、第１の電磁遮蔽層
３を形戒した状態を示している。FIG. 2 shows a state in which the first electromagnetic shielding layer 3 is formed at the mounting position of the rC9 on the surface 2b of the insulating substrate 2 made of a heat-resistant material such as ceramic material.
この第ｌの電磁遮蔽Ｍ３は、絶縁基板２上に、電磁遮蔽
物、例えばフエライトを含むペーストを印刷し、これを
焼威してなるものである。絶縁基板２には、スルーホー
ル２ａが穿設されている。The first electromagnetic shield M3 is formed by printing an electromagnetic shield, for example a paste containing ferrite, on the insulating substrate 2 and burning it. A through hole 2a is formed in the insulating substrate 2.
第３図は、絶縁基板２の表面２ｂと裏面２Ｃにそれぞれ
、下層導体パターン５と裏面導体パターン４を形成した
状態を示している。これら下層導体パターン５と裏面導
体パターン４とは、導体ペーストを印刷・焼威してなる
ものであり、下層導体パターン５の一部は、第１の電磁
遮蔽層３上に重なっており、またスルーホール２ａの内
面に沿って絶縁基板裏面２Ｃに達し、裏面導体パターン
４と導通する。FIG. 3 shows a state in which a lower conductor pattern 5 and a back conductor pattern 4 are formed on the front surface 2b and back surface 2C of the insulating substrate 2, respectively. The lower conductor pattern 5 and the back conductor pattern 4 are formed by printing and burning conductor paste, and a portion of the lower conductor pattern 5 overlaps the first electromagnetic shielding layer 3, and It reaches the back surface 2C of the insulating substrate along the inner surface of the through hole 2a, and is electrically connected to the back surface conductor pattern 4.
第４図は、第１の電磁遮蔽層３上に第２の電磁遮蔽層６
を形或した状態を示しており、この第２の電磁遮蔽層６
は、第１の電磁遮蔽層３と同様にペーストを印刷・焼威
して形成されている。この第２の電磁遮蔽層６は、導体
パターン５の第１の？ｉｔ磁遮蔽層３上に位置する部分
及びスルーホール２ａを覆っている。また、その大きさ
は周縁６ａがランド（はんだ付け部）Ｌまで．達する程
度とされる。FIG. 4 shows a second electromagnetic shielding layer 6 on the first electromagnetic shielding layer 3.
This second electromagnetic shielding layer 6
is formed by printing and burning a paste in the same way as the first electromagnetic shielding layer 3. This second electromagnetic shielding layer 6 is the first layer of the conductive pattern 5. It covers the portion located on the IT magnetic shielding layer 3 and the through hole 2a. Also, its size is such that the peripheral edge 6a extends to the land (soldering part) L. It is said that it reaches the extent that
第５図は、上層導体パターン７を形成した状態を示して
いる。この上層導体パターン７は、下層導体パターン５
から第２の電磁遮蔽層周縁６ａ上にかけて形或され、ラ
ンドＬを構或する。もちろん、下層導体パターン５と上
層導体パターン７とは導通することとなる。FIG. 5 shows the state in which the upper layer conductor pattern 7 has been formed. This upper layer conductor pattern 7 is similar to the lower layer conductor pattern 5.
The land L is formed from the top to the second electromagnetic shielding layer peripheral edge 6a. Of course, the lower layer conductor pattern 5 and the upper layer conductor pattern 7 are electrically connected.
最後に、第ｌ図に示すように、絶縁基板表面２ｂに、オ
ーバーガラス層８が形成され、上層導体パターン７のラ
ンドＬを除いて、上層導体パターン７、下層導体パター
ン５、第ｌ、第２の電磁遮蔽層３、６が被覆され、絶縁
される。なお、第１図乃至第５図では、導体パターン４
、５、７及び第１、第２の電磁遮蔽層３、６の厚さは、
絶縁基板２の厚さに対して誇張して描いている。Finally, as shown in FIG. Two electromagnetic shielding layers 3, 6 are coated and insulated. In addition, in FIGS. 1 to 5, the conductor pattern 4
, 5, 7 and the thicknesses of the first and second electromagnetic shielding layers 3, 6 are:
The thickness of the insulating substrate 2 is exaggerated.
第１図では、さらにフラットパッケージ型のＩＣ９を搭
載した状態を示している。ＩＣ９のりード９ａぱ、前記
ランドしにはんだＳではんだ付けされる。この時、ＩＣ
９のパッケージ９ｂ直下のオーバーガラスｗ１８の高さ
と、ランドＬの高さがほぼ揃うため、はんだ付Ｕ不良が
防止できる。FIG. 1 shows a state in which a flat package type IC 9 is further mounted. The lead 9a of the IC9 is soldered to the land with solder S. At this time, I.C.
Since the height of the overglass w18 directly under the package 9b of No. 9 and the height of the land L are almost the same, defects in soldering U can be prevented.
第ｌ図の場合には、裏面導体パターン４とりード９ａと
の間で、信号電流は矢印で示すように、スルーホール２
ａ、下層導体パターン５、上層導体パターン７を経て流
れる。この信号電流よりの不要輻射は、第ｌ、第２の電
磁遮蔽層３、６により遮蔽される。In the case of FIG. 1, the signal current flows between the back conductor pattern 4 and the lead 9a through the through hole 2 as shown by the arrow.
a, it flows through the lower layer conductor pattern 5 and the upper layer conductor pattern 7. Unnecessary radiation from this signal current is shielded by the first and second electromagnetic shielding layers 3 and 6.
また、第２の電磁遮蔽層周縁６ａは、リード９ａの下方
にも位置しているので、従来よりも有効に、ＩＣ９と絶
縁基板裏而２ｃとを電磁遮蔽することができる。Further, since the second electromagnetic shielding layer peripheral edge 6a is also located below the lead 9a, it is possible to electromagnetically shield the IC 9 and the insulating substrate backing 2c more effectively than before.
なお、上記説明では、ＩＣを電磁遮蔽する場合を例に上
げているが、この発明は、トランジスタ、チップダイオ
ード、チップ抵抗器、チップコンデンサ等各種電子部品
の電磁遮蔽に適用可能である。In the above description, the case of electromagnetically shielding an IC is taken as an example, but the present invention is applicable to electromagnetically shielding various electronic components such as transistors, chip diodes, chip resistors, and chip capacitors.
（へ）発明の効果
以上説明したように、この発明の印刷回路基板は、第２
の電磁遮蔽層の周縁を、電子部品のリードはんだ付け位
置まで延設し、導体パターン上からこの第２の電磁遮蔽
周縁上にかけて形成され、前記リードはんだ付け位置ま
で達する七層導体パターンを備えたことを特徴とするも
のであるから、はんだ付け不良を防止できると共に、電
子部品と印刷回路基板裏面とを有効に電磁遮蔽できる利
点を有している。(f) Effects of the invention As explained above, the printed circuit board of this invention has a second
The peripheral edge of the electromagnetic shielding layer is extended to the lead soldering position of the electronic component, and a seven-layer conductive pattern is formed from the conductor pattern to the second electromagnetic shielding peripheral edge and reaches the lead soldering position. Because of this feature, it has the advantage of being able to prevent soldering defects and effectively shielding electronic components from the back surface of the printed circuit board.
第ｌ図は、この発明の一実施例に係る印刷回路基板の要
部断面図、第２図、第３図、第４図及び第５図は、それ
ぞれ順に同印刷回路基板の製造工程を説明する断面図、
第６図は、従来の印刷回路基板の要部断面図である。
２：絶縁基板、 ３：第ｌの電磁遮蔽層、５：下
層導体パターン、６：第２の電磁遮蔽層、７：上層導体
パターン。FIG. 1 is a sectional view of a main part of a printed circuit board according to an embodiment of the present invention, and FIGS. 2, 3, 4, and 5 each illustrate the manufacturing process of the same printed circuit board in order. cross-sectional view,
FIG. 6 is a sectional view of essential parts of a conventional printed circuit board. 2: insulating substrate, 3: lth electromagnetic shielding layer, 5: lower layer conductor pattern, 6: second electromagnetic shielding layer, 7: upper layer conductor pattern.
Claims (1)
に形成される第１の電磁遮蔽層と、前記絶縁基板上に形
成され、その一部が第１の電磁遮蔽層上に重なる導体パ
ターンと、前記第１の電磁遮蔽層上に形成され、前記導
体パターンの一部を被覆する第２の電磁遮蔽層とを備え
てなる印刷回路基板において、 前記第２の電磁遮蔽層の周縁を、前記電子部品のリード
はんだ付け位置まで延設し、前記導体パターン上からこ
の第２の電磁遮蔽層周縁上にかけて形成され、前記リー
ドはんだ付け位置まで達する上層導体パターンを備えた
ことを特徴とする印刷回路基板。(1) An insulating substrate, a first electromagnetic shielding layer formed on the insulating substrate at an electronic component mounting position, and a conductor formed on the insulating substrate, a part of which overlaps the first electromagnetic shielding layer. A printed circuit board comprising a pattern and a second electromagnetic shielding layer formed on the first electromagnetic shielding layer and covering a part of the conductive pattern, the periphery of the second electromagnetic shielding layer being , an upper conductor pattern extending to the lead soldering position of the electronic component, formed from above the conductor pattern to the periphery of the second electromagnetic shielding layer, and reaching the lead soldering position. printed circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP191890A JPH0812955B2 (en) | 1990-01-09 | 1990-01-09 | Printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP191890A JPH0812955B2 (en) | 1990-01-09 | 1990-01-09 | Printed circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03206692A true JPH03206692A (en) | 1991-09-10 |
| JPH0812955B2 JPH0812955B2 (en) | 1996-02-07 |
Family
ID=11514970
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP191890A Expired - Lifetime JPH0812955B2 (en) | 1990-01-09 | 1990-01-09 | Printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0812955B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112394577A (en) * | 2020-12-02 | 2021-02-23 | 上海摩软通讯技术有限公司 | Display module and display device |
-
1990
- 1990-01-09 JP JP191890A patent/JPH0812955B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112394577A (en) * | 2020-12-02 | 2021-02-23 | 上海摩软通讯技术有限公司 | Display module and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0812955B2 (en) | 1996-02-07 |
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