JPH03252193A - Wiring board - Google Patents
Wiring boardInfo
- Publication number
- JPH03252193A JPH03252193A JP4975690A JP4975690A JPH03252193A JP H03252193 A JPH03252193 A JP H03252193A JP 4975690 A JP4975690 A JP 4975690A JP 4975690 A JP4975690 A JP 4975690A JP H03252193 A JPH03252193 A JP H03252193A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- hole
- capacitor
- dielectric
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 12
- 239000003989 dielectric material Substances 0.000 claims description 6
- 239000003990 capacitor Substances 0.000 abstract description 24
- 230000000694 effects Effects 0.000 abstract description 6
- 239000004020 conductor Substances 0.000 abstract description 3
- 229910052802 copper Inorganic materials 0.000 abstract description 3
- 229910052709 silver Inorganic materials 0.000 abstract description 3
- 229910000464 lead oxide Inorganic materials 0.000 abstract description 2
- YEXPOXQUZXUXJW-UHFFFAOYSA-N oxolead Chemical compound [Pb]=O YEXPOXQUZXUXJW-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052712 strontium Inorganic materials 0.000 abstract description 2
- CIOAGBVUUVVLOB-UHFFFAOYSA-N strontium atom Chemical compound [Sr] CIOAGBVUUVVLOB-UHFFFAOYSA-N 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 12
- 238000007639 printing Methods 0.000 description 6
- 230000008030 elimination Effects 0.000 description 4
- 238000003379 elimination reaction Methods 0.000 description 4
- 238000010304 firing Methods 0.000 description 4
- 238000005476 soldering Methods 0.000 description 4
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 230000008642 heat stress Effects 0.000 description 2
- 239000005011 phenolic resin Substances 0.000 description 2
- 229920001568 phenolic resin Polymers 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はコンデンサ内蔵の配線基板に関するものである
。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a wiring board with a built-in capacitor.
従来の技術
第3図のごと〈従来のコンデンサ内蔵の配線基板1は、
基板2の表面にCu、Ag等の導電性材料からなる第一
層の電極3が膜厚印刷工程と焼成工程等を経て形成され
、更に、電極3の上面に設計コンデンサ容量を持たせる
ために、誘電体4が厚膜印刷工程と焼成工程等を経て形
成される。そして、誘電体4を挟み込むように電極5が
厚膜印刷工程と焼成工程等を経て形成され、これらの電
極3,5と誘電体4でコンデンサ6が構成されている。Conventional technology As shown in Figure 3, the conventional wiring board 1 with a built-in capacitor is
A first layer electrode 3 made of a conductive material such as Cu or Ag is formed on the surface of the substrate 2 through a film thickness printing process and a baking process, and furthermore, in order to have a designed capacitance on the top surface of the electrode 3. , the dielectric 4 is formed through a thick film printing process, a firing process, and the like. Then, electrodes 5 are formed through a thick film printing process, a firing process, etc. so as to sandwich the dielectric 4, and a capacitor 6 is constituted by these electrodes 3, 5 and the dielectric 4.
更に電極5の上面には、本コンデンサ6の半田付は時に
おける熱ストレス、市場での温度、湿度等によるストレ
スなどに対する保護の目的で、エポキシ、フェノール樹
脂、ガラスなどのオーバーコート材料7によるコーティ
ングが行われている。Furthermore, the upper surface of the electrode 5 is coated with an overcoat material 7 such as epoxy, phenolic resin, or glass for the purpose of protection against heat stress during soldering of the capacitor 6, stress caused by temperature, humidity, etc. in the market. is being carried out.
発明が解決しようとする課題
このような第3図のコンデンサ内蔵の配線基板1におい
ては、容量が大きいコンデンサはより大きな面積を必要
とするため、基板2のその他の部品(入出力端子8.チ
ップ部品9.ICなど)の高密度実装が要求される場合
、その実装を阻害する要因となる。また、コンデンサ6
が第3図に示すように、高周波機器などの、電源端子の
妨害排除接地コンデンサの場合、電源端子の電極10と
コンデンサ6の距離が遠くて配線部が長くなり、妨害排
除の効果が半減することになる。そこで本発明はこのよ
うな課題を解決し、他の部品の実装を阻害したり、妨害
排除効果が低下したりすることを防止することを目的と
するものである。Problems to be Solved by the Invention In the wiring board 1 with a built-in capacitor as shown in FIG. When high-density mounting of components 9. IC, etc.) is required, this becomes a factor that impedes the mounting. Also, capacitor 6
As shown in Figure 3, in the case of a grounded capacitor for eliminating interference at the power supply terminal of high-frequency equipment, etc., the distance between the electrode 10 of the power supply terminal and the capacitor 6 is long, and the wiring becomes long, reducing the interference elimination effect by half. It turns out. SUMMARY OF THE INVENTION An object of the present invention is to solve these problems and prevent the mounting of other components from being obstructed and the interference elimination effect from decreasing.
課題を解決するための手段
そしてこの目的を達成するために本発明は、基板に設け
た貫通孔、または穴の内面に第1の電極を形成し、この
第1の電極の上面に誘電体を形成し、この誘電体の上に
第2の電極を形成したものである。Means for Solving the Problems In order to achieve this object, the present invention forms a first electrode on the inner surface of a through hole or hole provided in a substrate, and coats a dielectric material on the upper surface of the first electrode. A second electrode is formed on this dielectric.
作用
以上の構成とすることにより、第1.第2の電極と誘電
体よりなるコンデンサが基板の板厚部に形成されるため
、横方向への広がりがなくなる。By having a configuration that exceeds the functions, the first. Since the capacitor made of the second electrode and the dielectric material is formed in the thick part of the substrate, there is no spread in the lateral direction.
このため配線基板への入出力端子、チップ部品。For this reason, input/output terminals and chip components to wiring boards.
ICなど各種電子部品の高密度実装が要求される場合で
も、高密度に電子部品の実装が出来る。また、入出力端
子やリード線付きの部品なとはリード線の半田付はラン
ドを、コンデンサの第2電極で兼用可能となるため、更
に高密度実装が実現できるだけでなく、従来の印刷コン
デンサに比較して、配線部分のないコンデンサであるた
め、ESR(高周波抵抗)が小さく、バラツキの小さい
高性能コンデンサを構成する事が可能となるので、妨害
排除効果が低減したりすることもなくなる。Even when high-density mounting of various electronic components such as ICs is required, electronic components can be mounted at high density. In addition, for components with input/output terminals or lead wires, the second electrode of the capacitor can be used as the land for soldering the lead wires, which not only allows for even higher density mounting, but also allows for the soldering of the lead wires to the second electrode of the capacitor. In comparison, since it is a capacitor without a wiring part, it is possible to construct a high-performance capacitor with low ESR (high frequency resistance) and small variations, so that the interference elimination effect is not reduced.
実施例
以下、本発明の一実施例について、以下図面を用いて説
明する。第1図(a) 、 (b)において、セラミッ
ク基板やプリント基板などの基板12には角又は丸など
の貫通孔20が設けられている。そしてこの貫通孔20
の内面とその上下部の孔縁の基板12部にはCu、Ag
などの導電性材料からなる第1の電極13が厚膜印刷と
焼成工法又はメ・ソキ工法等により形成している。なお
貫通孔20の上下部の孔縁はゆるやかなテーパとし、そ
の上に第1の電極13を設けている。そして更に第1の
電極13の上面には必要な設計コンデンサ容量を持たせ
るために酸化鉛、ストロンチウムなどを含む誘電体14
が、厚膜印刷と焼成工程などにより形成されている。そ
して更に誘電体14を挟み込むようにその上に第2の電
極15が厚膜印刷と焼成工法又はメツキ工法等により形
成される。このような工程と構造によりコンデンサ16
が形成されている。そして更にこのコンデンサ16を内
蔵した配線基板11の半田デイツプなど行う場合の熱ス
トレス、市場での温度、湿度等による熱ストレスの保護
の目的でエポキシ、フェノール樹脂ガラス等のオーバー
コート17が必要な部分にコーティングされている。EXAMPLE An example of the present invention will be described below with reference to the drawings. In FIGS. 1A and 1B, a substrate 12 such as a ceramic substrate or a printed circuit board is provided with a through hole 20 having a corner or a round shape. And this through hole 20
The inner surface and the upper and lower hole edges of the substrate 12 are coated with Cu and Ag.
The first electrode 13 made of a conductive material such as, for example, is formed by a thick film printing and baking method, or a mesoki method. Note that the upper and lower edges of the through hole 20 are gently tapered, and the first electrode 13 is provided thereon. Further, on the upper surface of the first electrode 13, a dielectric material 14 containing lead oxide, strontium, etc. is disposed on the upper surface of the first electrode 13 to provide the necessary design capacitance.
is formed by thick film printing and firing process. Further, a second electrode 15 is formed on the dielectric 14 so as to sandwich the dielectric 14 therebetween by a thick film printing and firing method, a plating method, or the like. With this process and structure, the capacitor 16
is formed. In addition, there are areas where an overcoat 17 of epoxy, phenolic resin glass, etc. is required for the purpose of protecting the wiring board 11 containing the capacitor 16 from heat stress caused by solder dipping, temperature, humidity, etc. in the market. coated with.
本発明のコンデンサ16はスルホール形状でコンデンサ
を形成出来るため第1図に示すように入出力端子18や
チップ部品19や図示してはいないが、リード付きのコ
ンデンサ、抵抗、半導体など部品のリード部をコンデン
サ16の第2の電極15で直接半田付けする事ができる
。Since the capacitor 16 of the present invention can be formed into a capacitor in the form of a through-hole, as shown in FIG. can be directly soldered to the second electrode 15 of the capacitor 16.
次に本発明の他の実施例について第2図(al、(b)
を参照に説明する。基板12に細長い溝状の貫通孔20
を設け、この溝状の貫通孔20の右側内面に電極第1の
電極13を形成し、この第1の電極13の基板12の上
面部分は他の部品を接続するランドとなっている。また
溝状の貫通孔20の左側の内面には第2の電極15を形
成し、これもその基板12の上面部はランドとなってい
る。但しこの場合第1の電極13と第2電極15はそれ
ぞれ電気的に接続のない独立のものとなっている。Next, FIG. 2 (al, (b)) shows another embodiment of the present invention.
Explain with reference to. A long and narrow groove-shaped through hole 20 is formed in the substrate 12.
A first electrode 13 is formed on the right inner surface of this groove-shaped through hole 20, and the upper surface portion of the substrate 12 of this first electrode 13 serves as a land for connecting other components. A second electrode 15 is formed on the left inner surface of the groove-shaped through hole 20, and the upper surface of the substrate 12 is also a land. However, in this case, the first electrode 13 and the second electrode 15 are independent with no electrical connection.
そしてこの細長い溝状の貫通孔20にコンデンサの誘電
体14が充填されることにより、第1の電極13と第2
電極15の間にコンデンサ16を構成したものである。By filling this elongated groove-shaped through hole 20 with the dielectric material 14 of the capacitor, the first electrode 13 and the second electrode
A capacitor 16 is configured between electrodes 15.
なおこの場合も貫通孔20の上下の孔縁はゆるやかなテ
ーパとなっており、その上に第1.第2の電極13.1
5が形成されている。In this case as well, the upper and lower edges of the through hole 20 are gently tapered, and the first and second holes are formed on the upper and lower edges of the through hole 20. Second electrode 13.1
5 is formed.
また上記実施例では、基板12を貫通する貫通孔20を
形成したが、これは基板途中までの穴にして、ここに第
1.第2の電極13.15を設けても良い。Further, in the above embodiment, the through hole 20 that penetrates the substrate 12 is formed, but this hole is made halfway through the substrate, and the first through hole 20 is formed here. A second electrode 13.15 may also be provided.
発明の効果
以上のように本発明はコンデンサを基板の板厚部で形成
するので、基板への入出力端子、チップ部品、ICなど
各種電子部品の高密度実装が阻害されることのないもの
となる。特に入出力端子やリード線付きの部品などはリ
ード線の半田付はランドを、貫通孔、または穴の電極で
兼用でき、この点からも高密度実装が実現でき、また配
線部分のないコンデンサであるため、ESR(高周波抵
抗)が小さく、妨害排除効果が低減したりすることもな
くなる。Effects of the Invention As described above, since the present invention forms the capacitor in the thick part of the board, high-density mounting of various electronic parts such as input/output terminals, chip parts, and ICs on the board is not hindered. Become. In particular, for input/output terminals and components with lead wires, the land can be used as the land for soldering the lead wires, and the electrodes in the through holes or holes can also be used. This also makes it possible to achieve high-density mounting. Therefore, the ESR (high frequency resistance) is small, and the interference elimination effect is not reduced.
第1図(a)、(blは本発明の一実施例の配線基板の
断面図と下面図、第2図(a)、(b)は本発明の他の
実施例の断面図と平面図、第3図(al、(blは従来
例の断面図と下面図である。
11・・・・・・配線基板、12・・・・・・基板、1
3・・・・・・第1の電極、14・・・・・・誘電体、
15・・・・・・第2の電極、16・・・・・・コンデ
ンサ、17・・・・・・オーバコート、20・・・・・
・貫通孔。FIGS. 1(a) and (bl) are a cross-sectional view and a bottom view of a wiring board according to an embodiment of the present invention, and FIGS. 2(a) and (b) are a cross-sectional view and a plan view of another embodiment of the present invention. , FIG. 3 (al, (bl is a sectional view and bottom view of a conventional example. 11... Wiring board, 12... Board, 1
3...First electrode, 14...Dielectric material,
15... Second electrode, 16... Capacitor, 17... Overcoat, 20...
・Through hole.
Claims (2)
極を形成し、この第1の電極の上面に誘電体を形成し、
この誘電体の上に第2の電極を形成したことを特徴とす
る配線基板。(1) forming a first electrode on the inner surface of a through hole or hole provided in the substrate; forming a dielectric on the upper surface of the first electrode;
A wiring board characterized in that a second electrode is formed on the dielectric.
気的に独立した第1,第2の電極を形成するとともに、
前記貫通孔、または穴内に誘電体を充填した配線基板。(2) Forming electrically independent first and second electrodes in a through hole provided in the wiring board or on the inner surface of the hole,
A wiring board in which the through hole or the hole is filled with a dielectric material.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4975690A JPH03252193A (en) | 1990-03-01 | 1990-03-01 | Wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4975690A JPH03252193A (en) | 1990-03-01 | 1990-03-01 | Wiring board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03252193A true JPH03252193A (en) | 1991-11-11 |
Family
ID=12840033
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4975690A Pending JPH03252193A (en) | 1990-03-01 | 1990-03-01 | Wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03252193A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2001050823A1 (en) * | 1999-12-29 | 2001-07-12 | Intel Corporation | Self-aligned coaxial via capacitors |
JP2008028188A (en) * | 2006-07-21 | 2008-02-07 | Sharp Corp | Printed wiring board, method for manufacturing the same, and electronic apparatus |
US8558345B2 (en) | 2009-11-09 | 2013-10-15 | International Business Machines Corporation | Integrated decoupling capacitor employing conductive through-substrate vias |
JP2014222718A (en) * | 2013-05-14 | 2014-11-27 | 矢崎総業株式会社 | Molded circuit component |
-
1990
- 1990-03-01 JP JP4975690A patent/JPH03252193A/en active Pending
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2001050823A1 (en) * | 1999-12-29 | 2001-07-12 | Intel Corporation | Self-aligned coaxial via capacitors |
US6565730B2 (en) | 1999-12-29 | 2003-05-20 | Intel Corporation | Self-aligned coaxial via capacitors |
US6963483B2 (en) | 1999-12-29 | 2005-11-08 | Intel Corporation | Self-aligned coaxial via capacitors |
JP2008028188A (en) * | 2006-07-21 | 2008-02-07 | Sharp Corp | Printed wiring board, method for manufacturing the same, and electronic apparatus |
US8558345B2 (en) | 2009-11-09 | 2013-10-15 | International Business Machines Corporation | Integrated decoupling capacitor employing conductive through-substrate vias |
US8785289B2 (en) | 2009-11-09 | 2014-07-22 | International Business Machines Corporation | Integrated decoupling capacitor employing conductive through-substrate vias |
JP2014222718A (en) * | 2013-05-14 | 2014-11-27 | 矢崎総業株式会社 | Molded circuit component |
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