JPS6347248B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a hybrid integrated circuit board incorporating a multilayer capacitor.

A hybrid integrated circuit is a circuit in which circuit elements such as transistors, diodes, inductors L, capacitors C, and resistors R are mounted on a relatively small printed wiring board, and the necessary connections are made by soldering.
This is housed in a resin or other case, and a single
Some are inline packages or dual inline packages. Since such conventional methods have a low degree of integration and a complicated manufacturing process, the present inventors first proposed a solid-state multilayer electronic circuit component using a multilayer capacitor board with a built-in capacitor (Japanese Patent Application Laid-Open No. 56-43716 etc.). This method improves the degree of integration compared to the conventional method,
Although the manufacturing process is simplified, since the ends of the electrodes are exposed on the side surfaces of flat multilayer capacitors, it is necessary to further coat the conductor from there to the flat surface. The drawback is that it requires extra manufacturing steps such as hand painting.
In addition, the connection between the hand-painted conductor and the electrode end of the multilayer capacitor was often poor, resulting in a lack of reliability. Furthermore, there is a high possibility of interference with printed circuits placed on the flat surface of multilayer capacitors, which necessitates the use of jumpers, and without jumpers, only a simple circuit can be designed or the design becomes complicated. Therefore, there was a drawback that manufacturing was complicated.

The present invention was made to eliminate the above-mentioned drawbacks, and its purpose is to simplify the manufacturing process of a hybrid integrated circuit board, and provide a highly reliable hybrid integrated circuit board that is easy to design. It is to be. Briefly, the present invention provides an electrode extraction opening in the dielectric layers to be laminated, and extends the electrode of a multilayer capacitor through the opening onto the same plane of the outermost dielectric layer of the multilayer capacitor to form an electrode extraction terminal. The present invention also provides a hybrid integrated circuit board in which a printed circuit of a predetermined pattern is formed on this plane.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, an embodiment of the hybrid integrated circuit board of the present invention will be explained in the order of manufacturing steps with reference to FIGS. 1 to 3. First, as shown in FIG. 1A, a dielectric layer 1 is formed by a printing method or a sheet method. The printing method and sheet method refer to dielectric materials (TiO ₂ ,
It refers to printing by a squeegee method etc. from a paste made from powder of BaTiO ₃ etc.) with an appropriate binder, and spreading such a paste into a sheet. Note that, in reality, a number of capacitors are manufactured at the same time according to the circuit design, but for the sake of simplicity, a method for manufacturing a single capacitor will be described here. Next, as shown in FIG. 1B, a wide conductive pattern 2 for a capacitor electrode is formed on the dielectric layer 1, leaving a wide area under the dielectric layer 1. Next, as shown in Figure C,
Opening 3 at a position corresponding to the upper end of conductive pattern 2
A dielectric layer 4 is formed over the entire surface. Next, as shown in FIG. A conductive pattern 6 for connection is also formed. As a result, conductive patterns 2 and 6 are electrically connected. Next, as shown in Figure E, a dielectric layer 9 having an opening 7 of approximately the same size at a position corresponding to the opening 3 and an opening 8 at a position corresponding to the lower end of the conductive pattern 5 is formed over the entire surface. .
Next, as shown in FIG. 11 respectively. As a result, conductive patterns 10 and 6 are electrically connected, and conductive patterns 5 and 11 are electrically connected. Next, as shown in FIG. G, a dielectric layer 14 having openings 12 and 13 at positions corresponding to openings 7 and 8, respectively, is formed over the entire surface. Next, as shown in FIG.
Conductive patterns 15 and 16 are formed on and 13, respectively. As a result, the conductive pattern 15 is electrically connected to the conductive pattern 10 and therefore also to the conductive patterns 6 and 2, and the conductive pattern 16 is electrically connected to the conductive pattern 11 and therefore conductive. It is also electrically connected to pattern 5. That is, the conductive patterns 2 and 10 and the conductive pattern 5 forming the electrodes of the multilayer capacitor are connected to the openings 3, 7, 12 and 8, 13 in the dielectric layer.
They are drawn out onto the same plane of the outermost dielectric layer of the multilayer capacitor through the respective layers. The thus obtained laminate is placed in a firing furnace and treated at a temperature and time required for the dielectric to obtain an integrated multilayer capacitor. FIG. 2 is a schematic cross-sectional view of FIG. 1 H taken along line 2--2 after firing, and FIG. 3 is a perspective view. The conductor for the conductive pattern is Ag-
A paste consisting of a Pd alloy (75:25 to 50:50 alloy), Pd or other heat-resistant metal powder, and a binder is used.

After the firing is completed, a printed circuit in a predetermined pattern is formed on the plane 18 of the outermost dielectric layer from which the electrodes of the multilayer capacitor 17 are drawn. Thus,
A hybrid integrated circuit substrate according to the present invention is formed.
A desired hybrid integrated circuit is constructed by mounting predetermined circuit elements on this hybrid integrated circuit substrate and electrically connecting them, for example, by soldering. In this case, it is preferable that the interconnection between the electrode lead terminals (conductive patterns 15 and 16) of the multilayer capacitor and other circuit elements or terminals be performed by a printed circuit formed on the substrate 17; There is no problem even if the circuit element or terminal is directly connected to the electrode lead terminal.

FIG. 4 shows a multilayer capacitor 19 constituting another embodiment of the hybrid integrated circuit board according to the present invention.
Four capacitor elements (not shown) are formed inside this multilayer capacitor 19 by the same manufacturing process as described above, and electrode lead terminals C ₁ to C ₁ ', C ₂ to C ₂ ′, C ₃ ~C ₃ ′ and
C ₄ to C ₄ ' are drawn out on the same plane 20 of the outermost dielectric layer of the capacitor 19. This capacitor 19 has a protruding portion 21 formed on one side (the upper side in the figure), and this protruding portion 21 constitutes a leg portion for insertion into an insertion hole formed on a printed circuit board (see Fig. 5). Therefore, for example, six connection terminals T ₁ , T ₂ , . . . T ₆ are formed at predetermined positions. These connection terminals T ₁ to _{T 6} are electrode lead terminals
It can be formed by printing simultaneously with the formation of C ₁ to C ₄ and C ₁ ′ to C ₄ ′. Next, as shown in FIG. 5, for example, a printed circuit 22 having a predetermined pattern is formed on the plane 20 of the multilayer capacitor 19, thereby forming a hybrid integrated circuit substrate.
Predetermined circuit elements, in the illustrated example, transistors Q ₁ to _{Q 4} and various resistors R (R
(only shown in the diagram, but the constant of each resistor may be different)
be installed in the designated position. Note that the printed circuit 22
A jumper J (an element that allows crossing while insulating the crossing conductor) is provided at a location in the pattern that requires insulation crossing. Furthermore, although the intersections of the patterns of the printed circuit 22 are shown as black circles (.), this is only for ease of understanding.

After predetermined circuit elements are mounted, these circuit elements are electrically connected to the circuit pattern by, for example, soldering, thus forming a hybrid integrated circuit.
As shown in FIG. 5, this hybrid integrated circuit has its protrusion 21 inserted into an insertion hole 24 formed in a printed circuit board 23, and is connected to an external circuit via terminals _T1 to _T6 . FIG. 6 is a circuit connection diagram of the hybrid integrated circuit shown in FIG. 5, which can be used, for example, as a recording amplifier in a tape recorder. In addition, the protruding portion 21 is formed to connect the connecting terminal.
Instead of forming T ₁ to T ₆ , multilayer capacitor 19
Terminals are formed at predetermined ends of the terminal, external leads are connected to these terminals, and the terminals are sealed in a resin or other case to create a single in-line system as shown in Figure 7.
It may be packaged or dual inline packaged as shown in FIG. 7th
In the figure and FIG. 8, 25 is a package, 26
indicates an external lead.

As described above, in the present invention, openings for leading out electrodes are provided in the dielectric layers to be laminated, conductive patterns are formed in these openings, and the electrodes of the multilayer capacitor are drawn out on the same plane of the outermost dielectric layer of the multilayer capacitor. , since these pulled out terminals are used as they are as external connection terminals of the hybrid integrated circuit,
The manufacturing process is greatly simplified compared to the conventional method, and manufacturing efficiency is further improved. In addition, the lead-out terminal is made of a laminate of conductive patterns, and the connection area is much larger than if the electrode ends were exposed on both ends of the laminate, so the connection with printed circuit patterns etc. is extremely good. Yes, the reliability is very high. Furthermore, even in the case of a complex circuit configuration as shown in FIG. 6, the use of jumpers can be minimized to two, so if a hybrid integrated circuit board incorporating a multilayer capacitor according to the present invention is used, This greatly simplifies the design of the circuit pattern formed on the board, and provides many excellent effects such as efficient and high-density mounting design.

Note that the above embodiments are merely for illustrating the present invention, and therefore the number, shape, and dimensions of the dielectric layer and conductive pattern, and the size, shape, and position of the openings may be varied as necessary. Needless to say, it can be changed to

[Brief explanation of the drawing]

1A to 1H are plan views showing one manufacturing process of a multilayer capacitor constituting a hybrid integrated circuit board according to the present invention, and FIG. 2 is a schematic cross-sectional view taken along the line 2-2 of FIG. Figure 3 is a perspective view of Figure 1H;
FIG. 4 is a plan view showing another example of a multilayer capacitor constituting a hybrid integrated circuit board according to the present invention;
The figure is a schematic plan view illustrating a mode in which a hybrid integrated circuit using the hybrid integrated circuit board of the present invention is inserted into a printed circuit board, FIG. 6 is a circuit connection diagram of the hybrid integrated circuit of FIG. 5, and FIG. FIG. 8 is a plan view and a perspective view illustrating a state in which the hybrid integrated circuit is packaged. 1, 4, 9, 14: dielectric layer, 2, 5, 6, 1
0, 11, 15, 16: conductive pattern, 3, 7,
8, 12, 13: opening, 17, 19: multilayer capacitor, 22: printed circuit, _Q1 to _Q4 : transistor, R: resistor, _C1 to _C4 , _C1 ' to _C4 ': electrode extraction terminal.

Claims (1)

[Claims] 1 A multilayer capacitor formed by laminating a dielectric layer and a conductive pattern constituting an electrode, wherein the conductive pattern is connected to one plane of the outermost dielectric layer of the multilayer capacitor through an opening provided in the dielectric layer. A hybrid integrated circuit incorporating a multilayer capacitor, characterized by comprising a multilayer capacitor drawn upward to serve as an electrode lead terminal, and a printed circuit with a predetermined pattern formed on the one plane of the multilayer capacitor. substrate.