JPH022318B2 - - Google Patents
Info
- Publication number
- JPH022318B2 JPH022318B2 JP59170893A JP17089384A JPH022318B2 JP H022318 B2 JPH022318 B2 JP H022318B2 JP 59170893 A JP59170893 A JP 59170893A JP 17089384 A JP17089384 A JP 17089384A JP H022318 B2 JPH022318 B2 JP H022318B2
- Authority
- JP
- Japan
- Prior art keywords
- ceramic
- laminated
- ceramic capacitor
- multilayer
- green sheets
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000919 ceramic Substances 0.000 claims description 21
- 239000003985 ceramic capacitor Substances 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 9
- 239000010410 layer Substances 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000005245 sintering Methods 0.000 claims description 4
- 238000010304 firing Methods 0.000 claims description 3
- 238000010030 laminating Methods 0.000 claims description 3
- 239000011229 interlayer Substances 0.000 claims description 2
- 238000000465 moulding Methods 0.000 claims description 2
- 239000003990 capacitor Substances 0.000 description 9
- 239000000758 substrate Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Description
【発明の詳細な説明】
＜技術分野＞
本発明は、セラミツク多層配線基板の製造方法
に係わり、特に混成IC等に使用されるCR内蔵の
多層セラミツク配線基板の製造方法に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION <Technical Field> The present invention relates to a method of manufacturing a ceramic multilayer wiring board, and more particularly to a method of manufacturing a multilayer ceramic wiring board with a built-in CR for use in hybrid ICs and the like.
＜従来の技術＞
従来、混成ICを多層化し、高密度化を図る技
術として、セラミツク基板の表面に抵抗体を印刷
し、多層配線部分は下層の配線上に誘電ペースト
又は絶縁ペーストを印刷し、その上に上層の配線
を印刷形成する多段印刷法等が主に用いられてい
る。<Conventional technology> Conventionally, as a technology for multilayering hybrid ICs to increase density, a resistor is printed on the surface of a ceramic substrate, and dielectric paste or insulating paste is printed on the lower layer wiring for the multilayer wiring part. Mainly used is a multistage printing method in which upper layer wiring is printed on top of the wiring.
しかし、これらの方法では、小容量のコンデン
サの形成は、誘電ペースト又は絶縁ペーストを誘
電体として用いて行うことができるが、大容量の
コンデンサ及び高精度のコンデンサを形成するこ
とができない。したがつてこれらのコンデンサは
能動部品と共にセラミツク基板の表面にハンダ付
けによつて搭載され、混成IC上での占有面積も
大きく、混成ICの小型化への大きな障害となつ
ている。 However, with these methods, although small capacitance capacitors can be formed using dielectric paste or insulating paste as a dielectric, large capacitance capacitors and high precision capacitors cannot be formed. Therefore, these capacitors are mounted along with active components on the surface of a ceramic substrate by soldering, and occupy a large area on the hybrid IC, which is a major obstacle to miniaturization of the hybrid IC.
＜発明の目的＞
本発明の目的は、かかる従来技術の欠点を除去
し、大容量、且つ高精度のコンデンサを内蔵させ
たセラミツク多層配線基板の製造方法を提供する
ことにある。<Object of the Invention> An object of the present invention is to eliminate the drawbacks of the prior art and to provide a method for manufacturing a ceramic multilayer wiring board incorporating a large capacity and high precision capacitor.
＜発明の構成＞
本発明によれば、層間を電気的に接続するバイ
ア・ホール、抵抗体パターン及び回路パターンを
形成し、かつ、積層セラミツクコンデンサの外形
寸法に相当する形状の穴部を設けたセラミツク・
グリーンシートの複数枚を積層して積層体を形成
する工程と、上記積層体の穴部に積層セラミツク
コンデンサを挿入し、この積層体の上下両面又は
いずれか一面に上記積層セラミツクコンデンサの
電極並びに層間を電気的に接巳するバイア・ホー
ル、抵抗体パターン及び回路パターンを形成した
セラミツク・グリーンシートを積層し熱圧着して
一体化成形する工程と、上記成形体を上記積層セ
ラミツクコンデンサの焼結温度より低い温度で焼
成する工程とから成ることを特徴とするセラミツ
ク多層配線基板の製造方法が得られる。<Structure of the Invention> According to the present invention, via holes for electrically connecting layers, a resistor pattern, and a circuit pattern are formed, and a hole portion having a shape corresponding to the external dimensions of a multilayer ceramic capacitor is provided. Ceramic
A process of laminating a plurality of green sheets to form a laminate, inserting a laminated ceramic capacitor into the hole of the laminate, and attaching the electrodes and interlayers of the laminated ceramic capacitor to the upper and lower surfaces or either one of the upper and lower surfaces of the laminate. A process of laminating ceramic green sheets on which via holes for electrically interconnecting, resistor patterns, and circuit patterns are formed and integrally molding them by thermocompression bonding, and a process of sintering the molded body into the laminated ceramic capacitor. A method for manufacturing a ceramic multilayer wiring board is obtained, which is characterized by comprising a step of firing at a lower temperature.
＜実施例＞
以下、本発明を図面を用いて詳細に説明する。
第１図は本発明の一実施例で製造したCR内蔵の
セラミツク多層配線基板の分解模式図である。<Example> Hereinafter, the present invention will be explained in detail using the drawings.
FIG. 1 is an exploded schematic diagram of a ceramic multilayer wiring board with a built-in CR manufactured in one embodiment of the present invention.
まず、セラミツク・グリーンシートに、後工程
で内蔵する積層セラミツクコンデンサ１ａ，１ｂ
の縦・横寸法に相当する形状の角穴２ａ，２ｂと
層間の電気的接続用バイア・ホール（図示省略）
とを設けて穴付きグリーンシート３Ａを形成す
る。次に穴付きグリーンシート３Ａの片面にスク
リーン印刷手段にてAg／Pd系導電ペースト及び
RuO2系抵抗体ペーストを被着させて、回路パタ
ーン４、導電ペーストが充填されたバイア・ホー
ル及び抵抗体パターン５を形成する。次に前述の
穴付きグリーンシート３Ａとは印刷パターンが異
なり、かつ角穴２ａ，２ｂの形成位置が同一の穴
付きグリーンシート３Ｂを積層セラミツク・コン
デンサ１ａ，１ｂの厚み寸法に相当する枚数まで
積層し積層体３を形成した後、角穴２ａ，２ｂに
積層セラミツクコンデンサ１ａ，１ｂを挿入す
る。次に、積層セラミツクコンデンサ１ａ，１ｂ
の電極と層間の電気的接続用バイア・ホールとを
設けたセセラミツク・グリーンシート６Ａ，６Ｂ
に上記と同様に回路パターン４、導体ペーストが
充填されたバイア・ホール（図示省略）、及び抵
抗体パターン５を被着形成し、これらを前述の穴
付きグリーンシート３Ａ，３Ｂと、積層セラミツ
ク・コンデンサ１ａ，１ｂとの積層体３の上下両
面に各々複数枚積層した後、熱プレス機で圧着
し、一体化成形して成形体（図示省略）を形成す
る。次にこの成形体を脱バインダー処理した後、
成形体に内蔵させた積層セラミツクコンデンサ１
ａ，１ｂの焼結温度より低い温度で焼成（ピーク
温度800〜900℃、ピーク温度保持時間10分）す
る。この焼成により積層セラミツク・コンデンサ
１ａ，１ｂの電極及び各層間の回路パターン４は
バイア・ホールに充填された導体ペーストにより
電気的に接続され、CR内蔵のセラミツク多層配
線基板を製造することができる。 First, multilayer ceramic capacitors 1a and 1b are built into the ceramic green sheet in a later process.
square holes 2a, 2b with a shape corresponding to the vertical and horizontal dimensions of
A green sheet with holes 3A is formed. Next, one side of the holed green sheet 3A is coated with Ag/Pd-based conductive paste by screen printing.
A RuO 2 based resistor paste is deposited to form a circuit pattern 4, a via hole filled with conductive paste and a resistor pattern 5. Next, green sheets with holes 3B having a different printing pattern from the above-mentioned holed green sheets 3A but with the same formation positions of the square holes 2a and 2b are stacked up to a number corresponding to the thickness of the multilayer ceramic capacitors 1a and 1b. After forming the laminate 3, the multilayer ceramic capacitors 1a, 1b are inserted into the square holes 2a, 2b. Next, the multilayer ceramic capacitors 1a, 1b
Ceramic green sheets 6A and 6B provided with electrodes and via holes for electrical connection between layers.
A circuit pattern 4, a via hole filled with conductor paste (not shown), and a resistor pattern 5 are formed in the same manner as above, and these are bonded to the holed green sheets 3A, 3B and the laminated ceramic layer. After a plurality of capacitors 1a and 1b are laminated on both the upper and lower surfaces of the laminate 3, they are crimped with a hot press and integrally molded to form a molded body (not shown). Next, after debinding the molded body,
Multilayer ceramic capacitor built into a molded body 1
Calcinate at a temperature lower than the sintering temperature of a and 1b (peak temperature 800-900°C, peak temperature holding time 10 minutes). By this firing, the electrodes of the laminated ceramic capacitors 1a, 1b and the circuit pattern 4 between each layer are electrically connected by the conductive paste filled in the via holes, and a ceramic multilayer wiring board with a built-in CR can be manufactured.
＜発明の効果＞
以上、本発明によれば、焼結済みで、精度も明
確な積層セラミツクコンデンサをセラミツク誘電
体に内蔵させ、かつ積層セラミツクコンデンサの
焼結温度より低い温度で焼成するため、内蔵され
たコンデンサの高精度を維持することも、また低
容量から大容量に至る全範囲の積層セラミツク・
コンデンサを内蔵することができる。従つて、セ
ラミツク基板表面に積層セラミツクコンデンサを
搭載する必要がなく、セラミツク基板表面を大幅
に縮小することができ、混成ICの小型化、さら
に電子機器の小型化に大きく貢献することができ
る。<Effects of the Invention> As described above, according to the present invention, a sintered multilayer ceramic capacitor with clear precision is built into a ceramic dielectric, and the built-in ceramic capacitor is fired at a temperature lower than the sintering temperature of the multilayer ceramic capacitor. Maintaining the high precision of the capacitors manufactured by the manufacturer is also important in maintaining the high accuracy of the capacitors manufactured by the company.
A capacitor can be built-in. Therefore, there is no need to mount a laminated ceramic capacitor on the surface of the ceramic substrate, and the surface area of the ceramic substrate can be significantly reduced, making it possible to greatly contribute to the miniaturization of hybrid ICs and electronic devices.
第１図は本発明によるCR内蔵セラミツク多層
配線基板の分解斜視図。
１ａ，１ｂ……積層セラミツクコンデンサ、２
ａ，２ｂ……セラミツク・グリーンシート上の角
穴部、３Ａ，３Ｂ……穴付きグリーンシート、３
……積層体、４……回路パターン、５……抵抗体
パターン、６Ａ，６Ｂ……グリーンシート。
FIG. 1 is an exploded perspective view of a ceramic multilayer wiring board with a built-in CR according to the present invention. 1a, 1b...Multilayer ceramic capacitor, 2
a, 2b...square hole on ceramic green sheet, 3A, 3B...green sheet with hole, 3
...Laminated body, 4...Circuit pattern, 5...Resistor pattern, 6A, 6B...Green sheet.
Claims (1)
抗体パターン及び回路パターンを形成し、かつ積
層セラミツク・コンデンサの外形寸法に相当する
形状の穴部を設けたセラミツク・グリーンシート
の複数枚を積層して積層体を形成する工程と、前
記積層体の穴部に積層セラミツク・コンデンサを
挿入し、この積層体の上下両面又はいずれか一面
に前記積層セラミツク・コンデンサの電極並びに
層間を電気的に接続するバイア・ホール、抵抗体
パターン及び回路パターンを形成したセラミツ
ク・グリーンシートを積層し熱圧着して一体化成
形する工程と、前記成形体を前記積層セラミツ
ク・コンデンサの焼結温度より低い温度で焼成す
る工程とから成ることを特徴とするセラミツク多
層配線基板の製造方法。1 Laminated multiple ceramic green sheets in which via holes, resistor patterns, and circuit patterns are formed to electrically connect layers, and holes with a shape corresponding to the external dimensions of a multilayer ceramic capacitor are provided. inserting a laminated ceramic capacitor into the hole of the laminated body, and electrically connecting the electrodes and interlayers of the laminated ceramic capacitor to the upper and lower surfaces or either one of the upper and lower surfaces of the laminated body. A step of laminating ceramic green sheets on which via holes, resistor patterns, and circuit patterns are formed and integrally molding them by thermocompression bonding, and firing the molded body at a temperature lower than the sintering temperature of the laminated ceramic capacitor. 1. A method for manufacturing a ceramic multilayer wiring board, comprising the steps of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59170893A JPS6148996A (en) | 1984-08-16 | 1984-08-16 | Method of producing ceramic multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59170893A JPS6148996A (en) | 1984-08-16 | 1984-08-16 | Method of producing ceramic multilayer wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6148996A JPS6148996A (en) | 1986-03-10 |
| JPH022318B2 true JPH022318B2 (en) | 1990-01-17 |
Family
ID=15913267
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59170893A Granted JPS6148996A (en) | 1984-08-16 | 1984-08-16 | Method of producing ceramic multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6148996A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2555638B2 (en) * | 1987-10-07 | 1996-11-20 | 株式会社村田製作所 | Method for manufacturing multilayer ceramic substrate |
| JP2555639B2 (en) * | 1987-10-07 | 1996-11-20 | 株式会社村田製作所 | Method for manufacturing multilayer ceramic substrate |
| JPH0632384B2 (en) * | 1987-12-22 | 1994-04-27 | 株式会社住友金属セラミックス | Method for manufacturing laminated ceramic substrate |
-
1984
- 1984-08-16 JP JP59170893A patent/JPS6148996A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6148996A (en) | 1986-03-10 |
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