JP2006510233A - Printed wiring board having low-inductance embedded capacitor and manufacturing method thereof - Google Patents

Abstract

The printed wiring board (PWB) has stacked interlayer panels (1001, 1002, 1003,...) Composed of passive circuit elements (105). The passive element (105) can include a capacitor whose electrode termination is located within the footprint of the capacitor electrode (170, 180). Thus, the capacitor terminations are spaced closely apart, reducing the capacitor's contribution to the loop inductance in the interlayer. Also, the presence of the capacitor termination in the electrode footprint reduces the PWB board surface area used when forming the capacitor. The capacitor terminations are connected by circuit conductors (1021, 1022).

Description

  The technical field is ceramic capacitors. More specifically, the technical field includes low inductance, space efficient ceramic capacitors that can be embedded in printed wiring boards.

(Cross-reference of related applications)
This application is related to the following applications: Assigned agent directory number EL-0495, U.S. Patent Application No. 60 / 418,045, filed on Oct. 11, 2002 to the U.S. Patent and Trademark Office, entitled "Co-fired ceramic for use in printed wiring boards""Manufacturing method of capacitor and ceramic capacitor".

  By embedding passive circuit elements in a multilayer printed wiring board (PWB), the circuit size is reduced and the circuit performance is improved. Passive circuit elements are usually embedded in stacked panels. These panels are connected by conductive vias, and a stack of panels forms a multilayer printed wiring board. The panel is generally referred to as an “interlayer panel”.

  Passive circuit elements, such as capacitors, embedded in the interlayer panels cause circuit loop inductance (also known as “lead inductance”). High circuit loop inductance is undesirable in most applications. Low circuit loop inductance is also particularly desirable in circuits used in high frequency and high speed applications. The capacitor's contribution to the loop inductance is caused by the capacitor's self-inductance and its termination isolation. The “termination” of a capacitor can generally be defined as the point where a circuit conductor, such as a conductive trace or a conductive lead, is connected to the capacitor electrode. Conventional capacitor elements have one end located on one edge of the capacitor and another end located on the opposite edge of the capacitor. In conventional capacitor elements, the location of the termination is generally not within the plan view surface area or the “footprint” of the capacitor electrode. By positioning the termination at the opposite edge of the capacitor, the termination isolation in the capacitor is maximized and the loop inductance is correspondingly increased.

  US Patent Publication (Patent Document 1) (Singhdeo et al.) Discloses a glass capacitor 60 having a large termination separation. As shown in FIG. 6 of Singdeo, an external electrode 66 is connected to the internal electrodes 62 and 64 at opposite ends of the glass capacitor 60. Therefore, termination isolation is maximized in capacitor 60.

US Pat. No. 4,687,540

  In addition to low circuit loop inductance, space is also important for PWB interlayer panels. Therefore, the surface area occupied by the capacitor in the intermediate layer panel must be relatively small. Positioning the capacitor termination at the opposite end of the capacitor has the additional disadvantage of increasing the overall capacitor footprint. As a result, the space occupied by the capacitor in the printed wiring board increases.

  According to the first embodiment, the printed wiring board includes a first circuit conductor extending through at least part of the printed wiring board, and a second circuit conductor extending through at least part of the printed wiring board; A plurality of stacked intermediate layer panels. The one or more interlayer panels are first electrodes formed from foil and having terminations, the first circuit conductor being coupled to the first electrodes at the termination of the first electrodes, The termination of the electrode is located within the footprint of the first electrode, the first electrode, at least one dielectric disposed on the first electrode, spaced from the first electrode and terminated And a second electrode. The second electrode, the first electrode, and the dielectric form a capacitor. The second electrode capacitor termination is preferably located within the footprint of the second electrode.

  According to the first embodiment, by positioning the first electrode capacitor termination within the footprint of the first electrode, the spacing between the first electrode capacitor termination and the second electrode capacitor termination is reduced. . By positioning the end of the second electrode within the footprint of the second electrode, the end separation can be further reduced. By reducing the termination isolation, the capacitor contribution to the circuit loop inductance is reduced. Low inductance capacitors are particularly advantageous in high frequency and high speed PWB applications. In addition, since the termination connection is not necessary at the peripheral edge of the capacitor, the printed wiring board area occupied by the capacitor is reduced.

  According to an alternative embodiment, the printed wiring board includes at least one intermediate layer panel, the intermediate layer panel comprising a two-layer dielectric capacitor with three electrodes, and the location of the termination of each electrode is an individual electrode foot. In print. The two-layer dielectric capacitor interlayer panel conveys the advantages of low circuit loop inductance and reduces the footprint of the PWB board. In addition, in the two-layer dielectric capacitor embodiment, additional dielectric layers and additional electrodes increase the capacitance density.

  Embodiments of a method for manufacturing a printed wiring board include forming a plurality of stacked interlayer panels. Forming at least one of the interlayer panels includes forming a dielectric on the metal foil, forming a first electrode from the foil, the first electrode having a termination, Forming a second electrode on the dielectric, the second electrode having a termination, wherein the first electrode, the second electrode, and the dielectric include a capacitor. Form. A first circuit conductor is formed. The first circuit conductor extends through at least a portion of the printed wiring board and contacts the end of the first electrode, the position of the end of the first electrode being within the footprint of the first electrode. A second circuit conductor is also formed. The second circuit conductor contacts the end of the second electrode and extends through at least a portion of the printed wiring board. The second electrode termination may be located within the footprint of the second electrode.

  According to the method for manufacturing a printed wiring board, a printed wiring board having an intermediate layer panel including a capacitor having a small contribution to circuit loop inductance can be obtained. In addition, the board area of the printed wiring board occupied by the intermediate layer panel manufactured by this method is relatively small.

  In the detailed description, reference is made to the accompanying drawings. In the drawings, like numerals refer to like elements.

  1A to 1G show a general manufacturing method of the printed wiring board 1000 (FIG. 1H). FIG. 1H shows a completed printed wiring board 1000. The printed wiring board 1000 includes stacked layers 1001, 1002, 1003,. . . The circuit element is embedded in each layer. Stacked layers 1001, 1002, 1003,. . . Is commonly referred to as an “interlayer panel”. 1A to 1G show a method for manufacturing the intermediate layer panel 100 of the first embodiment before the intermediate layer panel 100 is combined into a printed wiring board 1000. FIG. 1I is an exploded view of the intermediate layer panel 1001. The intermediate layer panel 1001 corresponds to the intermediate layer panel 100 after the intermediate layer panel 100 is combined into the printed wiring board 1000.

  Shown in FIGS. 1A-1G are steps in the manufacture of an intermediate panel 100 having a capacitor 105 (FIG. 1G shows the completed intermediate panel 100). Specific embodiments of the interlayer panel 100 are also described in detail below. The single capacitor 105 is formed by a method described later. However, each of the interlayer panels 1001, 1002, 1003 includes many different types of separate capacitors. These capacitors are arranged in various ways in the interlayer panel 100 along with other passive elements. Also, the printed wiring board 1000 shown in FIG. 1H may include any number of stacked interlayer panels and conductive interconnections between the panels.

  Shown in FIGS. 1A and 1B is a first stage in the manufacture of the interlayer panel 100. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along line 1B-1B in the side view from FIG. 1A. In FIGS. 1A and 1B, a metal foil 110 is provided. The foil 110 may have a large surface area, and the foil 110 can be used to make a number of passive elements such as capacitors. The foil 110 may be of a type generally available in the printed wiring board industry. For example, the foil 110 may be copper, copper-invar-copper, invar, nickel, nickel-coated copper, or other metals having melting points above the firing temperature for thick film pastes. Preferred foils include foils made primarily of copper. For example, reverse processed copper foil, double processed copper foil, and other foils commonly used in the multilayer printed wiring board industry. The thickness of the foil 110 ranges, for example, from about 1 to 100 microns, preferably from 3 to 75 microns, and most preferably from 12 to 36 microns, which is a copper foil between about 1/3 ounce and 1 ounce. Correspond.

  The foil 110 may be preprocessed by applying a base print 112. The base print 112 is a relatively thin layer applied to the component surface of the foil 110. In FIG. 1B, the base print 112 is shown as a surface coating on the foil 110. The base print 112 adheres well to the metal foil 110 and the layer deposited over the base print 112. The underprint 112 is formed, for example, by applying a paste to the foil 110 and baking it at a temperature lower than the softening point of the foil 110. The paste may be printed as an open coating that covers the entire surface of the foil 110 or may be printed on selected areas of the foil 110. In general, it is more economical to print the base printing paste on a selected area of the foil. However, when the copper foil 110 is used with the copper underprint 112, the oxidative corrosion of the copper foil is suppressed by the glass in the copper underprint paste. Therefore, when using oxygen-doped firing, it may be preferable to coat the entire surface of foil 110.

  Referring to FIG. 1B, a dielectric material is screen printed on the pretreated foil 110 to form a first dielectric layer 120 on the foil 110. The dielectric material may be, for example, a thick film dielectric ink. The dielectric ink may be formed from, for example, a paste.

The first dielectric layer 120 is dried, and the second dielectric layer 122 is applied and dried. During molding, a first aperture 124 and a second aperture 126 are included in the individual dielectric layers 120, 122. Apertures 124 and 126 are sometimes referred to as “through holes” or “clearance holes”. In the embodiment shown in FIGS. 1A and 1B, the apertures 124, 126 are circular as shown in the plan view of FIG. 1A. As other shapes, for example, polygonal shapes and the like are possible. The circular apertures 124, 126 shown in the embodiment of FIGS. 1A and 1B are spaced apart by a distance d ₁ , and the diameter of each aperture is d ₂ . The aperture diameter d ₂ may be larger than, for example, the size of a drill or laser spot that is subsequently used to form a via in the manufactured article. The via formation will be described later with reference to FIG. 1H. However, the diameters of the apertures 124, 126 need not be the same. The distance d ₁ may be selected, for example, to be equal to the distance d ₂ plus further increments. The incremental distance is preferably selected such that the desired minimum separation of the first and second apertures 124, 126 is maintained.

  Instead, in an alternative embodiment, a single layer of dielectric material may be deposited through a coarse mesh screen to provide a dielectric layer of equivalent thickness in a single screen printing step. good.

  A conductive layer 130 is formed over the second dielectric layer 122 and dried. The conductive layer 130 can be formed, for example, by screen printing a thick film metal ink. The conductive layer 130 is formed by aligning the aperture 132 over the first aperture or through hole 124. Aperture 132 is preferably concentric with aperture 124. However, in the case of apertures molded into circles and other polygons, other arrangements may be satisfactory. The aperture 132 has a larger surface area than the first aperture 124. A portion of the conductive layer 130 extends through the second aperture 126 and contacts the foil 110.

  Next, the first dielectric layer 120, the second dielectric layer 122, and the conductive layer 130 are baked. 1C and 1D show the article after firing. Baking the dielectric layers 120, 122 and the conductive layer 130 simultaneously without firing the dielectric layers 120, 122 first may be referred to as “co-firing” the dielectric and conductive layers. . As a result of the co-firing, a dielectric 128 is obtained. Thick film dielectric layers 120, 122 are, for example, from a high dielectric constant functional phase, such as barium titanate, and an additive that modifies dielectric properties, such as zirconium oxide, mixed with a glass-ceramic-frit phase. It may be. During co-firing, the glass-ceramic-frit phase softens, wets and fuses the functional and additive phases to form a dispersion of functional and modifying additives in the glass-ceramic matrix To do. At the same time, the metal electrode powder of the conductive layer 130 is wetted by the softened glass-ceramic-frit phase and the separate phases are sintered together. In general, as shown in FIG. 1C, the surface area of the dielectric 128 should be greater than that of the conductive layer 130.

  In FIG. 1E, the resulting article is inverted and laminated to the laminate material 140. The component side of the foil 110 (which contacts the dielectric 128) is laminated to the laminate material 140. Lamination can be performed, for example, with a standard printing wiring board process using FR4 prepreg. In one embodiment, a 106 epoxy type prepreg may be used. The foil 142 may be attached to the laminated material 140 to be a surface for producing a circuit such as a signal layer, for example.

  The dielectric prepreg and laminate material can be any type of dielectric material. For example, standard epoxy, high Tg epoxy, polyimide, polytetrafluoroethylene, cyanate ester resin, filled resin system, BT epoxy, and other resins and laminates that insulate between circuit layers.

  After lamination, a photoresist is applied to foil 110 and foil 142 shown in FIG. 1E. The foils 110 and 142 are drawn and etched. The photoresist is then stripped using, for example, standard printing wiring board processes and conditions. As a result of the etching step, an interlayer panel 100 is obtained. FIG. 1F is a plan view of the intermediate layer panel 100. FIG. 1F is seen from the direction of arrow A in FIG. 1G. 1G is a cross-sectional view taken along line 1G-1G in FIG. 1F. The interlayer panel 100 can be laminated on another printed wiring board core by forming a multilayer printed wiring board using a prepreg and standard lamination conditions.

  The etching step results in a trench 116 that isolates the etched foil first portion 114 from the second portion 118. Portions 114 and 118 are portions of foil 110 that remain after etching. Also, the trench 116 blocks electrical contact between the first conductive layer 130 and the first portion 114. As shown in FIG. 1F, the peripheral edge 119 is also etched back, so that the dielectric 128 has a slightly larger surface area than the first portion 114. The conductive layer 130 remains in contact with the second portion 118. The etching of the foil 142 results in a circuit 143 that may then be used to connect to the capacitor termination.

  Referring to FIG. 1H, the drawn interlayer panel 100 shown in FIGS. 1F and 1G is laminated together with other drawn interlayer panels. FIG. 1H is a cross-sectional view of a completed printed wiring board 1000 in a side view. The printed wiring board 1000 includes intermediate layer panels 1001, 1002, 1003. . . It is included. The intermediate layer panel 1001 schematically represents the intermediate layer panel 100 formed by the above-described method, and is obtained after the intermediate layer panel 100 is combined into a printed wiring board 1000. A block representation of the capacitor 105 is also shown in the interlayer panel 1001.

  The intermediate layer panels used to form the printed wiring board 1000 can be stacked and pressed together. The interlayer panels can be bonded together using, for example, a dielectric prepreg. Each interlayer panel can have a different design. For example, the arrangement of circuit elements is different. The term “interlayer panel” does not mean that the panel must be sandwiched inside the printed wiring board 1000. The intermediate layer panel can also be positioned at the end of the printed wiring board 1000. The printed wiring board 1000 may be laminated in a plurality of stages. For example, the sub-assembly of the interlayer panel may be processed and laminated. Thereafter, one or more subassemblies can be laminated together to form the finished printed wiring board 1000.

  Intermediate layer panels 1001, 1002, 1003. . . May be connected by an interconnect circuit generally referred to as a “circuit conductor”. The circuit conductor can be formed, for example, after all the interlayer panels have been laminated together. Alternatively, all the middle layer panels 1001, 1002, 1003. . . The circuit conductors can be formed in sub-assemblies of the interlayer panels or in individual panels prior to combining into a finished printed wiring board 1000.

  The interconnect circuit between the intermediate layers can include, for example, one or more conductive vias that extend through all or part of the printed wiring board 1000. In FIG. 1H, first and second circuit conductors 1021, 1022 extend through the entire printed wiring board 1000 and are in the form of through-hole conductive vias. The first and second conductive vias 1021, 1022 can be formed, for example, by laser or mechanical drilling through the laminated interlayer panels. Next, the hole formed by drilling is plated with a conductive material. The resulting conductive vias 1021, 1022 extend through the entire printed wiring board 1000, but are usually referred to as “plated through holes”, and typically after all the interlayer panels have been laminated together. It is formed.

  Circuit conductors may also extend through sub-assemblies of interlayer panels or through individual panels. Via circuit conductors that extend through only a portion of the printed wiring board 1000 are commonly referred to as “buried vias”. Typically, the buried vias are drilled and plated through the sub-assembly of the intermediate panel before the intermediate panel sub-assembly is assembled into a printed wiring board. Conductive vias formed in individual interlayer panels are commonly referred to as “micro vias” and may be used, for example, to terminate capacitors in interlayer panels.

  After all the interconnections are formed and all sub-assemblies of the interlayer panels or individual interlayer panels are laminated together, the printed wiring board 1000 is completed. The printed wiring board 1000 shown in FIG. 1H includes a configuration in which intermediate layer panels 1001, 1002, and 1003 are stacked, and these are stacked and connected by circuit conductors 1021 and 1022. However, any number of intermediate layer panels may be included in the printed wiring board according to the present embodiment.

  FIG. 1I is an exploded view of the intermediate panel 1001 shown in FIG. 1H. FIG. 1I also shows part of the first circuit conductor 1021 and part of the second circuit conductor 1022. These may extend through the printed wiring board 1000 as shown in FIG. 1H. The intermediate layer panel 1001 includes a completed capacitor 105, and its electrode termination is connected to the first and second circuit conductors 1021 and 1022.

  After forming the circuit conductors 1021, 1022, the one used to form the portion 114 (FIG. 1G) forms the first electrode 170. First electrode 170 is electrically coupled to first circuit conductor 1021. What is used to form conductive layer 130 and portion 118 (FIG. 1G) forms second electrode 180. Second electrode 180 is electrically coupled to second circuit conductor 1022.

  One completed capacitor 105 is shown as part of the completed interlayer panel 1001. However, many capacitors and other circuit components having different designs and arranged in different patterns can be included in the embodiment of the interlayer panel 1001.

  The first and second circuit conductors 1021, 1022 shown in FIG. 1I are shown as part of the first and second plated through-hole vias 1021, 1022 shown in FIG. 1H. However, the circuit conductors in the interlayer panel 1001 can be, for example, buried vias that extend through the sub-assembly of the interlayer panel in the printed wiring board 1000. The first and second circuit conductors 1021 and 1022 may be vias that extend through only the intermediate panel 1001, for example. This is, for example, a microvia that is used to terminate the capacitor 105.

  1J is a cross-sectional view taken along line 1J-1J in FIG. 1I. FIG. 1J shows the capacitor 105 in a plan view. As shown in FIGS. 1I and 1J, the termination of the first electrode 170 is located at the through hole aperture of the dielectric 128, where the first circuit conductor 1021 is connected to the first electrode 170. Electrically coupled. The end of the second electrode 180 is positioned where the second circuit conductor 1022 is coupled to the second electrode 180. With particular reference to FIG. 1J, the ends of the electrodes 170, 180 are positioned within the plan view surface area, or “footprint” of the individual electrodes 170, 180.

The distance between the ends of the electrodes 170 and 180 is indicated as d, the width of the first electrode 170 is I ₁ , and the width of the second electrode 180 is I ₂ . The end interval d corresponds to the interval d ₁ shown in FIG. 1A. In the embodiment described herein, the termination interval d can be much smaller than the widths I ₁ and I _{2 of} the first electrode 170 and the second electrode 180. For example, the distance d may be less than half of the widths I ₁ and I ₂ . The spacing d may be selected to be equal, for example, to the sum of the aperture radii of the via conductors 1021, 1022 plus a further increment determined, for example, by the screen printing alignment capability. Further increments may generally be selected to maintain a preferred or minimal amount of dielectric between the apertures to provide a margin of error for alignment problems inherent in screen printing.

  According to the above-described embodiment, the terminations positioned in the electrode footprint may be arranged at a relatively small distance from each other, so that the contribution of the capacitor 105 to the circuit inductance is reduced.

  The following examples illustrate specific materials and processes used to carry out the general method of manufacturing the printed wiring board 1000 shown in FIGS.

Example 1
A specific embodiment of the interlayer panel 1001 will be described with reference to FIGS. In this embodiment, the foil 110 is a copper foil. The type of copper foil 110 was a commercially available grade 1 ounce copper foil. Pretreatment of the copper foil 110 was performed by applying a copper underprint paste onto selected areas of the foil 110. The resulting product was then fired at 900 ° C. nitrogen for 10 minutes at peak temperature. The total cycle time was approximately 1 hour, and as a result, the base print 112 was formed.

In FIGS. 1A and 1B, thick film dielectric ink was screen printed through a 400 mesh screen onto a pretreated copper foil 110 to form a 198 mm × 230 mm first dielectric layer 120. The wet printed thickness of the first dielectric layer 120 was approximately 12-15 microns. The first dielectric layer 120 was dried at 125 ° C. for approximately 10 minutes. The second dielectric layer 122 was then applied through a 400 mesh screen by screen printing. Subsequently, another drying step was performed at 125 ° C. The thick film dielectric ink included a barium titanate component, a zirconium oxide component, and a glass-ceramic phase. The distance d ₁ between the first and second apertures 124, 126 was approximately 41 mils. The diameter d ₂ of the apertures 124,126 was approximately 26 mils.

  Referring to FIGS. 1C and 1D, a thick film copper electrode ink layer 130 was printed on the dielectric layer 122 through a 400 mesh screen and then dried at 125 ° C. for approximately 10 minutes. Referring to FIG. 1C, the layer 130 had a plan view dimension of about 178 mm × 210 mm. The size of layer 130 is approximately 10 mils smaller than dielectric 128 around its peripheral edge. The printed conductive layer 130 had a thickness of about 5 microns. The resulting structure was then co-fired with a thick film nitrogen profile at 900 ° C. for 10 minutes at the peak temperature. The nitrogen profile contained less than 50 ppm oxygen in the burnout zone, 2-10 ppm oxygen in the calcining zone, and the overall cycle time was 1 hour.

  With reference to FIG. 1E, the substrate laminate material 140 of the FR4 printed wiring board was laminated on the component surface of the foil 110. A copper foil 142 was formed on the laminate material 140. Lamination conditions were in a vacuum chamber evacuated to 28 inches in terms of mercury at 185 ° C. and 208 psig for 1 hour. A silicone rubber press pad and a smooth PTFE filled glass release sheet were brought into contact with the foil 110 to prevent the epoxy from adhering the laminated plates together.

  Referring to FIGS. 1F and 1G, a photoresist was applied to foils 110 and 142, drawn, etched, and then the photoresist was peeled to form intermediate layer panel 100. The trench 116 had an inner diameter of approximately 36 mils and an outer diameter of approximately 46 mils.

  Referring to FIG. 1H, printed wiring board 1000 was then formed using intermediate layer panel 100. In order to form the printed wiring board 1000, the intermediate layer panel 100 was laminated together with other intermediate layer panels to form a stacked configuration. Each intermediate panel combined into a printed wiring board 1000 contained an interconnect circuit. Circuit components in the interlayer panel were connected to buried vias, through hole vias, or both. Circuit conductors 1021, 1022 are plated by drilling 16 mil (16/1000 inch) diameter through holes and copper on the via walls to a thickness of approximately 25 microns (1 mil or 1/1000 inch). To form.

  Referring to FIG. 1I, first and second vias 1021, 1022 are coupled to first and second electrodes 170, 180, respectively.

In this example, the thick film dielectric material had the following composition.
Barium titanate powder: 64.18%
Zirconium oxide powder: 3.78%
Glass A: 11.63%
Ethylcellulose: 0.86%
Texanol: 18.21%
Barium acid powder: 0.84%
Phosphate lubricant: 0.5%
The composition of glass A was as follows.
Germanium oxide: 21.5%
Lead tetroxide: 78.5%

The composition of glass A corresponded to Pb ₅ Ge ₃ O ₁₁ . This precipitated during co-firing and the dielectric constant was approximately 70-150. The composition of the thick film copper electrode ink was as follows.
Copper powder: 55.1%
Glass A: 1.6%
Cuprous oxide powder: 5.6%
Ethylcellulose T-200: 1.7%
Texanol: 36.0%.

  The capacitor design shown in the first embodiment and its alternatives described above reduces termination isolation and correspondingly contributes less to circuit loop inductance. Low inductance circuits are desirable in various applications. For example, low inductance circuits are particularly desirable in high frequency and high speed applications. In addition, according to the first embodiment described above and its alternatives, no termination connection is required at the peripheral edge of the capacitor. By this aspect, the printed wiring board area required for accommodating the capacitor is reduced. With this feature, the number of capacitors incorporated in the printed wiring board can be increased. Alternatively, a printed wiring board that requires a specified capacitance can be made smaller than a printed wiring board having a capacitor termination at the peripheral edge of the electrode.

  2A to 2D show a method for manufacturing the intermediate layer panel 2001 of the second embodiment. The completed capacitor intermediate layer panel 2001 includes a capacitor 205. The capacitor intermediate layer panel 2001 is shown in FIG. 2D as a separate exploded sectional view. The intermediate layer panel 2001 may be combined into a multilayer printed wiring board, for example, the printed wiring board 1000 shown in FIG. 1H. The intermediate layer panel 2001 has two layers of dielectrics and three electrodes. A two-layer dielectric design provides a high capacitance density for capacitor 205. A two-layer dielectric can provide, for example, a capacitance density of at least twice when compared to a single-layer capacitor design.

  2A is a cross-sectional view illustrating a stage in the manufacture of the interlayer panel 2001 illustrated in FIG. 2D. The article shown in FIG. 2A includes a foil 210, a first dielectric layer 228, and a first conductive layer 230. The first dielectric layer 228 includes a first aperture 229 and a second aperture 231. The article of FIG. 2A generally corresponds to the article shown in FIG. 1D and can be manufactured in a similar manner. In addition, however, a second dielectric layer 240 is formed on the conductive electrode layer 230 and dried. The formation of the second dielectric layer 240 is performed by aligning the first and second apertures 242 and 244 on the first and second apertures 229 and 231 respectively. The first and second apertures 229, 231 and 242 and 244 may have a circular shape when viewed from a plan perspective view, for example. Other shapes such as polygonal shapes may be used.

  Referring to FIG. 2B, a second conductive layer 250 is formed on the dielectric layer 240. The second conductive layer 250 includes an aperture 252 that coincides with the aperture 244. The resulting article is then fired. Co-firing of the conductive layer 250 and the dielectric layer 240 is a preferred firing method. FIG. 2B shows the article after firing. As a result of firing, a single dielectric 248 is formed from the dielectric layers 228 and 240. This is because the boundary between dielectric layers 228 and 240 is effectively removed during co-firing. A single dielectric 248 can be described as a “two-layer” dielectric. This is because it functions to separate the three electrodes in the finished interlayer panel 2001.

  In this embodiment, the firing can be performed in one or more cases. For example, co-firing the article (ie, the dielectric layer 228 under the conductive layer 230 has not been pre-fired) can be performed after forming the first conductive layer 230, and the article can be Baking again can be performed after the second conductive layer 250 is formed. Alternatively, the first co-firing of the article can be performed after the second conductive layer 250 is formed.

  As shown in FIG. 2C, the component surface of the foil 210 is laminated to the laminate material 260. Laminate material 260 can have, for example, the same composition as the laminate material described above with reference to FIGS. The foil 262 may be attached to the laminated material 260. The foil 262 may be used to obtain a surface for forming a circuit and a connection to the capacitor electrode.

  Referring to FIGS. 2C and 2D, a photoresist is applied to foil 210 and foil 262 after lamination. The foils 210 and 262 are then drawn and etched, and then the photoresist is stripped. The size to etch the foil 210 is preferably smaller than the dielectric 248. This is similar to the etching process for the foil 110 shown in FIG. 1F. The trench 216 is also etched in the foil 210. The trench 216 may be annular, for example. This is similar to the case of the trench 116 shown in FIG. 1F. FIG. 2D shows the resulting interlayer panel 2001.

  FIG. 2D is a cross-sectional view in a side view of the completed interlayer panel 2001 and includes a capacitor 205. The intermediate layer panel 2001 is suitable for integration into a printed wiring board. The intermediate layer panel 2001 of FIG. 2D is shown separately from the multilayer printed wiring board in order to show details of the intermediate layer panel 2001. Further, the intermediate layer panel 2001 may be combined into a sub-assembly of the intermediate layer panel.

  The foil 262 (FIG. 2C) may be etched to form a circuit 263 (FIG. 2D) that may be used to connect to the end of the capacitor 205. After etching, the resulting article may be laminated together with other interlayer panels that contain circuits such as passive circuit elements. As a result, a multilayer printed wiring board or a subassembly of an intermediate layer panel used in the multilayer printed wiring board is formed. In FIG. 2D, the first circuit conductor 2021 and the second circuit conductor 2022 are formed so as to extend through the intermediate layer panel 2001. The first and second circuit conductors 2021 and 2022 can be, for example, through-hole plated vias formed after the intermediate layer panel 2001 is combined into a printed wiring board. The first and second circuit conductors 2021, 2022 may also be buried vias that extend through a sub-assembly of the interlayer panel including the interlayer panel 2002. Alternatively, the circuit conductors 2021 and 2022 can be microvias that extend through only the interlayer panel 2001. Microvias can be formed prior to combining the interlayer panel 2001 into a sub-assembly of the interlayer panel.

  After etching the foil 210 and after forming the first and second circuit conductors 2021, 2022, the capacitor 205 (FIG. 2D) includes a first electrode 281, a two-layer dielectric 248, a second electrode 282. , And a third electrode 283. The first electrode 281 and the third electrode 283 are electrically connected to each other and electrically connected to the first circuit conductor 2021. The second electrode 282 is electrically connected to the second circuit conductor 2022. The second electrode 282 is electrically insulated from the first electrode 281 by the trench 216.

  As shown in FIG. 2D, the terminations of the first electrode 281 and the third electrode 283 are positioned at the through hole apertures of both dielectric layers included in the two-layer dielectric 248. Here, the first circuit conductor 2021 is electrically coupled to the first and third electrodes 281 and 283. Similarly, the termination of the second electrode 282 is at the location where the second circuit conductor 2022 is electrically coupled to the second electrode 282, i.e., through-through in both dielectric layers included in the dielectric 248. Positioned in the hall aperture. Advantageously, the terminations of the first electrode 281, the second electrode 282, and the third electrode 283 may all be located within their individual electrode footprint.

  The three-electrode / two-layer dielectric capacitor 205 has a high capacitance density in addition to a small contribution to circuit loop inductance. The small contribution to the circuit loop inductance is due to the reduced termination isolation achieved by positioning the capacitor terminations within their individual capacitor electrode footprints. In addition, since the capacitor termination connection need not be on the peripheral edge of capacitor 205, the PWB board area occupied by capacitor 205 is reduced.

  FIG. 3A is a cross-sectional view in a side view of a capacitor interlayer panel 3001 of the third embodiment having a capacitor 305. Capacitor 305 has a first electrode 310, a dielectric 320, and a second electrode 330 formed from foil. The first electrode 310 is isolated from the second electrode 330 by the trench 312. Capacitor 305 generally corresponds in configuration to capacitor 105 shown in FIG. 1H, except that only one clearance hole or aperture 322 is required in dielectric 320. No clearance hole is required in the second electrode 330 to connect the first circuit conductor 3021 to the first electrode 310. Instead, a first circuit conductor 3021 and a second circuit conductor 3022 extend from the surface of the first electrode 310 opposite the component surface of the first electrode 310.

  The intermediate layer panel 3001 can be formed in the same manner as the intermediate layer panel 1001 shown in FIGS. A dielectric layer corresponding to the dielectric 320 is deposited on the foil. A conductive layer corresponding to the second electrode 330 is deposited on the dielectric layer. The dielectric layer can be formed, for example, in one or two screen printing steps. Next, the dielectric layer and the conductive layer are co-fired. The resulting article is laminated to the laminate material 341 with the component side down to form a laminate structure. Next, a photoresist is applied to the foil 310 and the foil 310 is etched to form a trench 312. As a result, the first electrode 310 is formed by separating it from the second electrode 330.

  The article can then be laminated to the laminate material 340. This is done with the “foil surface” of the first electrode 310 (ie, the surface opposite the component surface) facing the laminate material 340. A foil is applied to the laminate material 340. The circuit may be formed by etching the foil. Next, a first circuit conductor 3021 and a second circuit conductor 3022 are formed in the resulting article. Thus, the intermediate layer panel 3001 is completed. The interlayer panel 3001 can be combined into a multilayer printed wiring board or combined with other interlayer panels to form a multilayer subassembly. In general, an interlayer panel including two layers, eg, an interlayer panel 3001 having laminate layers 340 and 341, can also be referred to as a “subassembly”. In this specification, the term “interlayer panel” is used as a general term to indicate a panel that is laminated to either one or two sides of a foil electrode.

The first and second circuit conductors 3021 and 3022 are formed by using, for example, a CO ₂ laser to connect the first and second circuit conductors 3021 and 3022 to the first and second electrodes 310 and 330, the electrode 310. , 330 can be terminated without damaging it. Next, a conductive material is plated in the hole formed by the drill operation to form the first and second circuit conductors 3021 and 3022. First and second circuit conductors 3021 and 3022 are shown as plated vias.

  As shown in FIG. 3A, the second electrode 330 may be in contact with a portion 314 of the foil 310 because the dielectric 320 only requires one clearance through hole 322. .

3B is a cross-sectional view taken along line 3B-3B in FIG. 3A. Terminals of the first and second electrodes 310 and 330 (the second electrode 330 is indicated by a broken line) (the first and second circuit conductors 3021 and 3022 are in contact with the electrodes 310 and 330, respectively) are And located in the footprint of the second electrodes 310,330. The distance between the ends of the electrodes 310 and 330 is indicated by d, the width of the first electrode 310 is l ₁ , and the width of the second electrode 330 is l ₂ . In this embodiment and the remaining embodiments described herein, the termination spacing d is advantageously much smaller than the widths l ₁ , l _{2 of} the first and second electrodes 310, 330. As a result, the contribution from the capacitor 305 to the circuit loop inductance is small. The use area of the printed wiring board is also reduced. This is because it is not necessary to connect at the edges of the electrodes 310 and 330.

  FIG. 4 is a cross-sectional view in a side view showing an intermediate panel 4001 of the fourth embodiment having a capacitor 405. Capacitor 405 has two dielectric layers and three electrodes. The intermediate layer panel 4001 may be combined into a printed wiring board, such as the printed wiring board 1000 shown in FIG. 1H, or a sub-assembly of the intermediate layer panel.

  The capacitor 405 includes a first electrode 410 formed from a foil, a two-layer dielectric 420, a second electrode 430, and a third electrode 440. The first electrode 410 is isolated from the second electrode 430 by a trench 416. The third electrode 440 is electrically coupled to the first electrode 410 through a clearance hole aperture 423 that extends through both layers of the two-layer dielectric 420. First electrode 410 is electrically coupled to first circuit conductor 4021. Second electrode 430 is electrically coupled to second circuit conductor 4022. The capacitor 405 has a laminated material 451 laminated on one surface thereof. Further, the laminate material 450 may be laminated on the article, and as a result, the intermediate layer panel 4001 becomes a “subassembly”. This is as described above. Alternatively, the articles can be directly combined into a printed wiring board without being laminated on the laminated material 450. When the laminated material 450 is used in the intermediate layer panel 4001, the circuit 453 may be formed from a foil on the laminated material 450. Since circuit 453 is included, a connection may be formed at the end of capacitor 405 via first and second circuit conductors 4021 and 4022.

  Capacitor 405 generally corresponds in configuration to capacitor 205 shown in FIG. 2D, except that clearance through holes are not required in third electrode 440. Instead, first and second conductive vias 4021, 4022 extend from the foil surface of the first electrode 410.

  The capacitor 405 of the intermediate layer panel 4001 can be formed in the same manner as the capacitor 205 of the intermediate layer panel 2001 shown in FIG. 2D. A first dielectric layer (indicated by reference numeral 421) is formed on the foil in one or two screen printing steps. Next, the dielectric layer 421 is dried. A first conductive layer corresponding to the second electrode 430 is formed on the first dielectric layer 421. The resulting article is then cofired. A second dielectric layer (indicated by reference numeral 422) is formed on the first conductive layer and dried. Next, a third electrode 440 corresponding to the second conductive layer is formed on the second dielectric layer 422. The resulting article is then cofired. Co-firing generally results in a single two-layer dielectric structure 420. In FIG. 4, separate dielectric layers 421, 422 are shown to illustrate the steps involved in forming the capacitor 405. Also, co-firing generally removes the boundaries between the dielectric layers.

  After the co-firing, the laminated material 451 is laminated on the foil with the component surface facing down. The foil is then drawn, etched and stripped to form the first electrode 410 and to isolate the first electrode 410 from the second electrode 430. As shown in FIG. 4, the two-layer dielectric 420 has two clearance holes. A clearance hole 423 allows the third electrode 440 to be electrically connected to the first electrode 410 of the foil. A clearance hole 425 also allows the second electrode 430 to be electrically connected to the foil portion 416.

  Next, a laminate material 450 may be laminated to the resulting article to form a foil on the laminate material 450. The circuit may be formed by etching the foil. The formation of the circuit conductors 4021 and 4022 can be performed, for example, only in the intermediate layer panel 4001 or through a printed wiring board including the intermediate layer panel 4001. Circuit 453 allows electrical connection to the end of capacitor 405 via first and second circuit conductors 4021, 4022. The interlayer panel 4001 is preferably laminated to a multilayer printed wiring board along with other interlayer panels containing interconnect circuits. The first and second circuit conductors 4021 and 4022 can be formed, for example, by forming conductive vias by laser drilling and plating.

  The ends of the electrodes 410, 430 are located within the footprint of the electrodes 410, 430 and not at the edges of the electrodes. The circuit conductors 4021 and 4022 connected to the terminal ends of the electrodes 410 and 430 extend outward from the foil surface of the first electrode 410 and do not extend from the electrode edge. As a result, the capacitor 405 has an advantage that the terminal separation is small and the PWB board area size is small.

  FIG. 5 is a cross-sectional view showing a capacitor interlayer panel 5001 of the fifth embodiment including the capacitor 505. Capacitor 505 includes a first electrode 510, a dielectric 520, and a second electrode 530 formed from foil. A capacitor 505 is stacked on the stacked material 540. Further, the circuit 543 may be disposed on the laminated material 540 to allow connection to the terminal of the capacitor 505 through the first and second circuit conductors 5021 and 5022.

  First electrode 510 is coupled to first circuit conductor 5021. Second electrode 530 is coupled to second circuit conductor 5022. The termination of the first electrode 510 is positioned at the through hole aperture 522 in the dielectric 520. The through hole aperture 522 coincides with the through hole aperture 532 in the second electrode 530.

  FIG. 6 is a cross-sectional view showing an intermediate panel 6001 of the sixth embodiment including a capacitor 605. Capacitor 605 includes a first electrode 610, a two-layer dielectric 620, a second electrode 630, and a third electrode 640 formed from foil. A capacitor 605 is stacked on the stacked material 650. A circuit 653 may also be formed on the laminate material 650 to allow connection to the end of the capacitor 605 via the first and second circuit conductors 6021, 6022.

  First electrode 610 and third electrode 640 are coupled to first circuit conductor 6021. Second electrode 630 is coupled to second circuit conductor 6022. The end of the second electrode 630 is positioned at the through hole aperture 622 of the dielectric 620. The through hole aperture 622 coincides with the through hole aperture 641 in the third electrode 640.

  The embodiment of capacitor 605 described above has the advantage that the termination separation is reduced and the surface area is reduced associated with positioning the capacitor electrode terminations within their individual electrode footprints. The capacitor 605 has a high capacitance density. This is because it is a three-electrode, two-layer dielectric design.

  In the above-described embodiment, instead of a thick film composition designed to be fired at a high temperature, a polymer thick film composition designed to be dried at a low temperature, for example, 150 ° C. may be used. The material may be formed on the foil in much the same manner as described above, but using a curing step instead of a firing step. Illustrated in FIGS. 7A-7E are embodiments and methods of interlayer panels using polymer thick film compositions.

  7A to 7D show a general manufacturing method of the intermediate layer panel 7001 of the seventh embodiment. Shown in FIG. 7E is a completed interlayer panel 7001 that includes a capacitor 705. The interlayer panel 7001 is manufactured by forming a panel layer using a polymer thick film composition.

  FIG. 7A is a cross-sectional view illustrating a first stage of manufacturing the intermediate layer panel 7001. In FIG. 7A, an article is provided that includes a first foil 710 and a second foil 720 laminated on opposite sides of a laminate material 730. The first and second foils 710, 720 may be formed from a polymer thick film material. Since the polymer thick film material is cured at a relatively low temperature, such as 150 ° C., the capacitor can be formed directly on the laminate material 730. The thick film material is dried simultaneously with curing.

  Referring to FIG. 7B, the laminated article of FIG. 7A is etched to form first electrode 712 from foil 710. Circuit 722 may also be formed from foil 720 during the etching step.

  Shown in FIGS. 7C and 7D is the next stage in the manufacture of the interlayer panel 7001. FIG. 7C is a plan view of the article formed at this stage of manufacture. 7D is a cross-sectional view in a side view taken along line 7D-7D in FIG. 7C. Referring to FIG. 7D, a dielectric 740 is formed on the first electrode 712. Dielectric 740 includes clearance holes or apertures 742 and is formed from a polymer thick film material. The dielectric 740 may be formed using one or more screen printing steps. Next, the dielectric 740 is cured. A second electrode 750 is formed on dielectric 740 using a polymer thick film material. The formation of the second electrode 750 may be performed, for example, by depositing a polymer thick film material in one or more screen prints and then curing. The second electrode 750 includes a clearance hole 752 that coincides with the clearance hole 742 but has a larger diameter (shown in FIG. 7C).

  FIG. 7E shows the completed intermediate layer panel 7001 as a cross-sectional view in a side view. In FIG. 7E, the article resulting from the screen printing step shown in FIGS. 7C and 7D is laminated to the laminate material 760 with the component side down. A foil may be laminated to the laminate material 760. Alternatively, the circuit 773 may be formed by etching the foil. Thus, the interlayer panel 7001 is a multilayer subassembly configuration.

  Next, the first conductor 761 and the second conductor 762 are formed. This is done, for example, by forming plated microvias by drilling and plating. The first conductor 761 extends through the laminate material 760 and through the clearance apertures 742, 752 in the dielectric 740 and the second electrode 750, respectively. The first conductor 761 is electrically connected to the first electrode 712, and the second conductor 762 is electrically connected to the second electrode 750.

  In the interlayer panel 7001, the panel 7001 is a circuitized interlayer or subassembly. Alternatively, the interlayer panel can be formed using a polymer thick film composition. In this case, the interlayer panel is part of the subset or is a larger subassembly of the interlayer panel. This is, for example, the embodiment of the fired foil described above. In such embodiments, circuit conductors may be formed after the interlayer panel 7001 is combined with one or more interlayer panels of the subassembly. The circuit conductor extends through all or part of the subassembly. Also, an interlayer panel having a polymer thick film layer can be combined with one or more interlayer panels to form a printed wiring board, such as that shown in FIG. 1I. In general, the previously described interlayer panel embodiments formed by the fired foil method can alternatively be formed using a cured polymer thick film composition. Capacitors formed using polymer thick film compositions are particularly useful, for example, in low capacitance capacitor applications.

  In the fired foil embodiments described herein, the term “paste” may correspond to conventional terms used in the electronic materials industry and generally refers to thick film compositions. Usually, the metal component of the base printing paste is matched to the metal in the metal foil. For example, when a copper foil is used, a copper-containing paste is used as the base printing. Another application is to pair silver and nickel foil with a similar metal substrate printing paste. A thick film paste may be used to form both the base print and passive circuit components.

  In general, thick film pastes are ceramic, glass, metal or other solid finely divided particles dispersed in a polymer dissolved in a mixture of plasticizer, dispersant and organic solvent. Is included. A preferred capacitor paste for use in calcined copper foil applications has an organic vehicle with good burnout characteristics in a nitrogen atmosphere. Such vehicles generally contain a very small amount of resin, such as high molecular weight ethylcellulose. Only a small amount is needed to produce a viscosity suitable for screen printing. Further, blending an oxidizing component such as barium nitrate powder into the dielectric powder mixture helps incinerate the organic component in a nitrogen atmosphere. The solid is mixed with an essentially inert liquid medium (“vehicle”) and then dispersed on a three roll mill to form a paste-like composition suitable for screen printing. Any liquid may be used as the vehicle if it is essentially inert. For example, various organic liquids (thickeners and / or stabilizers and / or other common additives included) may be used as the vehicle.

High dielectric constant (“high K”) thick dielectric pastes typically comprise at least one high K functional phase powder and at least one glass powder, comprising at least one resin and one or more solvents. Included are those distributed throughout the vehicle system. The vehicle system is designed to provide a dense and spatially clear film when screen printed. The high-K functional phase powder can contain a perovskite ferroelectric composition (general formula ABO ₃ ). Examples of such compositions include BaTiO ₃ , SrTiO ₃ , PbTiO ₃ , CaTiO ₃ , PbZrO ₃ , BaZrO ₃ , and SrZrO ₃ . Other compositions are possible by substituting alternative elements for the A and / or B positions. For example, Pb (Mg _1/3 Nb _2/3 ) O ₃ and Pb (Zn _1/3 Nb _2/3 ) O ₃ . TiO ₂ and SrBi ₂ Ta ₂ O ₉ are other possible high K materials.

  Also suitable are metal versions doped and mixed with the composition. Doping and mixing primarily achieves the required end-use characterization specifications, such as the required capacitance temperature coefficient (TCC), to ensure that the material meets industry regulations such as “X7R” or “Z5U” standards. Because.

The glass in the paste can be, for example, borosilicate Ca—Al, borosilicate Pb—Ba, silicate Mg—Al, rare earth borates, and other similar glass compositions. High K glass-ceramic powders such as lead germanate (Pb ₅ Ge ₃ O ₁₁ ) are preferred materials.

  Low K thick film dielectric pastes can also be utilized in low impedance designs where low capacitance is required. In this case, for example, a neodymium titanate, titanium dioxide, and barium titanate powder mixture is used instead of the high-K functional phase.

  The paste used to form the fired electrode layer may be based on a metal powder of copper, nickel, silver, a silver-containing noble metal composition, or a mixture of these compounds. A copper powder composition is preferred.

  Polymer thick film pastes used in cured components, such as those described above with reference to FIGS. 7A-7E, are generally organic solvents that may contain dispersed finely divided particles of ceramic or metal It consists of a permanent resin that is dissolved in it. Plasticizers, dispersants, or other additives may be used. A preferred polymer thick film capacitor paste may be, for example, a pure resin, barium titanate, or other high dielectric constant phase dispersed in an epoxy or polyimide resin solution. For the polymer thick film embodiment described above, the preferred polymer thick film conductor paste used to form the second electrode 750 in the interlayer panel 7001 is copper or silver powder, similar to that of the capacitor paste. It may be dispersed in a resin.

  The interlayer panel embodiments described herein have many applications. For example, interlayer panel embodiments can be used in organic printed circuit boards, IC packages, applications of these structures in decoupling applications, and devices such as IC modules and / or handheld device motherboards. Any of the intermediate panel embodiments described above can be combined into a printed wiring board structure. Moreover, you may form a printed wiring board combining the embodiment of the intermediate | middle layer panel mentioned above with the other conventional intermediate | middle layer panel.

  In the above-described embodiment, it is described that the conductive electrode layer is formed by screen printing. However, other methods may be used, for example deposition of the electrode metal by sputtering or evaporation onto the surface of the dielectric layer. The dielectric layer is also described as being formed by screen printing, and may be formed by an alternative method.

  The shape of the capacitor embodiment described above is substantially rectangular when viewed in plan view. However, capacitor electrodes, dielectrics, and other capacitor components can have other surface region shapes, such as circular or elliptical shapes and polygonal shapes.

  In the foregoing description of the invention, the invention has been illustrated and described. Also, while the disclosure has shown and described only selected preferred embodiments of the present invention, the present invention can be used in various other combinations, modifications, and environments and is expressed herein. It should be understood that variations or modifications can be made within the scope of the present inventive concept, corresponding to the above teachings, and / or within the skill or knowledge of the art.

  The above-described embodiments are further described to illustrate the best mode known for carrying out the invention, and those skilled in the art will recognize the invention in the above and other embodiments and according to specific applications or uses of the invention. It is intended to be available with various modifications required. Accordingly, the description is not intended to limit the invention to the form disclosed herein. It is also intended that the appended claims be construed to include alternative embodiments not explicitly defined in the detailed description.

It is a top view which shows the step of manufacture of 1st Embodiment of the intermediate | middle layer panel of a printed wiring board. It is sectional drawing seen along the line 1B-1B of the side view from FIG. 1A. It is a top view which shows the step of manufacture of 1st intermediate | middle layer panel embodiment. 1D is a cross-sectional view taken along line 1D-1D in the side view from FIG. 1C. FIG. It is sectional drawing in the side view which shows the step of manufacture of 1st intermediate | middle layer panel embodiment. FIG. 6 is a plan view showing the stages of manufacture of the first interlayer panel embodiment, showing the completed interlayer panel before bonding conductors to the interlayer panel termination. 1F is a cross-sectional view taken along line 1G-1G in the side view from FIG. 1F. It is sectional drawing in the side view which shows 1st Embodiment of the printed wiring board containing an intermediate | middle layer panel. It is sectional drawing in the side view and isolation | separation figure which show the 1st intermediate | middle layer panel embodiment after uniting with the printed wiring board shown to FIG. 1H. It is sectional drawing seen along line 1J-1J of FIG. 1I. It is sectional drawing in the side view which shows the step of manufacture of 2nd Embodiment of an intermediate | middle layer panel. It is sectional drawing in the side view which shows the step of manufacture of 2nd Embodiment of an intermediate | middle layer panel. It is sectional drawing in the side view which shows the step of manufacture of 2nd Embodiment of an intermediate | middle layer panel. It is sectional drawing in the side view which shows 2nd intermediate | middle layer panel embodiment. It is sectional drawing in the side view which shows 3rd Embodiment of an intermediate | middle layer panel. FIG. 3B is a cross-sectional view taken along line 3B-3B from FIG. 3A. It is sectional drawing in the side view which shows 4th Embodiment of an intermediate | middle layer panel. It is sectional drawing in the side view which shows 5th Embodiment of an intermediate | middle layer panel. It is sectional drawing in the side view which shows 6th Embodiment of an intermediate | middle layer panel. It is sectional drawing in the side view which shows the step of manufacture of 7th Embodiment of an intermediate | middle layer panel. It is sectional drawing in the side view which shows the step of manufacture of 7th Embodiment of an intermediate | middle layer panel. It is a top view which shows the step of manufacture of 7th intermediate | middle layer panel embodiment. It is sectional drawing in the side view seen along line 7D-7D of FIG. 7C. It is sectional drawing in the side view which shows the completed 7th intermediate | middle layer panel embodiment.

Claims (23)

A printed wiring board,
A first circuit conductor extending through at least a portion of the printed wiring board;
A second circuit conductor extending through at least a portion of the printed wiring board;
A plurality of stacked intermediate layer panels, and
At least one of the interlayer panels is
A first electrode formed from a foil and having a termination, wherein the first circuit conductor is coupled to the first electrode at the termination of the first electrode, the termination of the first electrode being at the first electrode A first electrode in the footprint;
At least one dielectric disposed on the first electrode;
A second electrode spaced apart from the first electrode and having a termination,
A printed wiring board, wherein the second electrode, the first electrode, and the dielectric form a capacitor, and the second circuit conductor is coupled to the end of the second electrode.   The printed circuit board according to claim 1, wherein the first circuit conductor extends through the dielectric. The end of the second electrode is within the footprint of the second electrode;
The printed wiring board according to claim 2, wherein the second circuit conductor extends through the dielectric. The intermediate layer comprises a laminate material disposed on the first and second electrodes and on the dielectric;
The printed wiring board according to claim 2, wherein the first circuit conductor extends through the laminated material.   The printed wiring board according to claim 4, wherein the second circuit conductor extends through the laminated material. The intermediate layer comprises a third electrode disposed spaced from the second electrode and electrically connected to the first electrode;
The printed wiring board according to claim 2, wherein the first electrode, the second electrode, the dielectric, and the third electrode form a capacitor.   The first electrode includes a first component surface that contacts the dielectric and a second surface opposite the first surface, and the first circuit conductor extends from the second surface of the first electrode. The printed wiring board according to claim 1.   The printed wiring board according to claim 7, wherein the end of the second electrode is in the footprint of the second electrode. The intermediate layer comprises a laminate material disposed on the second surface of the first electrode;
8. The printed wiring board according to claim 7, wherein the first circuit conductor extends through the laminated material and the second circuit conductor extends through the laminated material. The intermediate layer comprises a third electrode disposed spaced from the second electrode and electrically connected to the first electrode;
The printed wiring board according to claim 7, wherein the first electrode, the second electrode, the dielectric, and the third electrode form a capacitor. Forming a plurality of stacked interlayer panels, wherein forming at least one of the interlayer panels comprises:
Providing a metal foil;
Forming a dielectric on a metal foil;
Forming a first electrode from a metal foil, the first electrode having a termination positioned within the footprint of the first electrode;
Forming a second electrode on the dielectric, wherein the second electrode has a termination, and the first electrode, the second electrode, and the dielectric form a capacitor; ,
Forming a first circuit conductor, the first circuit conductor extending through at least a portion of the printed wiring board and contacting a terminal end of the first electrode;
Forming a second circuit conductor, the second circuit conductor contacting a terminal end of the second electrode and extending through at least a part of the printed wiring board. Manufacturing method of printed wiring board. The step of forming the dielectric
The method of claim 11, comprising forming a dielectric having a through hole, the first circuit conductor extending through the through hole. The end of the second electrode is within the footprint of the second electrode;
The method of claim 12, wherein forming the second circuit conductor includes forming a conductive via extending through the dielectric. The step of forming the intermediate layer panel is
13. The method of claim 12, comprising forming a laminate material on the first and second electrodes and on the dielectric. Forming the first circuit conductor includes forming a conductive via through the laminate material;
The method of claim 14, wherein forming the second circuit conductor includes forming a conductive via through the laminate material. Forming the interlayer panel includes forming a third electrode spaced apart from the second electrode and electrically connected to the first electrode;
The method of claim 12, wherein the first electrode, the second electrode, the third electrode, and the dielectric form a capacitor. The step of forming the intermediate layer panel is
Providing a laminated material;
And laminating a metal foil on the laminate material prior to forming the first electrode. A first electrode having a first component surface in contact with the dielectric and a second surface opposite the first surface;
The method of claim 11, wherein forming the first circuit conductor includes forming the first circuit conductor to extend from the second surface of the first electrode. The end of the second electrode is within the footprint of the second electrode;
The method of claim 18, wherein forming the interlayer panel comprises forming a laminate material on the second surface of the first electrode. Forming the first circuit conductor includes forming a conductive via through the laminate material;
20. The method of claim 19, wherein forming the second circuit conductor includes forming a conductive via through the laminate material. Forming the interlayer panel includes forming a third electrode spaced apart from the second electrode and electrically connected to the first electrode;
The method of claim 18, wherein the first electrode, the second electrode, the third electrode, and the dielectric form a capacitor. The step of forming the intermediate layer panel is
Providing a laminated material;
19. A method according to claim 18, comprising laminating a metal foil to a laminate material prior to forming the first electrode. Forming a plurality of stacked interlayer panels,
Providing a specific number of interlayer panels;
Bonding the interlayer panels together;
Forming a third circuit conductor through at least two of the joined interlayer panels;
12. The method of claim 11, including the step of combining the joined interlayer panels into a printed wiring board.

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