JP3956851B2 - Passive element embedded substrate and manufacturing method thereof - Google Patents

Passive element embedded substrate and manufacturing method thereof Download PDF

Info

Publication number
JP3956851B2
JP3956851B2 JP2003011957A JP2003011957A JP3956851B2 JP 3956851 B2 JP3956851 B2 JP 3956851B2 JP 2003011957 A JP2003011957 A JP 2003011957A JP 2003011957 A JP2003011957 A JP 2003011957A JP 3956851 B2 JP3956851 B2 JP 3956851B2
Authority
JP
Japan
Prior art keywords
laminate
layer
metal foil
substrate
passive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2003011957A
Other languages
Japanese (ja)
Other versions
JP2004228190A (en
Inventor
尽 佐藤
憲治 河本
Original Assignee
凸版印刷株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 凸版印刷株式会社 filed Critical 凸版印刷株式会社
Priority to JP2003011957A priority Critical patent/JP3956851B2/en
Publication of JP2004228190A publication Critical patent/JP2004228190A/en
Application granted granted Critical
Publication of JP3956851B2 publication Critical patent/JP3956851B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Description

【0001】
【発明の属する技術分野】
本発明は多層プリント配線板に埋め込み導通をとることでコンデンサーとして作動する積層体の付属した金属箔及びこれを用いて作製する受動素子内蔵基板の製造方法に関するものである。
【0002】
【従来の技術】
近年、電子機器の高性能化、小型化の要求に伴い回路部品の高密度化、高機能化が強まっている。そのため、プリント配線板にコンデンサー(C)、レジスタ(R)、インダクタ(L)等の受動素子を実装する場合においてはその実装効率を高めるためにこれら受動素子を基板内に内蔵した構造のプリント配線板が注目されている。
【0003】
受動素子を内蔵した基板の例としては、プリント基板に設けた透孔内にリードレスの回路部品を埋設した特開昭54−38561号公報、絶縁基板に設けた貫通孔内にセラミックコンデンサー等の受動素子を埋設した特公昭60−41480号公報、半導体素子のバイパスコンデンサーをプリント基板の孔に埋設した特開平4−73992号公報及び特開平5−218615号公報等が開示されている。
これは配線基板に設けられた貫通孔にチップ抵抗器またはチップコンデンサー等の既に完成されたリードレス素子を埋設した後、このリードレス素子の電極と配線基板上の配線パターンとを導電性ペーストまたは半田付けによって接続するものである。
【0004】
また、セラミック配線基板に設けたビアホール内に導電性物質と誘電性物質を充填して同時焼成した特開平8−222656号公報、有機系絶縁基板に設けた貫通孔に電子部品形成材料を埋め込んだ後、固化させてコンデンサーや抵抗器を形成した特開平10−56251号公報等が知られている。
【0005】
無機系(セラミック)配線基板の場合は、セラミックグリーンシートに設けられたビアホール内に誘電体ペーストや導電性ペーストを充填した後、高温で焼成することにより、所望のコンデンサーを内蔵した配線基板を形成することができる。ここでグリーンシートとは積層セラミックコンデンサーの製造に用いる、誘電性フィラーが樹脂に混練された焼成前のシートである。
有機系配線基板の場合には、配線基板に設けた貫通孔にコンデンサー等の電子部品形成材料(例えば誘電材料)を埋め込み、固化させることによって所望のコンデンサーとした後、その上下の端面にめっきを施して電極を形成し、電子部品内蔵配線基板を形成する。
【0006】
しかしながら、これらの貫通孔を利用して焼成あるいは固化したコンデンサーで大容量を得ることは困難である。一方、あらかじめ大容量が確保されているチップコンデンサー等を貫通孔へ埋設、実装する場合は、現行で最小サイズの0603チップを用いたとしても0.3mmあるいは0.6mmの層厚みが伴うため、薄い多層基板を実現することは困難であった。
【0007】
また、チップ部品単体でみた場合、市場には、1005、0603に代表される側面に電極が構成されたチップ部品が代表的であり、それらを基板に内蔵した例は、特許文献1等に既に提案されているが、内蔵用に特性、形状を考慮したチップ部品、またそれを基板に内蔵させた例はほとんど報告されていない。数少ない例として特許文献2に、転写法を利用してアルミナ、エポキシ樹脂を主成分とするコンポジット材料より成るシート状基材(Bステージ)中に長さL及び幅Wに比べて厚さtを小さくした埋め込みに適した形状の受動素子を埋め込む方法が開示されている。
【0008】
しかしながら上述のシート状基材を用いた方法では、Bステージ状態のコンポジット材料が流動性に乏しいため、厚さが100μm以上もある積層チップコンデンサーを埋め込むことは難しく、特に静電容量を確保するために誘電体の面積を大きくすると埋め込み性は悪化する。したがって、この方法では比較的静電容量の小さなコンデンサーしか埋め込むことができない。また、むき出しの素子を真空プレスで埋没させるため素子本体及びその周辺部へのダメージや樹脂の染み出しによる受動素子内蔵基板表面の平滑性の悪化等が懸念される。
【0009】
また、1層全面を誘電体層として形成し必要な部分のみ電極を付け静電容量を取り出すといった方法がある。図1に従来のプレーナータイプのコンデンサー素子内蔵基板の模式構成部分断面図を示す。従来の誘電体フィラーをバインダー樹脂に練り込んだ層を基板全面に設け上下に電極パターンを設けたいわゆるプレーナータイプコンデンサーは素子の静電容量が小さいことが問題になっていた。また、表面実装で用いられる積層セラミックチップコンデンサーは基板に内蔵することを目的として製造されていないため、小型ではあるものの厚さが不適であり、電極形状も内蔵には不向きであった。
【0010】
【特許文献1】
特開平11−220262号公報
【特許文献2】
特開2002−9416号公報
【0011】
【発明が解決しようとする課題】
本発明の目的は、多層プリント配線板の層間絶縁体層に内蔵するのに適した誘電体数を減らした薄型コンデンサーとすることができる積層体をあらかじめ表面粗化された金属箔上に形成し、この積層体を通常の金属箔積層手段によってプリント配線板の絶縁体層に埋没し、ビア形成を行って積層体の導通を図りコンデンサーとすることで、受動素子をプリント配線板に実装する手間が省けるとともに、積層工程を削減でき、また、電気的接続をビアで取ることによる配線長の短縮でより高密度な実装が可能な受動素子内蔵基板を開発することにある。
【0012】
【課題を解決するための手段】
請求項1に係る第1の発明は、配線パターンが形成されたプリント基板又は金属箔に、複数の誘電体層と複数の内層電極とをそれぞれ交互に積層した積層体を備えた積層体付き金属箔を、絶縁体層となる絶縁性樹脂を介して積層し、当該絶縁体層に前記積層体を埋め込んだ後、当該積層体にビアホールを形成後導電性ペーストの充填又はめっき処理を施すことで前記積層体の導通を図り、前記金属箔をエッチングによりパターニングすることで配線パターン及び積層体の外部接続端子を形成することを特徴とする受動素子内蔵基板の製造方法である。
【0025】
請求項に係る第の発明は、複数の誘電体層と複数の内層電極とをそれぞれ交互に積層した積層体を備えた積層体付き金属箔同士で絶縁性樹脂を挟み、一層の絶縁体層に両側から積層体を埋め込み、当該積層体にビアホールを形成後導電性ペーストの充填又はめっき処理を施すことで前記積層体の導通を図り、前記金属箔をエッチングによりパターニングすることで配線パターン及び積層体の外部接続端子を形成することを特徴とする受動素子内蔵基板の製造方法である。
【0026】
請求項3に係る第3の発明は、複数の誘電体層と複数の内層電極とをそれぞれ交互に積層した積層体を備えた積層体付き金属箔同士で、絶縁体層となる絶縁性樹脂を挟み、当該絶縁体層に両側から前記積層体が対向するように位置を合わせて埋め込んだ後、当該積層体にビアホールを形成後導電性ペーストの充填又はめっき処理を施すことで前記対向する積層体同士の導通あるいは配線を図って一体の受動素子とし、前記金属箔をエッチングによりパターニングすることで配線パターン及び積層体の外部接続端子を形成することを特徴とする受動素子内蔵基板の製造方法である。
【0027】
【発明の実施の形態】
本発明は複数の積層体が金属箔上に形成された積層体付き金属箔および、この金属箔上の積層体を絶縁性樹脂を介してプリント基板に、あるいは積層体付き金属箔同士を積層することで絶縁体層に埋め込み、積層体内の内層電極の導通をビアホール形成によって図り、また、金属箔をエッチングすることで配線パターンを形成した受動素子内蔵基板である。
【0028】
このとき積層体の誘電体層が樹脂シート、誘電性フィラー含有樹脂、誘電性セラミックスのいずれかのもので構成されており、樹脂シートは熱可塑性樹脂、熱硬化性樹脂もしくはその2つから構成され、誘電性フィラー含有樹脂はそれらの樹脂にに誘電性フィラーを混練してなり、誘電性セラミックスは誘電性フィラー含有樹脂を脱バインダー処理の後焼成したものである。前記誘電体層の厚さは一層が2〜20μm、積層数が1〜25層で、積層体全体の厚さが5〜100μmの範囲である積層体付き金属箔を用いて製造された受動素子内蔵基板である。
【0029】
本発明は受動素子内蔵基板に埋め込むために必要な静電容量を確保しつつ、多層プリント配線板の製造工程を考慮した最適構造を有するコンデンサーを提供し、埋め込み信頼性に優れた受動素子内蔵基板を提供するものである。
すなわち、単層で達成できなかったコンデンサー素子の静電容量を、内層電極面積を拡大し多層化を行うことによって確保し、さらに多層プリント配線板の積層工程で基板に埋め込めるように金属箔上に形成したものである。
【0030】
本発明の積層体の長さL及び幅Wは0.2mm≦L≦10mm、0.2mm≦W≦10mmの範囲であるとよい。ここでL及びWは積層体の辺のうち、金属箔表面と平行な二辺である。L及びWが上述の範囲であり、積層体の厚さtが5〜100μmであることで、プリント配線板のコア間の絶縁体層に複数個の積層体を埋設することが可能となる。
【0031】
本発明で述べる積層体は誘電体層と内層電極を順次積層して形成される。
ここで内層電極とは基板に内蔵されたコンデンサー(あるいは積層体)を構成する電極であって、静電容量の蓄積に関与する電極を指し、必ずしもコンデンサーの内部にあるわけではない。
誘電体層は熱可塑性樹脂もしくは熱硬化性樹脂、またはそれらを混合したものを用いることができ、これに誘電性フィラーを混練したものはより望ましい。樹脂材料を用いる理由としては、樹脂材料からなる誘電体は誘電率は低いがある程度の可とう性を有することから基板に内蔵する素子の材料に適している。
セラミックをシート状に焼成させたものを使用すると、誘電率が高く静電容量を稼げる一方で、静電容量を上げようと層を薄くすると割れやすくなり、多層プリント配線板の製造工程でクラックなどを生じ機能しなくなる恐れがある。この場合は誘電率の高さを活かして誘電体層の面積を小さくすると良い。
【0032】
本発明で述べる熱可塑性樹脂とは加熱によって塑性変形可能となるポリエステル、ポリイミド、ポリアミド、ポリアミドイミド、ポリエーテルスルホン、ポリスルホン、ポリエーテルエーテルケトン、ポリスチレン、ポリエチレン、ポリプロピレンなどがあげられる。
本発明で述べる熱硬化性樹脂とはエポキシ樹脂、フェノール樹脂、ウレタン樹脂、メラミン樹脂、アクリル樹脂などの三次元硬化物があげられる。
本発明では上述した熱可塑性樹脂、または熱硬化性樹脂を単独で、または複数種類を用いてもよく、熱可塑性樹脂と熱硬化性樹脂を混合して用いてもよい。
この際、必要に応じて溶剤、分散剤、カップリング剤などの添加剤を用いても良い。また、熱硬化性樹脂が成分として入っている場合は誘電体層を積層した後、加熱により熱硬化させて用いるとよい。特に半硬化(Bステージ)状態の熱硬化性樹脂を含む材料を用いると扱いやすい。
【0033】
本発明の積層体を構成する誘電体層には上述の熱可塑性及び/又は熱可塑性樹脂に加えて、誘電性フィラーを加えて誘電体層の誘電率を改善することができる。誘電性フィラーとしては無機フィラーが好ましく、その割合は重量比で樹脂:誘電性フィラー=10:90〜100:0の範囲であるが、必要とされるコンデンサーの特質に応じてその割合を変更することが可能である。高容量を得るためには通常は50wt%以上の誘電性フィラーを入れることが望ましい。
誘電性フィラーとして特に好ましくはBaTiO3、SrTiO3、CaTiO3、Mg2TiO3、ZnTiO3、La2Ti27、Nd2Ti27、PbTiO3、CaZrO3、BaZrO3、PbZrO3、BaTi1-xZrx3、PbZrxTi1-x3などが用いられ、必要に応じてそれらを混合して、あるいはそれらの固溶体を用いても良い。
【0034】
本発明の積層体(コンデンサー)は1〜25層の誘電体層から構成されることを特徴とする。好ましくは3層以上の誘電体層を有することが望まれる。この理由は誘電体層が1層だけであると必要とするコンデンサー素子の容量を得るためには大面積にならざるを得なく、確保できる静電容量、および素子の個数に制約を受けるためである。多層構造にすることでコンデンサーの静電容量を大きくすることができる。絶縁体層に収まる範囲内であれば可能な限り積層することができ、また誘電体層あるいは内層電極一層当たりの厚みが信頼性を損なわない範囲内で薄くなれば、それだけ積層数を増やすことができる。
【0035】
本発明の積層体の誘電体層の厚みは一層あたり50μm以下であることが好ましく、20μm以下であることがさらに望ましい。この理由はコンデンサー素子自体の厚さが薄くなるほど、プリント基板に埋め込みやすいことと、静電容量は電極間距離に反比例するため誘電体層が薄いほど大きな静電容量を得ることができるためである。
樹脂ベースの誘電体層を用いることで、フレキシブル基板への内蔵に対応した積層体(すなわちコンデンサー)とすることができる。
【0036】
本発明で述べる積層体に用いる内層電極は導電性であれば特に限定されるものではなく、金属の箔もしくはカーボンや金属微粒子を樹脂に混練した導電性ペーストが利用できる。
積層体及びそれからなるコンデンサーの薄型化の為に、内層電極の厚さは5μm以下であることが望ましい。
内層電極の形状もしくは形成位置は、積層体形成後、上下の内層電極間の導通をビアでとった際に、互い違いに導通が図れるように工夫すると良い。最も簡単な方法は、奇数層は奇数層で、偶数層は偶数層で重なるように、奇数層と偶数層は重なる部分を持ちつつもビア形成位置(導通部分)では重なることのないように内層電極を積層していくというものである。また本出願人による特願2002−277597号に記載のように内層電極をパターニングすることもできる。
【0037】
本発明で述べる積層体を作製する方法としては、あらかじめ誘電体層となる樹脂シートを用意し、内層電極となる金属箔を挟む、あるいは導電性ペーストで内層電極を印刷したのち、次の誘電体層を順次積層して形成する。この際に各誘電体層、内層電極間の密着性を増すために必要に応じて加熱下でプレスすることが望ましい。また、未硬化の熱硬化性樹脂が成分として含まれる場合は、積層過程で加熱硬化させるかもしくはプリント基板に埋め込み後一括して熱硬化させて使用する。
【0038】
本発明で述べる積層体の厚さtは5〜100μmの範囲であることが特に好ましい。この理由は積層体をプリント基板に内蔵する際、これより厚いと積層体と金属箔の段差を絶縁体層で埋めることが困難となり、基板表面の平滑性を確保しにくくなるためである。
【0039】
本発明で積層体を配設することになる金属箔としては、電気伝導性・延性・展性・加工性に優れた金属の箔が好ましく、具体例を挙げると銅またはニッケルの箔が好ましい。金属箔は使用前に化学薬品等で処理することにより、表面を粗化しておくとよい。
【0040】
積層体を金属箔上に設ける方法としては、まず金属箔上に誘電体層と内層電極とを順次積層していく方法が挙げられる。この場合、一番上になる層は内層電極とするのが静電容量を稼ぐために好ましい。
もう一つの方法は、内層電極と誘電体層を交互に積層して完成した積層体を金属箔に貼り付けるというものである。誘電体層を半硬化(Bステージ)状態の熱硬化性樹脂を含むものやグリーンシート等とすれば、特に接着性物質を用いなくとも熱プレスによって樹脂が溶融・硬化し容易に金属箔と接着可能である。
接着性物質を用いて積層体と金属箔との接着を行ってもよく、この場合貼り付けに導電性の接着材料を用い、積層体側の接着面を誘電体層とすると、より薄く静電容量の大きい積層体とすることができる。
いずれの場合も非接着面は内層電極とするのが完成したコンデンサーの容量を大きくする上で好ましい。
【0041】
従来の、小型コンデンサを基板上あるいは基板内に配設し、絶縁材料で埋め込む方法で製造される素子内蔵基板では、内蔵したコンデンサ周囲に絶縁材料が回り込まない等の接続不良が発生するのに対し、本発明の積層体は、後に配線パターン、あるいはコンデンサー電極となる金属箔と面で接着されることになるため周囲に空洞が生じることがなく、信頼性が高い構造である。
【0042】
本発明の積層体を特に簡便に得る方法としては、積層セラミックコンデンサーの製造に用いるグリーンシートを利用することもできる。グリーンシートとは誘電性フィラーが樹脂に混練された焼成前のシートであり、通常チタン酸バリウムのような誘電性フィラーがポリビニルブチラールやポリエチレンなどに練り込まれている。その他、誘電性フィラーとしてはBaTiO3、SrTiO3、CaTiO3、Mg2TiO3、ZnTiO3、La2Ti27、Nd2Ti27、PbTiO3、CaZrO3、BaZrO3、PbZrO3、BaTi1-xZrx3、PbZrxTi1-x3などが用いられ、必要に応じてそれらを混合して、あるいはそれらの固溶体を用いても良い。
このグリーンシートに導電性ペーストなどで内層電極を印刷し、複数層を積層することで本発明の積層体とすることができる。
【0043】
本発明の積層体として焼成前のグリーンシートの状態で使用する場合、グリーンシートには可撓性があるためフレキシブル基板への適用が可能であるという利点があるが、グリーンシートに用いられる樹脂の軟化点が低いため、できるだけコンデンサー層を基板の内層に配置すること、および製品となる受動素子内蔵基板の使用温度への注意が必要である。特に基板に耐熱性が要求される用途では耐熱性の樹脂で構成される誘電体層を用いることが好ましい。
【0044】
こグリーンシートを使用した積層体を300℃〜500℃に加熱して樹脂成分を加熱分解除去(脱バインダー工程)した後、さらに900℃〜1400℃の温度で焼成させチップ部品としてもよい。脱バインダー工程を経ると誘電性フィラーと導電性の電極剤のみとなるため、焼成しないと形状が保持できないが、焼成すると割れやすくなる。従って大きな面積では用いることができないが、バインダーが除かれることによって層としては薄くなり、また誘電率があがるため実際には樹脂を誘電体層とした積層体よりも小型化することができるため問題はない。誘電体層が焼成工程を経ているため、高温での使用が予想される受動素子内蔵基板に特に適している。
【0045】
本発明の積層体からなるコンデンサー素子は、その導通を、積層体を絶縁体層内に埋め込んだ後にビアホール形成によって行うので、絶縁体層の上下どちらの側にもコンデンサー素子の電極(外部接続電極)を形成することができ、配線の自由度が高い構造である。
【0046】
本発明の積層体付き金属箔は、絶縁性樹脂を介して基板に積層され、積層体は絶縁体層に埋め込まれることになる(図6、図8)。または片方は金属箔、もう一方は本発明の積層体付き金属箔を用いて絶縁性樹脂を挟み込み、ビアによる導通、配線パターンの形成を行ってもよい。
積層体付き金属箔同士で絶縁性樹脂を挟み、一層の絶縁体層に両側から積層体を埋め込むこともできる(図9、図10)。このとき上下で積層体の位置を合わせ、ビアで導通を図ることによって、静電容量の大きなコンデンサーを作り込むことも可能である(図10)。
【0047】
絶縁性樹脂(後の絶縁体層)は、としては導体回路やコンデンサー素子の段差が小さくなるよう、加熱加圧によりレベリング性を示すものであればよく、例えばプリント基板の積層に用いるプリプレグ、ビルトアップ層形成に用いる樹脂絶縁シートなどがあげられ、また樹脂ワニスなどを用いてもよい。金属箔及び積層体との接着性が高い材料が好ましい。
絶縁性樹脂は受動素子埋め込み・配線パターンの形成後に、配線パターンの絶縁及び基板表面を平滑にする目的で積層してもよい。
【0048】
本発明の積層体は絶縁体層に埋め込み後、所定位置に貫通孔をあけ、導電性樹脂ペーストを充填する、あるいは孔内を金属でめっきすることなどにより各層の内層電極間の導通を得て、積層体をコンデンサーとする。貫通孔を開ける方法としてはドリル法、パンチ法、ピン挿入法、レーザー加工など公知のプリント配線板へのビア形成法によって行うことができる。
【0049】
本発明の積層体付き金属箔は、金属箔の基板への積層前に、当該積層体の側面を導電性ペースト等の導電性材料で覆い、内層電極と金属箔の電気的接続をあらかじめ行うことも可能である。この場合、絶縁層埋め込み後の積層体に貫通孔を形成し内層電極の導通をとる必要はなく、配線パターンのエッチングで受動素子内蔵基板を完成させることができる。
【0050】
上記の工程によって積層体の内層電極の導通をとった後、金属箔をエッチングすることで基板の配線パターン及びコンデンサー(積層体)の外部接続電極を形成する。誘電体層が金属箔の直下にある場合は金属箔がコンデンサーの電極としての役目を果たすようにパターニングを行う。
こうして配線パターン等のパターニングがされた、本発明による受動素子内蔵基板を得ることができる。この配線パターンの上に更に絶縁体層や、導体層、積層体やその他の受動素子付き金属箔を積層することで、より多層構造の受動素子内蔵基板とすることができる。
【0051】
本発明の受動素子内蔵基板にはコンデンサー素子の他に抵抗素子やインダクター素子を同時に埋め込んで用いても良い。抵抗素子やインダクター素子もコンデンサー素子(積層体)と同様に金属箔上に形成し、あるいは完成品を接着し、これら受動素子付き金属箔を絶縁性樹脂を介してプリント基板に積層し、受動素子を絶縁体層に埋め込むことが可能である。
本発明の製造方法による受動素子内蔵基板は通常のプリント配線板と同様に基板上にチップコンデンサー、抵抗、ICなどの各種表面実装部品を実装して使用することができる。
【0052】
【実施例】
以下に実施例を示し図を用いて本発明を具体的に説明するが、本発明はこれに限定されるものではない。
〔実施例1〕
<工程a:樹脂ペーストの調整>
まず、熱可塑性樹脂であるポリエーテルスルホン(住友化学工業社製:商品名スミカエクセル5003P)を溶剤であるγ−ブチロラクトンに溶解させて樹脂ペーストとした。
【0053】
<工程b:積層体付き金属箔の製作>
次に、ポリイミドシートを支持体(1)として、この上にコーターを用いて前記樹脂ペーストを塗布後、乾燥して溶剤を除去し、約15μmの厚さの樹脂シート(3)を得た(図2(a))。
この樹脂シート(3)を切り出し支持体を取り除いて、樹脂(2)と厚さ5μmの銅箔を積層し、それぞれ誘電体層(5)と内層電極(6)とした(図2(b))。この際に誘電体層(5)の上下の内層電極(6)の重なりが1cm2になるように交互にずらしながら誘電体層(5)を4層と内層電極(6)を3層積層したのち、230℃で熱プレスして積層体(7)とした(図2(c))。
この積層体(7)を金属箔(8)(あらかじめ表面を粗化処理した厚さ18μmの銅箔)上に配置し、230℃で再度熱プレスを行い圧着して積層体付き金属箔(10)を製作した(図2(d))。
【0054】
<工程c:受動素子内蔵基板の製作>
上記手法で製作した積層体付き金属箔(10)をあらかじめ配線パターン(11)が形成された基板(12)に絶縁性樹脂(13)(プリプレグシート)を介して積層し(図3(a))、積層体が絶縁体層(14)に埋め込まれた基板とした(図3(b))。次に、積層体の内層電極(6)の1層目と3層目、金属箔(8)と2層目がそれぞれ接続される位置にドリルを用いて0.2mmφの貫通孔を空けたのちスルーホールめっきして導通をとり(15)、内層電極の電気的接続を行った(図3(c))。その後金属箔(8)をエッチングして配線パターン(16)及びコンデンサーの外部接続端子(16)を形成し、図3(d)の受動素子内蔵基板(20)を製作した。
端子間a−bの静電容量をLCRメーターにて測定したところ、0.70nFであった。
【0055】
〔実施例2〕
<工程a:樹脂ペーストの調整>
実施例1の工程aと同様にして樹脂ペーストを調整した。
【0056】
<工程b:積層体付き金属箔の製作>
実施例1の工程aで調整した樹脂ペーストを金属箔(8)(厚さ18μmの銅箔)上にスクリーン印刷でパターンを形成し、200℃でポストベークして誘電体層(5)とした(図4(a))。次に、この上に内層電極(6)として導電性ペーストをスクリーン印刷によりパターン状に印刷し、乾燥させた。1層の内層電極の面積は1.2cm2である(図4(b))。この上に再び樹脂ペーストを印刷、ベークして誘電体層とした後、1層下の内層電極パターンと重なりが1cm2となるように2層目の内層電極を印刷、乾燥し、以上の工程を誘電体層(5)が4層、内層電極(6)が3層になるまで行って積層体付き金属箔(10)を製作した(図4(c))。
【0057】
<工程c:受動素子内蔵基板の製作>
実施例1の工程cと同様にして受動素子内蔵基板(20)の製作をした(図3)。
端子間a−bの静電容量をLCRメーターにて測定したところ、0.62nFであった。
【0058】
〔実施例3〕
<工程a:樹脂ペーストの調整>
熱可塑性樹脂であるポリエーテルスルホン(住友化学工業社製:商品名スミカエクセル5003P)を溶剤であるγ−ブチロラクトンに溶解させ、さらに誘電性フィラーとしてチタン酸バリウム(堺化学製:商品名BT−05)を均一に分散させて誘電性フィラー含有樹脂ペーストを作成した。誘電性フィラーは樹脂ペーストの総固形分(熱可塑性樹脂)100重量部に対して80重量部を加えた。
【0059】
<工程b:積層体付き金属箔の製作>
ポリイミドシートを支持体(1)として、この上にコーターを用いて前記誘電性フィラー含有樹脂ペーストを塗布後、乾燥して溶剤を除去し、約15μmの厚さの誘電性フィラー含有樹脂シート(3)を得た(図2(a))。
この誘電性フィラー含有樹脂シート(3)を切り出し支持体を取り除いて、誘電性フィラー含有樹脂(2)と厚さ5μmの銅箔を積層し、それぞれ誘電体層(5)と内層電極(6)とした(図2(b))。この際に誘電体層(5)の上下の内層電極(6)の重なりが1cm2になるように交互にずらしながら誘電体層(5)を4層と内層電極(6)を3層積層したのち、230℃で熱プレスし積層体(7)とした(図2(c))。
この積層体(7)を金属箔(8)(あらかじめ表面を粗化処理した厚さ18μmの銅箔)上に配置し、230℃で再度熱プレスを行い圧着して積層体付き金属箔(10)を製作した(図2(d))。
【0060】
<工程c:受動素子内蔵基板の製作>
実施例1の工程cと同様にして受動素子内蔵基板(20)の製作をした(図3)。
端子間a−bの静電容量をLCRメーターにて測定したところ、6.91nFであった。
【0061】
〔実施例4〕
<工程a:樹脂ペーストの調整>
実施例3の工程aと同様にして誘電性フィラー含有樹脂ペーストを調整した。
【0062】
<工程b:積層体付き金属箔の製作>
実施例3の工程aで調整した樹脂ペーストを金属箔(8)(厚さ18μmの銅箔)上にスクリーン印刷でパターンを形成し、200℃でポストベークして誘電体層(5)とした(図4(a))。次に、この上に内層電極(6)として導電性ペーストをスクリーン印刷によりパターン状に印刷し、乾燥させた。1層の内層電極の面積は1.2cm2である(図4(b))。この上に再び誘電性フィラー含有樹脂ペーストを印刷、ベークして誘電体層とした後、1層下の内層電極パターンと重なりが1cm2となるように2層目の内層電極を印刷、乾燥し、以上の工程を誘電体層(5)が4層、内層電極(6)が3層になるまで行って積層体付き金属箔(10)を製作した(図4(c))。
【0063】
<工程c:受動素子内蔵基板の製作>
実施例1の工程cと同様にして受動素子内蔵基板(20)の製作をした(図3)。
端子間a−bの静電容量をLCRメーターにて測定したところ、6.78nFであった。
【0064】
〔実施例5〕
<工程a:樹脂ペーストの調整>
実施例3の工程aと同様にして誘電性フィラー含有樹脂ペーストを調整した。
【0065】
<工程b:積層体付き金属箔の製作>
ポリイミドシートを支持体(1)として、この上にコーターを用いて前記誘電性フィラー含有樹脂ペーストを塗布後、乾燥して溶剤を除去し、約15μmの厚さの誘電性フィラー含有樹脂シート(3)を得た(図5(a))。
この誘電性フィラー含有樹脂シート(3)を切り出し支持体を取り除いて、誘電性フィラー含有樹脂(2)と厚さ5μmの銅箔を積層し、それぞれ誘電体層(5)と内層電極(6)とした(図5(b))。この際に誘電体層(5)の上下の内層電極(6)の重なりが1cm2になるように交互にずらしながら誘電体層(5)と内層電極(6)をそれぞれ4層積層したのち、230℃で熱プレスし積層体(7)とした(図5(c))。
この積層体(7)を金属箔(8)(あらかじめ表面を粗化処理した厚さ18μmの銅箔)上に誘電体層を下にして配置し、230℃で再度熱プレスを行い圧着して積層体付き金属箔(10)を製作した(図5(d))。
【0066】
上記手法で製作した積層体付き金属箔(10)を配線パターンが形成されていない基板(12)に絶縁性樹脂(13)(プリプレグシート)を介して積層し(図6(a))、積層体が絶縁体層(14)に埋め込まれた基板とした(図6(b))。次に、積層体の内層電極(6)の1層目と3層目、金属箔(8)及び2層目と4層目がそれぞれ接続される位置にドリルを用いて0.2mmφの貫通孔を空けたのち導電性ペーストを充填して導通をとり(15)、内層電極の電気的接続を行った(図6(c))。金属箔(8)をエッチングして配線パターン(16)及びコンデンサーの外部接続端子(16)を形成し、図6(d)の受動素子内蔵基板(20)を製作した。
端子間c−dの静電容量をLCRメーターにて測定したところ、9.41nFであった。
【0067】
〔実施例6〕
<工程b:積層体付き金属箔の製作>
厚さ30μmのセラミックグリーンシートであるソルフィル(帝人ソルフィル社製)上に、Pdペースト(ML−3822N、昭栄化学工業社製)をスクリーン印刷により塗布し、内層電極(6)とした(図7(a))。この内層電極(6)を印刷したグリーンシート(4)を、上下の内層電極(6)が1cm2の重なりをもちながら交互にずれるように4層積層し、内層電極を覆うようにさらに1層グリーンシートを積層して、内層電極(6)4層、グリーンシート(4)5層とした。これを160℃で熱プレスをして接着し(図7(b))、両端を内層電極が揃うように切り出して積層体(7)を作製した(図7(c))。
この積層体(7)を金属箔(8)(あらかじめ粗化された厚さ18μmのNi箔)上に配置し、160℃で再度熱プレスを行い圧着して積層体付き金属箔(10)を製作した(図7(d))。
【0068】
この積層体付き金属箔(10)をN2雰囲気下、600℃で加熱し脱バインダー処理を行った後、空気中1100℃で2時間保持して焼成し、誘電性セラミックスを誘電体層(5)とする積層体付き金属箔とした。焼成後の積層体両端面に導電性ペースト(17)として銀ペーストを塗布し、N2雰囲気下600℃で焼き付け、内層電極(6)と金属箔(8)を電気的に接続した後、導電性ペースト(17)上にNiめっき被膜を形成した(図7(e))。この誘電性セラミックスを誘電体層とする積層体の外形寸法は、長さL=10mm,幅W=10mm(但し、長さ及び幅は対向する辺間の距離),厚さt=75μmであり、内層電極(6)間に介在する誘電体層(5)の厚みは10μmであった。
【0069】
<c:受動素子内蔵基板の製作>
上記手法で製作した積層体付き金属箔(10)をあらかじめ配線パターン(11)が形成された基板(12)に絶縁性樹脂(13)(プリプレグシート)を介して積層し(図8(a))、積層体が絶縁体層(14)に埋め込まれた基板とした(図8(b))。任意の位置にレーザーを用いて0.2mmφのビアを空け導電性ペーストを充填して導通をとり(18)、基板内の上下の電気的接続を行った(図8(c))。その後金属箔(8)をエッチングして配線パターン(16)及びコンデンサーの外部接続端子(16)を形成し、図8(d)の受動素子内蔵基板(20)を製作した。
端子間e−fの静電容量をLCRメーターにて測定したところ、1416nFであった。
【0070】
【発明の効果】
以上本発明によれば、必要な静電容量を確保しつつ、多層プリント配線板の絶縁体層に内蔵するのに適した誘電体数を減らした薄型コンデンサーとすることができる積層体を金属箔上に形成し、この積層体を通常の金属箔積層手段によってプリント配線板を構成する絶縁体層に埋没し、ビア形成を行って積層体の導通を図りコンデンサーとすることで、受動素子をプリント配線板に実装する手間が省けるとともに、積層工程を削減でき、また、電気的接続をビアで取ることによる配線長の短縮でより高密度な実装が可能な受動素子内蔵基板を得ることができる。
また、絶縁性樹脂を両面から本発明の積層体付き金属箔で挟み込み、ビアによる導通及び配線パターンの形成を行うことで、より小さな面積に静電容量・設計の自由度の高いコンデンサーを埋め込むことができる。絶縁体層への埋め込み時は積層体であるため、上下の積層体を電気的に接続することによって受動素子内蔵基板の製造時に内蔵するコンデンサーの静電容量を調節することができる。
【0071】
また、積層体を構成する誘電体層にセラミックグリーンシートを用いることで、より簡便に積層体を製作することができる。グリーンシートを用いて製作した積層体を焼成し、チップコンデンサー付き金属箔としたものを受動素子内蔵基板の製作に用いることもできる。このとき内蔵されたコンデンサーはより大きな静電容量を確保することができる。
本発明の積層体付き金属箔の導通は、基板への積層前に導電性ペーストによってとることもできるし、基板に積層後にビアの形成によって図ることも可能である。
【0072】
以上のように本発明の積層体付き金属箔を用いると静電容量の大きなコンデンサー素子を通常のビルトアップ工法を用いて簡便に内蔵することができ更に、配線の短縮によって性能の向上した信頼性の高い部品内蔵基板を提供することができる。またあらかじめ配設パターンの異なる積層体付き金属箔を製造しておき、これを組み合わせることで自由度の高いプリント配線板の製造を行うことができる。本発明を用いることで、種々の多層プリント配線板やモジュール基板の特性を向上させることができる。
【0073】
【図面の簡単な説明】
【図1】従来の基板内蔵型コンデンサーの一例を示す断面図である。
【図2】本発明に係る積層体付き金属箔の第1の製造例を示す説明図である。
【図3】本発明に係る受動素子内蔵基板の第1の製造例を示す説明図である。
【図4】本発明に係る積層体付き金属箔の第2の製造例を示す説明図である。
【図5】本発明に係る積層体付き金属箔の第3の製造例を示す説明図である。
【図6】本発明に係る受動素子内蔵基板の第2の製造例を示す説明図である。
【図7】本発明に係る積層体付き金属箔の第4の製造例を示す説明図である。
【図8】本発明に係る受動素子内蔵基板の第3の製造例を示す説明図である。
【図9】本発明に係る受動素子内蔵基板の第4の製造例を示す説明図である。
【図10】本発明に係る受動素子内蔵基板の第5の製造例を示す説明図である。
【符号の説明】
101…プレーナータイプのコンデンサー素子
102…配線パターン
103…ビアホール(IVH)
104…絶縁層
105…誘電体層
1…支持体
2…(誘電性フィラー含有)樹脂
3…(誘電性フィラー含有)樹脂シート
4…グリーンシート
5…誘電体層
6…内層電極
7…積層体
8…金属箔
10…積層体付き金属箔
11…配線パターン
12…基板
13…絶縁性樹脂
14…絶縁体層
15…導通をとったスルーホール
16…外部接続端子(a〜n)
17…導電性ペースト
18…導通をとったビアホール
20…受動素子内蔵基板
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a metal foil attached to a laminate that operates as a capacitor by embedding conduction in a multilayer printed wiring board, and a method for manufacturing a substrate with a built-in passive element using the metal foil.
[0002]
[Prior art]
In recent years, with the demand for higher performance and smaller size of electronic devices, the density and functionality of circuit components are increasing. Therefore, when mounting passive elements such as capacitors (C), resistors (R), and inductors (L) on the printed wiring board, the printed wiring having a structure in which these passive elements are built in the substrate in order to increase the mounting efficiency. The board is drawing attention.
[0003]
As an example of a substrate incorporating a passive element, Japanese Patent Application Laid-Open No. 54-38561 in which leadless circuit components are embedded in a through hole provided in a printed circuit board, a ceramic capacitor or the like in a through hole provided in an insulating substrate Japanese Patent Publication No. 60-41480, in which passive elements are embedded, Japanese Patent Application Laid-Open Nos. Hei 4-73992 and Japanese Patent Application Laid-Open No. 5-218615, in which a bypass capacitor of a semiconductor element is embedded in a hole of a printed circuit board, is disclosed.
This is because a leadless element such as a chip resistor or a chip capacitor is embedded in a through-hole provided in the wiring board, and then an electrode of the leadless element and a wiring pattern on the wiring board are connected with a conductive paste or They are connected by soldering.
[0004]
Japanese Patent Laid-Open No. 8-222656, in which a conductive material and a dielectric material are filled in a via hole provided in a ceramic wiring substrate and simultaneously fired, an electronic component forming material is embedded in a through hole provided in an organic insulating substrate Japanese Patent Application Laid-Open No. 10-56251, etc., which has been solidified to form a capacitor or a resistor is known.
[0005]
In the case of an inorganic (ceramic) wiring board, a dielectric substrate or conductive paste is filled in a via hole provided in a ceramic green sheet, and then fired at a high temperature to form a wiring board containing a desired capacitor. can do. Here, the green sheet is a sheet before firing in which a dielectric filler is kneaded with a resin, which is used for manufacturing a multilayer ceramic capacitor.
In the case of an organic wiring board, an electronic component forming material such as a capacitor (for example, a dielectric material) is embedded in a through hole provided in the wiring board and solidified to obtain a desired capacitor, and then the upper and lower end faces thereof are plated. To form an electrode and form an electronic component built-in wiring board.
[0006]
However, it is difficult to obtain a large capacity with a capacitor fired or solidified using these through holes. On the other hand, when embedding and mounting a chip capacitor having a large capacity in advance in the through hole, even if the current 0603 chip of the minimum size is used, the layer thickness is 0.3 mm or 0.6 mm. It has been difficult to realize a thin multilayer substrate.
[0007]
Further, when viewed as a single chip component, in the market, chip components having electrodes configured on the side surfaces represented by 1005 and 0603 are typical, and examples of incorporating them into a substrate are already disclosed in Patent Document 1 and the like. Although it has been proposed, there have been few reports on chip components that consider the characteristics and shape for incorporation, and examples of incorporating them into a substrate. As a few examples, Patent Document 2 discloses that a thickness t is compared with a length L and a width W in a sheet-like base material (B stage) made of a composite material mainly composed of alumina and epoxy resin using a transfer method. A method of embedding a passive element having a shape suitable for a small embedding is disclosed.
[0008]
However, in the method using the above-mentioned sheet-like substrate, since the B-stage composite material has poor fluidity, it is difficult to embed a multilayer chip capacitor having a thickness of 100 μm or more, particularly in order to ensure capacitance. If the area of the dielectric is increased, the embeddability deteriorates. Therefore, only a capacitor having a relatively small capacitance can be embedded by this method. In addition, since the exposed element is buried in a vacuum press, there is a concern about damage to the element body and its peripheral part, deterioration of the smoothness of the surface of the passive element built-in substrate due to resin seepage.
[0009]
Further, there is a method in which the entire surface of one layer is formed as a dielectric layer, and electrodes are attached only to necessary portions to take out the capacitance. FIG. 1 is a schematic partial sectional view of a conventional planar type capacitor element built-in substrate. A so-called planar type capacitor in which a layer in which a conventional dielectric filler is kneaded with a binder resin is provided on the entire surface of the substrate and electrode patterns are provided on the upper and lower sides has a problem that the capacitance of the element is small. In addition, since a multilayer ceramic chip capacitor used for surface mounting is not manufactured for the purpose of being incorporated in a substrate, it is small but has an inappropriate thickness, and the electrode shape is not suitable for incorporation.
[0010]
[Patent Document 1]
Japanese Patent Laid-Open No. 11-220262
[Patent Document 2]
JP 2002-9416 A
[0011]
[Problems to be solved by the invention]
An object of the present invention is to form a laminate on a metal foil whose surface has been roughened in advance, which can be a thin capacitor with a reduced number of dielectrics suitable for incorporation in an interlayer insulator layer of a multilayer printed wiring board. , By embedding this laminate in an insulating layer of a printed wiring board by a normal metal foil laminating means, forming vias to make the laminate conductive, and using it as a capacitor, the trouble of mounting passive elements on the printed wiring board The object is to develop a substrate with a built-in passive element that can reduce the stacking process and can be mounted at a higher density by shortening the wiring length by making electrical connections with vias.
[0012]
[Means for Solving the Problems]
A first invention according to claim 1 is a metal with a laminate comprising a laminate in which a plurality of dielectric layers and a plurality of inner layer electrodes are alternately laminated on a printed circuit board or metal foil on which a wiring pattern is formed. Foil Become an insulator layer Laminated with insulating resin , After embedding the laminate in the insulator layer, After the via hole is formed in the laminate, the laminate is made conductive by filling with conductive paste or plating, and the metal foil is patterned by etching to form a wiring pattern and an external connection terminal of the laminate. This is a method for manufacturing a substrate with a built-in passive element.
[0025]
Claim 2 No. related to 2 The invention of Provided with a laminate in which a plurality of dielectric layers and a plurality of inner layer electrodes are alternately laminated. Metal foil with laminate Between each other Insulating resin Sandwiched, embedded a laminate from both sides in one insulator layer, After the via hole is formed in the laminate, the laminate is made conductive by filling with conductive paste or plating, and the metal foil is patterned by etching to form a wiring pattern and an external connection terminal of the laminate. This is a method for manufacturing a substrate with a built-in passive element.
[0026]
According to a third aspect of the present invention, there is provided a metal foil with a laminate including a laminate in which a plurality of dielectric layers and a plurality of inner layer electrodes are alternately laminated. Become an insulator layer Sandwiching insulating resin, Concerned From both sides to the insulator layer Said Laminated body So that Embed by matching the position After By forming a via hole in the laminate and filling with a conductive paste or plating treatment, opposite Laminated body Mutual Figure of continuity or wiring As an integrated passive element, A method for manufacturing a substrate with built-in passive elements, wherein the metal foil is patterned by etching to form a wiring pattern and an external connection terminal of the laminate.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
In the present invention, a metal foil with a laminate in which a plurality of laminates are formed on a metal foil, and a laminate on the metal foil are laminated on a printed circuit board via an insulating resin, or metal foils with a laminate are laminated together. This is a substrate with a built-in passive element in which the conductive layer is embedded in the insulator layer, the conduction of the inner layer electrode in the laminated body is achieved by forming a via hole, and the wiring pattern is formed by etching the metal foil.
[0028]
At this time, the dielectric layer of the laminate is composed of any of a resin sheet, a dielectric filler-containing resin, and a dielectric ceramic, and the resin sheet is composed of a thermoplastic resin, a thermosetting resin, or two of them. The dielectric filler-containing resin is obtained by kneading a dielectric filler in these resins, and the dielectric ceramic is obtained by baking the dielectric filler-containing resin after debinding. A passive element manufactured using a metal foil with a laminated body in which the thickness of the dielectric layer is 2 to 20 μm per layer, the number of laminated layers is 1 to 25, and the total thickness of the laminated body is in the range of 5 to 100 μm. It is a built-in substrate.
[0029]
The present invention provides a capacitor having an optimum structure in consideration of the manufacturing process of a multilayer printed wiring board while ensuring the capacitance necessary for embedding in a passive element built-in substrate, and provides a passive element built-in substrate excellent in embedding reliability. Is to provide.
In other words, the capacitance of the capacitor element that could not be achieved with a single layer is secured by expanding the inner layer electrode area and increasing the number of layers, and further embedding it in the substrate in the multilayer printed wiring board lamination process Is formed.
[0030]
The length L and width W of the laminate of the present invention are preferably in the range of 0.2 mm ≦ L ≦ 10 mm and 0.2 mm ≦ W ≦ 10 mm. Here, L and W are two sides parallel to the metal foil surface among the sides of the laminate. When L and W are in the above-described range and the thickness t of the laminate is 5 to 100 μm, a plurality of laminates can be embedded in the insulator layer between the cores of the printed wiring board.
[0031]
The laminate described in the present invention is formed by sequentially laminating a dielectric layer and an inner layer electrode.
Here, the inner layer electrode is an electrode that constitutes a capacitor (or a laminate) built in the substrate, refers to an electrode that is involved in the accumulation of capacitance, and is not necessarily inside the capacitor.
As the dielectric layer, a thermoplastic resin, a thermosetting resin, or a mixture thereof can be used, and a dielectric material kneaded with this is more desirable. The reason for using a resin material is that a dielectric made of a resin material is suitable for a material of an element incorporated in a substrate because it has a low dielectric constant but a certain degree of flexibility.
Using ceramics fired into a sheet can increase the dielectric constant and increase the capacitance, but if the layer is thinned to increase the capacitance, it becomes easy to break, and cracks etc. in the manufacturing process of multilayer printed wiring boards May cause malfunction. In this case, it is preferable to reduce the area of the dielectric layer by making use of the high dielectric constant.
[0032]
Examples of the thermoplastic resin described in the present invention include polyester, polyimide, polyamide, polyamideimide, polyethersulfone, polysulfone, polyetheretherketone, polystyrene, polyethylene, and polypropylene that can be plastically deformed by heating.
Examples of the thermosetting resin described in the present invention include three-dimensional cured products such as epoxy resins, phenol resins, urethane resins, melamine resins, and acrylic resins.
In the present invention, the above-described thermoplastic resin or thermosetting resin may be used alone or in combination, or a mixture of thermoplastic resin and thermosetting resin may be used.
At this time, additives such as a solvent, a dispersant, and a coupling agent may be used as necessary. Further, when a thermosetting resin is contained as a component, the dielectric layer is laminated and then thermally cured by heating. In particular, it is easy to handle when a material containing a thermosetting resin in a semi-cured (B stage) state is used.
[0033]
In addition to the above-described thermoplastic and / or thermoplastic resin, a dielectric filler can be added to the dielectric layer constituting the laminate of the present invention to improve the dielectric constant of the dielectric layer. As the dielectric filler, an inorganic filler is preferable, and its ratio is in the range of resin: dielectric filler = 10: 90 to 100: 0 by weight ratio, but the ratio is changed according to the required characteristics of the capacitor. It is possible. In order to obtain a high capacity, it is usually desirable to add a dielectric filler of 50 wt% or more.
Particularly preferred as a dielectric filler is BaTiO. Three , SrTiO Three , CaTiO Three , Mg 2 TiO Three ZnTiO Three , La 2 Ti 2 O 7 , Nd 2 Ti 2 O 7 , PbTiO Three , CaZrO Three , BaZrO Three , PbZrO Three , BaTi 1-x Zr x O Three , PbZr x Ti 1-x O Three These may be used, and if necessary, they may be mixed or their solid solution may be used.
[0034]
The laminate (capacitor) of the present invention is composed of 1 to 25 dielectric layers. It is desirable to have three or more dielectric layers. The reason for this is that if there is only one dielectric layer, it is necessary to have a large area in order to obtain the required capacitance of the capacitor element, and the capacitance that can be secured and the number of elements are limited. is there. By using a multilayer structure, the capacitance of the capacitor can be increased. The layers can be stacked as much as possible within the range that can be accommodated in the insulator layer, and if the thickness per dielectric layer or inner layer electrode is reduced within a range that does not impair the reliability, the number of layers can be increased accordingly. it can.
[0035]
The thickness of the dielectric layer of the laminate of the present invention is preferably 50 μm or less per layer, more preferably 20 μm or less. The reason for this is that the thinner the capacitor element itself, the easier it is to embed it in the printed circuit board, and because the capacitance is inversely proportional to the distance between the electrodes, so that the thinner the dielectric layer, the larger the capacitance can be obtained. .
By using a resin-based dielectric layer, a laminated body (that is, a capacitor) that can be built into a flexible substrate can be obtained.
[0036]
The inner layer electrode used in the laminate described in the present invention is not particularly limited as long as it is electrically conductive, and a conductive paste obtained by kneading a metal foil or carbon or metal fine particles into a resin can be used.
The thickness of the inner layer electrode is desirably 5 μm or less in order to reduce the thickness of the laminate and the capacitor comprising the laminate.
The shape or formation position of the inner layer electrode may be devised so that conduction can be achieved alternately when vias are used to connect the upper and lower inner layer electrodes after forming the laminate. The simplest method is that the odd layer is an odd layer, the even layer is an even layer, and the odd layer and the even layer have overlapping portions, but the inner layer is not overlapped at the via formation position (conducting portion). The electrodes are stacked. The inner layer electrode can also be patterned as described in Japanese Patent Application No. 2002-277597 by the present applicant.
[0037]
As a method for producing a laminate described in the present invention, a resin sheet to be a dielectric layer is prepared in advance, a metal foil to be an inner layer electrode is sandwiched, or the inner layer electrode is printed with a conductive paste, and then the next dielectric Layers are sequentially stacked. At this time, in order to increase the adhesion between each dielectric layer and inner layer electrode, it is desirable to press under heating as necessary. Further, when an uncured thermosetting resin is included as a component, it is used by being heat-cured in the laminating process or by being heat-cured collectively after being embedded in a printed circuit board.
[0038]
The thickness t of the laminate described in the present invention is particularly preferably in the range of 5 to 100 μm. This is because when the laminate is built in the printed circuit board, if it is thicker than this, it is difficult to fill the step between the laminate and the metal foil with an insulator layer, and it becomes difficult to ensure the smoothness of the substrate surface.
[0039]
The metal foil on which the laminate is disposed in the present invention is preferably a metal foil excellent in electrical conductivity, ductility, malleability, and workability, and a copper or nickel foil is preferred as a specific example. The metal foil is preferably roughened by treating it with chemicals before use.
[0040]
As a method of providing the laminate on the metal foil, first, a method of sequentially laminating a dielectric layer and an inner layer electrode on the metal foil can be mentioned. In this case, the uppermost layer is preferably an inner layer electrode in order to increase capacitance.
Another method is to affix a metal laminate to a laminate obtained by alternately laminating inner layer electrodes and dielectric layers. If the dielectric layer is made of a semi-cured (B-stage) thermosetting resin or a green sheet, the resin melts and cures easily by hot pressing without using any adhesive material, and easily adheres to the metal foil. Is possible.
The laminate may be bonded to the metal foil using an adhesive substance. In this case, if a conductive adhesive material is used for pasting and the adhesive surface on the laminate side is a dielectric layer, the capacitance becomes thinner. It can be set as a large laminated body.
In any case, the non-adhesive surface is preferably an inner layer electrode in order to increase the capacity of the completed capacitor.
[0041]
In a conventional device-embedded substrate manufactured by a method in which a small capacitor is placed on or in a substrate and embedded with an insulating material, a connection failure such as an insulating material not flowing around the built-in capacitor occurs. The laminated body of the present invention has a highly reliable structure without forming a cavity in the periphery because it is bonded to a metal pattern to be a wiring pattern or a capacitor electrode later on the surface.
[0042]
As a method for obtaining the laminate of the present invention in a particularly simple manner, a green sheet used for producing a multilayer ceramic capacitor can also be used. The green sheet is a sheet before firing in which a dielectric filler is kneaded with a resin, and usually a dielectric filler such as barium titanate is kneaded into polyvinyl butyral or polyethylene. In addition, as a dielectric filler, BaTiO Three , SrTiO Three , CaTiO Three , Mg 2 TiO Three ZnTiO Three , La 2 Ti 2 O 7 , Nd 2 Ti 2 O 7 , PbTiO Three , CaZrO Three , BaZrO Three , PbZrO Three , BaTi 1-x Zr x O Three , PbZr x Ti 1-x O Three These may be used, and if necessary, they may be mixed or their solid solution may be used.
An inner layer electrode is printed on this green sheet with a conductive paste or the like, and a plurality of layers are laminated to obtain the laminate of the present invention.
[0043]
When the laminate of the present invention is used in the state of a green sheet before firing, the green sheet has an advantage that it can be applied to a flexible substrate because it is flexible. Since the softening point is low, it is necessary to pay attention to the operating temperature of the substrate with a built-in passive element as a product, and to place the capacitor layer on the inner layer of the substrate as much as possible. In particular, in applications where the substrate requires heat resistance, it is preferable to use a dielectric layer made of a heat resistant resin.
[0044]
The laminate using this green sheet may be heated to 300 ° C. to 500 ° C. to thermally decompose and remove the resin component (debinding process), and then fired at a temperature of 900 ° C. to 1400 ° C. to obtain a chip component. When the binder removal process is performed, only the dielectric filler and the conductive electrode agent are obtained, so that the shape cannot be maintained unless fired, but cracking tends to occur when fired. Therefore, it cannot be used in a large area. However, the layer becomes thinner by removing the binder, and the dielectric constant increases, so it can actually be made smaller than a laminate with resin as a dielectric layer. There is no. Since the dielectric layer has undergone a firing process, it is particularly suitable for a substrate with a built-in passive element that is expected to be used at high temperatures.
[0045]
In the capacitor element made of the laminate of the present invention, the conduction is performed by forming via holes after the laminate is embedded in the insulator layer. Therefore, the capacitor element electrodes (external connection electrodes) are formed on either side of the insulator layer. ), And a structure with a high degree of freedom of wiring.
[0046]
The metal foil with a laminate of the present invention is laminated on a substrate via an insulating resin, and the laminate is embedded in the insulator layer (FIGS. 6 and 8). Alternatively, one side may be a metal foil, and the other side may be a metal foil with a laminate of the present invention, and an insulating resin may be sandwiched to conduct by vias and form a wiring pattern.
It is also possible to sandwich an insulating resin between metal foils with a laminate and embed the laminate from both sides in a single insulator layer (FIGS. 9 and 10). At this time, it is also possible to make a capacitor with a large electrostatic capacity by aligning the position of the stacked body at the top and bottom and conducting through the via (FIG. 10).
[0047]
The insulating resin (later insulator layer) may be any resin that exhibits leveling properties by heating and pressing so that the level difference between the conductor circuit and the capacitor element is reduced. Examples thereof include a resin insulating sheet used for forming an up layer, and a resin varnish may be used. A material having high adhesion to the metal foil and the laminate is preferred.
The insulating resin may be laminated for the purpose of insulating the wiring pattern and smoothing the substrate surface after embedding the passive elements and forming the wiring pattern.
[0048]
After the laminate of the present invention is embedded in the insulator layer, a through hole is formed at a predetermined position, and a conductive resin paste is filled, or the inside of the hole is plated with a metal to obtain conduction between inner layer electrodes of each layer. The laminate is a capacitor. As a method for opening the through hole, a known via forming method for a printed wiring board such as a drill method, a punch method, a pin insertion method, or laser processing can be used.
[0049]
In the metal foil with a laminate of the present invention, before laminating the metal foil on the substrate, the side surface of the laminate is covered with a conductive material such as a conductive paste, and the inner layer electrode and the metal foil are electrically connected in advance. Is also possible. In this case, it is not necessary to form a through hole in the laminated body after embedding the insulating layer to make the inner layer electrode conductive, and the passive element built-in substrate can be completed by etching the wiring pattern.
[0050]
After conducting the conduction of the inner layer electrode of the laminate by the above process, the wiring pattern of the substrate and the external connection electrode of the capacitor (laminate) are formed by etching the metal foil. When the dielectric layer is directly below the metal foil, patterning is performed so that the metal foil serves as the capacitor electrode.
Thus, a passive element-embedded substrate according to the present invention in which a wiring pattern or the like is patterned can be obtained. By further laminating an insulator layer, a conductor layer, a laminate, and other metal foil with passive elements on the wiring pattern, a passive element-embedded substrate having a multilayer structure can be obtained.
[0051]
In addition to the capacitor element, a resistor element and an inductor element may be simultaneously embedded in the passive element-embedded substrate of the present invention. Resistive elements and inductor elements are formed on a metal foil in the same way as a capacitor element (laminated body), or a finished product is bonded, and these passive element-attached metal foils are laminated on a printed circuit board via an insulating resin. Can be embedded in the insulator layer.
The passive element built-in substrate according to the manufacturing method of the present invention can be used by mounting various surface mount components such as a chip capacitor, a resistor, and an IC on the substrate in the same manner as an ordinary printed wiring board.
[0052]
【Example】
Hereinafter, the present invention will be described in detail with reference to examples and the drawings, but the present invention is not limited thereto.
[Example 1]
<Process a: Adjustment of resin paste>
First, polyethersulfone (manufactured by Sumitomo Chemical Co., Ltd .: trade name Sumika Excel 5003P), which is a thermoplastic resin, was dissolved in γ-butyrolactone, which was a solvent, to obtain a resin paste.
[0053]
<Process b: Production of metal foil with laminate>
Next, the polyimide sheet was used as a support (1), and the resin paste was applied thereon using a coater, followed by drying to remove the solvent, thereby obtaining a resin sheet (3) having a thickness of about 15 μm ( FIG. 2 (a)).
The resin sheet (3) was cut out, the support was removed, and the resin (2) and a copper foil having a thickness of 5 μm were laminated to form a dielectric layer (5) and an inner layer electrode (6), respectively (FIG. 2B). ). At this time, the overlap between the upper and lower inner layer electrodes (6) of the dielectric layer (5) is 1 cm. 2 4 layers of dielectric layers (5) and 3 layers of inner layer electrodes (6) were stacked while being alternately shifted so as to form a stacked body (7) by hot pressing at 230 ° C. (FIG. 2C). ).
This laminate (7) is placed on a metal foil (8) (copper foil having a thickness of 18 μm whose surface has been roughened in advance), and is hot-pressed again at 230 ° C. and pressure-bonded to provide a metal foil with a laminate (10 ) Was manufactured (FIG. 2D).
[0054]
<Process c: Production of substrate with built-in passive element>
A metal foil (10) with a laminate manufactured by the above method is laminated on a substrate (12) on which a wiring pattern (11) has been formed in advance via an insulating resin (13) (prepreg sheet) (FIG. 3A). ), And a substrate in which the laminate was embedded in the insulator layer (14) (FIG. 3B). Next, after drilling a 0.2 mmφ through hole at a position where the first layer and the third layer of the inner layer electrode (6) of the laminate and the metal foil (8) and the second layer are connected, respectively. Through hole plating was conducted (15), and the inner layer electrodes were electrically connected (FIG. 3 (c)). Thereafter, the metal foil (8) was etched to form the wiring pattern (16) and the external connection terminal (16) of the capacitor, and the passive element built-in substrate (20) of FIG.
It was 0.70 nF when the electrostatic capacitance of the terminal ab was measured with the LCR meter.
[0055]
[Example 2]
<Process a: Adjustment of resin paste>
A resin paste was prepared in the same manner as in Step 1 of Example 1.
[0056]
<Process b: Production of metal foil with laminate>
A pattern was formed by screen printing the resin paste prepared in step a of Example 1 on a metal foil (8) (copper foil having a thickness of 18 μm) and post-baked at 200 ° C. to obtain a dielectric layer (5). (FIG. 4A). Next, a conductive paste was printed as a pattern by screen printing on this as an inner layer electrode (6) and dried. The area of one inner layer electrode is 1.2cm 2 (FIG. 4B). A resin paste is again printed on this and baked to form a dielectric layer. After that, an overlap with the inner electrode pattern under one layer is 1 cm. 2 The inner electrode of the second layer is printed and dried so that the metal foil with laminated body (10) is subjected to the above process until the dielectric layer (5) has four layers and the inner layer electrode (6) has three layers. ) Was manufactured (FIG. 4C).
[0057]
<Process c: Production of substrate with built-in passive element>
A passive element built-in substrate (20) was manufactured in the same manner as in step c of Example 1 (FIG. 3).
It was 0.62 nF when the electrostatic capacitance of ab between terminals was measured with the LCR meter.
[0058]
Example 3
<Process a: Adjustment of resin paste>
Polyether sulfone (manufactured by Sumitomo Chemical Co., Ltd .: trade name Sumika Excel 5003P) as a thermoplastic resin is dissolved in γ-butyrolactone as a solvent, and barium titanate (manufactured by Sakai Chemical Co., Ltd .: trade name BT-05) is used as a dielectric filler. ) Was uniformly dispersed to prepare a resin paste containing a dielectric filler. The dielectric filler was added in an amount of 80 parts by weight based on 100 parts by weight of the total solid content (thermoplastic resin) of the resin paste.
[0059]
<Process b: Production of metal foil with laminate>
Using the polyimide sheet as a support (1), the dielectric filler-containing resin paste is applied onto the support using a coater, and then dried to remove the solvent, and the dielectric filler-containing resin sheet (3 ) Was obtained (FIG. 2 (a)).
The dielectric filler-containing resin sheet (3) is cut out, the support is removed, and the dielectric filler-containing resin (2) and a copper foil having a thickness of 5 μm are laminated, and the dielectric layer (5) and the inner layer electrode (6), respectively. (FIG. 2B). At this time, the overlap between the upper and lower inner layer electrodes (6) of the dielectric layer (5) is 1 cm. 2 4 layers of dielectric layers (5) and 3 layers of inner layer electrodes (6) were stacked while being alternately shifted so as to form a stacked body (7) by hot pressing at 230 ° C. (FIG. 2 (c)). .
This laminate (7) is placed on a metal foil (8) (copper foil having a thickness of 18 μm whose surface has been roughened in advance), and is hot-pressed again at 230 ° C. and pressure-bonded to provide a metal foil with a laminate (10 ) Was manufactured (FIG. 2D).
[0060]
<Process c: Production of substrate with built-in passive element>
A passive element built-in substrate (20) was manufactured in the same manner as in step c of Example 1 (FIG. 3).
It was 6.91 nF when the electrostatic capacitance of the terminal ab was measured with the LCR meter.
[0061]
Example 4
<Process a: Adjustment of resin paste>
A dielectric filler-containing resin paste was prepared in the same manner as in step a of Example 3.
[0062]
<Process b: Production of metal foil with laminate>
A pattern was formed by screen printing the resin paste prepared in step a of Example 3 on a metal foil (8) (copper foil having a thickness of 18 μm) and post-baked at 200 ° C. to obtain a dielectric layer (5). (FIG. 4A). Next, a conductive paste was printed as a pattern by screen printing on this as an inner layer electrode (6) and dried. The area of one inner layer electrode is 1.2cm 2 (FIG. 4B). A dielectric filler-containing resin paste is again printed on this and baked to form a dielectric layer, and then an overlap with the inner layer electrode pattern one layer below is 1 cm. 2 The inner electrode of the second layer is printed and dried so that the metal foil with laminated body (10) is subjected to the above process until the dielectric layer (5) has four layers and the inner layer electrode (6) has three layers. ) Was manufactured (FIG. 4C).
[0063]
<Process c: Production of substrate with built-in passive element>
A passive element built-in substrate (20) was manufactured in the same manner as in step c of Example 1 (FIG. 3).
It was 6.78 nF when the electrostatic capacitance of the terminal ab was measured with the LCR meter.
[0064]
Example 5
<Process a: Adjustment of resin paste>
A dielectric filler-containing resin paste was prepared in the same manner as in step a of Example 3.
[0065]
<Process b: Production of metal foil with laminate>
Using the polyimide sheet as a support (1), the dielectric filler-containing resin paste is applied onto the support using a coater, and then dried to remove the solvent, and the dielectric filler-containing resin sheet (3 ) Was obtained (FIG. 5 (a)).
The dielectric filler-containing resin sheet (3) is cut out, the support is removed, and the dielectric filler-containing resin (2) and a copper foil having a thickness of 5 μm are laminated, and the dielectric layer (5) and the inner layer electrode (6), respectively. (FIG. 5B). At this time, the overlap between the upper and lower inner layer electrodes (6) of the dielectric layer (5) is 1 cm. 2 4 layers of dielectric layers (5) and inner layer electrodes (6) were laminated while being alternately shifted so as to form a laminate (7) by hot pressing at 230 ° C. (FIG. 5C).
This laminate (7) is placed on a metal foil (8) (a copper foil having a thickness of 18 μm whose surface has been roughened in advance) with the dielectric layer facing down, and is subjected to heat pressing again at 230 ° C. for pressure bonding. A metal foil (10) with a laminate was produced (FIG. 5 (d)).
[0066]
The laminated metal foil (10) manufactured by the above method is laminated on the substrate (12) on which the wiring pattern is not formed via the insulating resin (13) (prepreg sheet) (FIG. 6 (a)). The substrate was a substrate embedded in an insulator layer (14) (FIG. 6B). Next, a 0.2 mmφ through-hole is used by using a drill at positions where the first layer and the third layer of the inner layer electrode (6) of the laminate, the metal foil (8), and the second layer and the fourth layer are respectively connected. Then, the conductive paste was filled to establish conduction (15), and the inner layer electrodes were electrically connected (FIG. 6C). The metal foil (8) was etched to form the wiring pattern (16) and the external connection terminal (16) of the capacitor, and the passive element built-in substrate (20) of FIG. 6 (d) was manufactured.
It was 9.41 nF when the electrostatic capacitance of cd between terminals was measured with the LCR meter.
[0067]
Example 6
<Process b: Production of metal foil with laminate>
Pd paste (ML-3822N, manufactured by Shoei Chemical Industry Co., Ltd.) was applied onto solfill (manufactured by Teijin Solfill Co., Ltd.), which is a ceramic green sheet having a thickness of 30 μm, to form an inner electrode (6) (FIG. 7 ( a)). The green sheet (4) on which the inner layer electrode (6) is printed is arranged so that the upper and lower inner layer electrodes (6) are 1 cm. 2 4 layers were laminated so as to be alternately shifted while overlapping each other, and another one-layer green sheet was laminated so as to cover the inner layer electrode, thereby forming four layers of inner layer electrode (6) and five layers of green sheet (4). This was hot-pressed at 160 ° C. and bonded (FIG. 7B), and both ends were cut out so that the inner layer electrodes were aligned to produce a laminate (7) (FIG. 7C).
The laminate (7) is placed on the metal foil (8) (a previously roughened Ni foil having a thickness of 18 μm), heat-pressed again at 160 ° C. and pressure-bonded to obtain the metal foil (10) with the laminate. It was manufactured (FIG. 7 (d)).
[0068]
This laminated metal foil (10) is made of N 2 After debinding by heating at 600 ° C. in an atmosphere, the laminate was held in air at 1100 ° C. for 2 hours and fired to obtain a metal foil with a laminate in which dielectric ceramics was used as the dielectric layer (5). A silver paste is applied as a conductive paste (17) to both end faces of the laminate after firing, and N 2 After baking at 600 ° C. in an atmosphere to electrically connect the inner layer electrode (6) and the metal foil (8), a Ni plating film was formed on the conductive paste (17) (FIG. 7E). The outer dimensions of the laminate using the dielectric ceramics as a dielectric layer are as follows: length L = 10 mm, width W = 10 mm (where the length and width are distances between opposing sides), and thickness t = 75 μm. The thickness of the dielectric layer (5) interposed between the inner layer electrodes (6) was 10 μm.
[0069]
<C: Production of substrate with built-in passive element>
A metal foil (10) with a laminate manufactured by the above method is laminated on a substrate (12) on which a wiring pattern (11) is formed in advance via an insulating resin (13) (prepreg sheet) (FIG. 8A). ), A substrate in which the laminate was embedded in the insulator layer (14) (FIG. 8B). A laser was used to open a 0.2 mmφ via at an arbitrary position, and a conductive paste was filled to establish conduction (18), and the upper and lower electrical connections in the substrate were made (FIG. 8C). Thereafter, the metal foil (8) was etched to form the wiring pattern (16) and the external connection terminal (16) of the capacitor, and the passive element built-in substrate (20) of FIG.
It was 1416 nF when the electrostatic capacitance of ef between terminals was measured with the LCR meter.
[0070]
【The invention's effect】
As described above, according to the present invention, a laminated body that can be made a thin capacitor with a reduced number of dielectrics suitable for being incorporated in an insulating layer of a multilayer printed wiring board while ensuring a necessary capacitance is provided as a metal foil. Passive elements are printed by forming the laminate on the insulator layer that constitutes the printed wiring board by ordinary metal foil lamination means, forming vias, and using the laminate as a capacitor. It is possible to save the trouble of mounting on the wiring board, reduce the stacking process, and obtain a passive element-embedded substrate that can be mounted with higher density by shortening the wiring length by taking electrical connection with vias.
In addition, by sandwiching insulating resin from both sides with the metal foil with the laminate of the present invention, conducting vias and forming wiring patterns, a capacitor with a high capacitance and design freedom can be embedded in a smaller area. Can do. Since it is a laminated body when embedded in the insulator layer, the electrostatic capacity of the capacitor built in the manufacturing of the passive element built-in substrate can be adjusted by electrically connecting the upper and lower laminated bodies.
[0071]
Moreover, a laminated body can be more simply manufactured by using a ceramic green sheet for the dielectric layer which comprises a laminated body. A laminated body manufactured using a green sheet is fired to form a metal foil with a chip capacitor, which can be used for manufacturing a substrate with a built-in passive element. At this time, the built-in capacitor can secure a larger capacitance.
Conductivity of the metal foil with a laminate of the present invention can be taken with a conductive paste before lamination on the substrate, or can be achieved by forming vias after lamination on the substrate.
[0072]
As described above, when the metal foil with a laminate of the present invention is used, a capacitor element having a large capacitance can be easily built in by using a normal built-up method, and the reliability is improved by shortening the wiring. It is possible to provide a component-embedded substrate having a high height. Moreover, the metal foil with a laminated body from which an arrangement pattern differs is manufactured previously, and a printed wiring board with a high freedom degree can be manufactured by combining this. By using the present invention, characteristics of various multilayer printed wiring boards and module substrates can be improved.
[0073]
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing an example of a conventional substrate built-in capacitor.
FIG. 2 is an explanatory view showing a first production example of a metal foil with a laminate according to the present invention.
FIG. 3 is an explanatory view showing a first production example of a substrate with a built-in passive element according to the present invention.
FIG. 4 is an explanatory view showing a second production example of a metal foil with a laminate according to the present invention.
FIG. 5 is an explanatory view showing a third production example of a metal foil with a laminate according to the present invention.
FIG. 6 is an explanatory view showing a second manufacturing example of the passive element-embedded substrate according to the present invention.
FIG. 7 is an explanatory view showing a fourth production example of a metal foil with a laminate according to the present invention.
FIG. 8 is an explanatory view showing a third manufacturing example of a substrate with a built-in passive element according to the present invention.
FIG. 9 is an explanatory diagram showing a fourth manufacturing example of a substrate with built-in passive element according to the present invention.
FIG. 10 is an explanatory diagram showing a fifth manufacturing example of a substrate with a built-in passive element according to the present invention.
[Explanation of symbols]
101 ... Planar type capacitor element
102: Wiring pattern
103 ... via hole (IVH)
104: Insulating layer
105: Dielectric layer
1 ... Support
2 ... (with dielectric filler) resin
3 ... (with dielectric filler) resin sheet
4 ... Green sheet
5. Dielectric layer
6 ... Inner layer electrode
7 ... Laminated body
8 ... metal foil
10 ... Metal foil with laminate
11 ... Wiring pattern
12 ... Board
13. Insulating resin
14 ... Insulator layer
15 ... Through hole with conduction
16: External connection terminals (a to n)
17 ... Conductive paste
18: Conducted via hole
20 ... Substrate built-in substrate

Claims (4)

  1. 配線パターンが形成されたプリント基板又は金属箔に、複数の誘電体層と複数の内層電極とをそれぞれ交互に積層した積層体を備えた積層体付き金属箔を、絶縁体層となる絶縁性樹脂を介して積層し、当該絶縁体層に前記積層体を埋め込んだ後、当該積層体にビアホールを形成後導電性ペーストの充填又はめっき処理を施すことで前記積層体の導通を図り、前記金属箔をエッチングによりパターニングすることで配線パターン及び積層体の外部接続端子を形成することを特徴とする受動素子内蔵基板の製造方法。Insulating resin that becomes an insulator layer from a metal foil with a laminate comprising a laminate in which a plurality of dielectric layers and a plurality of inner layer electrodes are alternately laminated on a printed circuit board or metal foil on which a wiring pattern is formed After the laminate is embedded in the insulator layer, a via hole is formed in the laminate, and then the conductive paste is filled or plated to make the laminate conductive, and the metal foil A method of manufacturing a substrate with a built-in passive element, wherein the wiring pattern and the external connection terminal of the laminate are formed by patterning the substrate by etching.
  2. 複数の誘電体層と複数の内層電極とをそれぞれ交互に積層した積層体を備えた積層体付き金属箔同士で絶縁性樹脂を挟み、一層の絶縁体層に両側から積層体を埋め込み、当該積層体にビアホールを形成後導電性ペーストの充填又はめっき処理を施すことで前記積層体の導通あるいは配線を図り、前記金属箔をエッチングによりパターニングすることで配線パターン及び積層体の外部接続端子を形成することを特徴とする受動素子内蔵基板の製造方法。  Insulating resin is sandwiched between metal foils with a laminate including a laminate in which a plurality of dielectric layers and a plurality of inner layer electrodes are alternately laminated, and the laminate is embedded in one insulator layer from both sides. A via hole is formed in the body, and then the conductive paste is filled or plated to conduct the laminated body or wire, and the metal foil is patterned by etching to form a wiring pattern and an external connection terminal of the laminated body. A method of manufacturing a substrate with a built-in passive element.
  3. 複数の誘電体層と複数の内層電極とをそれぞれ交互に積層した積層体を備えた積層体付き金属箔同士で、絶縁体層となる絶縁性樹脂を挟み、当該絶縁体層に両側から前記積層体が対向するように位置を合わせて埋め込んだ後、当該積層体にビアホールを形成後導電性ペーストの充填又はめっき処理を施すことで前記対向する積層体同士の導通あるいは配線を図って一体の受動素子とし、前記金属箔をエッチングによりパターニングすることで配線パターン及び積層体の外部接続端子を形成することを特徴とする受動素子内蔵基板の製造方法。A plurality of dielectric layers and a plurality of the a laminate with a metal foil to each other with a laminate formed by alternately laminating each inner electrode, sandwiching an insulating resin as the insulating layer, the laminate from both sides with the insulating layer after body I embed in alignment so as to face, I Figure conduction or wiring of the multilayer bodies of the opposed applying filling or plating of the via holes formed after the conductive paste on the multilayer body A method for manufacturing a substrate with a built-in passive element , wherein an integrated passive element is formed, and the metal foil is patterned by etching to form a wiring pattern and an external connection terminal of the laminate.
  4. 請求項1から3に記載の方法によって製造されたことを特徴とする受動素子内蔵基板。  A passive element built-in substrate manufactured by the method according to claim 1.
JP2003011957A 2003-01-21 2003-01-21 Passive element embedded substrate and manufacturing method thereof Expired - Fee Related JP3956851B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003011957A JP3956851B2 (en) 2003-01-21 2003-01-21 Passive element embedded substrate and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003011957A JP3956851B2 (en) 2003-01-21 2003-01-21 Passive element embedded substrate and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2004228190A JP2004228190A (en) 2004-08-12
JP3956851B2 true JP3956851B2 (en) 2007-08-08

Family

ID=32900707

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003011957A Expired - Fee Related JP3956851B2 (en) 2003-01-21 2003-01-21 Passive element embedded substrate and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP3956851B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102254885A (en) * 2010-05-20 2011-11-23 深南电路有限公司 Passive device, passive device-embedded circuit board and manufacturing method

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4599997B2 (en) * 2004-11-08 2010-12-15 凸版印刷株式会社 Manufacturing method of wiring board with built-in solid electrolytic capacitor
JP4667070B2 (en) * 2005-02-23 2011-04-06 日本特殊陶業株式会社 Wiring board and method of manufacturing wiring board
JP4718890B2 (en) * 2005-04-28 2011-07-06 日本特殊陶業株式会社 MULTILAYER WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME, MULTILAYER WIRING BOARD STRUCTURE
CN101199247B (en) * 2005-06-13 2010-09-29 揖斐电株式会社 Printed wiring board
KR100651358B1 (en) * 2005-06-22 2006-11-29 삼성전기주식회사 Pcb embedding rf module
JP5134194B2 (en) * 2005-07-19 2013-01-30 ナミックス株式会社 Component built-in device and manufacturing method
US7932471B2 (en) 2005-08-05 2011-04-26 Ngk Spark Plug Co., Ltd. Capacitor for incorporation in wiring board, wiring board, method of manufacturing wiring board, and ceramic chip for embedment
US7573697B2 (en) 2005-08-31 2009-08-11 Ngk Spark Plug Co., Ltd. Method of manufacturing capacitor for incorporation in wiring board, capacitor for incorporation in wiring board, and wiring board
US7549721B2 (en) 2005-08-31 2009-06-23 Seiko Epson Corporation Printing method, printing system and method for determining correction value
US7580240B2 (en) 2005-11-24 2009-08-25 Ngk Spark Plug Co., Ltd. Via array capacitor, wiring board incorporating a via array capacitor, and method of manufacturing the same
JP4841234B2 (en) * 2005-11-24 2011-12-21 日本特殊陶業株式会社 Manufacturing method of wiring substrate with built-in via array capacitor
JP5089880B2 (en) 2005-11-30 2012-12-05 日本特殊陶業株式会社 Capacitor for wiring board built-in, wiring board with built-in capacitor and manufacturing method thereof
JP4773531B2 (en) 2007-10-18 2011-09-14 イビデン株式会社 Wiring board and manufacturing method thereof
JP2009194096A (en) * 2008-02-13 2009-08-27 Murata Mfg Co Ltd Component built-in substrate and component package using the same
JP2010087499A (en) * 2008-09-30 2010-04-15 Ibiden Co Ltd Method of manufacturing capacitor device
JP5401617B1 (en) * 2013-01-24 2014-01-29 有限会社 ナプラ Substrate built-in substrate
US9659850B2 (en) 2014-12-08 2017-05-23 Qualcomm Incorporated Package substrate comprising capacitor, redistribution layer and discrete coaxial connection

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102254885A (en) * 2010-05-20 2011-11-23 深南电路有限公司 Passive device, passive device-embedded circuit board and manufacturing method

Also Published As

Publication number Publication date
JP2004228190A (en) 2004-08-12

Similar Documents

Publication Publication Date Title
US9119322B2 (en) Wiring board and method for manufacturing the same
US8575496B2 (en) Multilayer printed wiring board and method of manufacturing the same
JP3709882B2 (en) Circuit module and manufacturing method thereof
US7571536B2 (en) Method of making capacitive/resistive devices
US7570491B2 (en) Printed circuit board with embedded capacitors therein, and process for manufacturing the same
JP4332536B2 (en) Capacitor-embedded printed circuit board using hybrid material and manufacturing method thereof
TWI242398B (en) Printed circuit board and method of manufacturing the same
JP4568718B2 (en) Fabrication method of 3D all-organic interconnect structure
JP4079699B2 (en) Multilayer wiring circuit board
US7198996B2 (en) Component built-in module and method for producing the same
TW559955B (en) Interconnect module with reduced power distribution impedance
US8053673B2 (en) Capacitor embedded printed circuit board
US7072167B2 (en) Co-fired ceramic capacitor and method for forming ceramic capacitors for use in printed wiring boards
KR100562812B1 (en) Printed wiring boards having capacitors and methods of making thereof
JP3051700B2 (en) Method of manufacturing multilayer wiring board with built-in element
US7279412B2 (en) Parallel multi-layer printed circuit board having improved interconnection and method for manufacturing the same
KR100688768B1 (en) Embedded chip print circuit board and method for fabricating the same
JP5095398B2 (en) Multilayer printed wiring board
EP1578178B1 (en) Flexible substrate, multilayer flexible substrate and process for producing the same
US7384856B2 (en) Method of making an internal capacitive substrate for use in a circuitized substrate and method of making said circuitized substrate
KR940009175B1 (en) Multi-printed wiring board
KR100907045B1 (en) Passive device structure
US7548432B2 (en) Embedded capacitor structure
US8148645B2 (en) Wiring substrate and method of manufacturing the same
US20030049885A1 (en) Semiconductor package, method of manufacturing the same, and semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20051220

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20061212

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070209

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070313

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070322

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20070417

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20070430

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110518

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110518

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120518

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120518

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130518

Year of fee payment: 6

LAPS Cancellation because of no payment of annual fees