JPS5917232A - Composite laminated ceramic part and method of producing same - Google Patents

Composite laminated ceramic part and method of producing same

Info

Publication number
JPS5917232A
JPS5917232A JP57126176A JP12617682A JPS5917232A JP S5917232 A JPS5917232 A JP S5917232A JP 57126176 A JP57126176 A JP 57126176A JP 12617682 A JP12617682 A JP 12617682A JP S5917232 A JPS5917232 A JP S5917232A
Authority
JP
Japan
Prior art keywords
layer
sheet
resistor
insulator
raw
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57126176A
Other languages
Japanese (ja)
Inventor
嶋田 勇三
和明 内海
輝幸 池田
正則 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP57126176A priority Critical patent/JPS5917232A/en
Publication of JPS5917232A publication Critical patent/JPS5917232A/en
Pending legal-status Critical Current

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  • Ceramic Capacitors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は、コンデンサ・抵抗及び導体配線を有する複合
積層セラミック部品と、その製迅方法に導体を同時に焼
成して複合化した稍層セラミック部品とその製造方法に
関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a composite multilayer ceramic component having a capacitor, a resistor, and conductor wiring, a multilayer ceramic component in which a conductor is simultaneously fired and composited, and a manufacturing method thereof.

従来電7回路における蜆、抗、コンデンサ、インダクタ
ンス等の受動部品およびトランジスタ、ダイオード等の
能動部品はセラミック等の基板にプリント配線層を設け
、半田付けして回路を作り、それをユニットとして用い
ることが行なオ〕れていた。この場合円板形またはチッ
プ型のコンデンサやチップ抵抗等を1個づつ取付けられ
ねばならなかった。
Passive components such as wires, resistors, capacitors, and inductances, and active components such as transistors and diodes in conventional electric circuits are made by providing a printed wiring layer on a ceramic substrate, soldering it to form a circuit, and using it as a unit. was being carried out. In this case, disk-shaped or chip-shaped capacitors, chip resistors, etc. had to be installed one by one.

また抵抗複合部品においては、セラミ、り焼結基体に電
極及び抵抗体を焼付けして1跨られるし、コンデンサを
付加させる場合には、設けられた電極層にチーズ型等の
コンデンサを半田付けして得られていた。この場合にも
コンデンサ゛は1個づつ取付けられねはならないし、複
合部品を小型化することも困難であった。
In addition, in resistor composite parts, electrodes and resistors are baked on a ceramic or resintered base to span one layer, and when a capacitor is added, a cheese-shaped capacitor is soldered to the provided electrode layer. was obtained. In this case as well, the capacitors had to be attached one by one, and it was difficult to downsize the composite component.

一方、第1図に示すようなアルミナクリーンシートを用
いたコンデンサ、抵抗付多層セラミック基板においては
、コンデンサを基体焼成と同時に形成し、その後抵抗体
を焼+1’ +プし℃形成するものである。しかしこの
場合、基体羽1としてfルミナシ−)1を用いているた
め焼成温度は1500℃以上と高温にしなけれはならず
導体材料としてN10゜W、Mn等の導伝率の低い4体
2を用いて還元雰囲気中で行なわなければならなかった
またコンデンサ形成部分3の誘辺俸層4としてアルミナ
を用いているため誘電率も9程度と非常に低く、ぜいせ
い3pF/■2程度の容諷しか得ることが出来なかった
。さらに抵抗を形成する工程において(J1焼焼結体上
にスクリーン印刷等により抵抗体5を印刷し、焼付けし
て形成するため、工程が多くなることと、抵抗数を増す
に従い基体面積か火きくなり小型化、高@度化が困難に
なること等の欠点があった〇 才た、第2区〜第4図に示すようなlLC複合部品も考
えられている0各図には複合部品の模式的斜視図(R)
と等価11j路図(blをボした。紀2図、第3図にお
いては、積層チップコンデンサ■3の夕l都電極部11
に抵抗体12を形成した構造(・もっでいるが、複l)
I個のコンブ17号および抵抗!子を1個の部品中に構
成することは困粋であり、工程的にも多くの工程が心火
、!:なり熱ザイクルも加わるためコストの面でも信頼
性の面でも問題がある。第4図においては、積層構造中
にコンテ′ンザおよび抵抗12を形成しているが、g電
体15、絶縁体16のセラミックシートは同一物質であ
りアルミナ、ステアタイト、フォリステライト、チタン
酸バリウム、TlO2等を用いているため焼結後のセラ
ミックスの機械的強度は低くチップ部品として利用する
には十分であるにしても種々のチップ部品を搭載し実装
等に利用する基板部品には不十分で適用出来ない欠点が
あり、また焼成後、外部電極11を焼付けて完成部品と
するため工程を多く取らねはならず形状の大きな部品で
しかも多数個の抵抗、コンデンサ素子を構成することは
困難であり、高密度化に対しても問題がある。
On the other hand, in the case of capacitors and multilayer ceramic substrates with resistors using alumina clean sheets as shown in Figure 1, the capacitors are formed at the same time as the substrate is fired, and then the resistors are fired and formed at +1' +°C. . However, in this case, since f-luminescence) 1 is used as the base wing 1, the firing temperature must be as high as 1500°C or higher, and four materials 2 with low conductivity such as N10°W and Mn are used as conductive materials. In addition, since alumina is used as the dielectric layer 4 of the capacitor forming part 3, the dielectric constant is very low at about 9, and the capacitance is about 3 pF/2 at most. All I could get was a joke. Furthermore, in the process of forming the resistor (the resistor 5 is printed on the J1 sintered body by screen printing, etc. and baked, the number of steps increases, and as the number of resistors increases, the area of the base becomes smaller). However, LC composite parts as shown in Figures 2 to 4 are also being considered.Each figure shows the composite parts. Schematic perspective view (R)
Equivalent 11j path diagram (bl has been removed. In Figures 2 and 3, the electrode section 11 of the multilayer chip capacitor ■3)
A structure in which the resistor 12 is formed on the
I kelp No. 17 and resistance! It is difficult to configure children into one part, and there are many processes involved! : Since thermal cycles are also added, there are problems in terms of cost and reliability. In Fig. 4, a capacitor and a resistor 12 are formed in a laminated structure, and the ceramic sheets of the g-electric body 15 and the insulator 16 are made of the same material, and are made of alumina, steatite, follisterite, barium titanate. , TlO2, etc., the mechanical strength of the ceramic after sintering is low, and although it is sufficient for use as chip parts, it is insufficient for board parts on which various chip parts are mounted and used for mounting etc. Moreover, after firing, the external electrode 11 is baked to form a finished part, which requires many steps, and it is difficult to construct a large number of resistor and capacitor elements. Therefore, there is also a problem in increasing the density.

本発明の目的は、このような従来の種々の問題点および
欠点を除去せしめて酸化性雰囲気下で低温で同時焼成し
て複数個のRCを構成するとともに高誘電率のd′亀体
を用いることlこより大容量のコンデンサを形成した小
型^密度を部品あるいは機械的強度の十分な高密度大面
積実装用複合基板を提供し、同時焼成による工程の簡略
化とコスト低下で作業性、信頼性の向上をはかりまた導
体として高導電率導体か利用でき機能性も向上したコン
デンサ・抵抗及び導体配線を有する複合積層セラミック
部−品及びその製造方法を提供することにある0 すなわち本発明は絶縁体、誘電体、抵抗体、導体がそれ
ぞれ有機物と混合され、シート状又はペースト状になっ
たものが一体に成型され、焼成されてなる積層併結体で
あって、その内部に1以上のコンデンサ素子と1以上の
抵抗素子と配線用導電体を備えてなることを特徴とする
複合積層セラミック部品でありS誘電体生シートと抵抗
体生シートおよび絶縁体生シートを形成する工程と絶縁
体生シートおよび訪電体生シートにスルーホールを穿設
して該スルーホール1こ導電性物質を充填すると同時に
導体層を表面Jこ形成する工程と抵抗体生シー トを7
9を望の形状に切ルfし、41記スルーポールが設けら
ハ孔中に々t′嵯性物性物質填された絶縁体生シート面
又はスルーホールを設けていない絶縁体生シート面に接
するように積層する工程とそれぞれの生シートを堕層熱
圧着して積層体を形成する工程と該積層体を所定の大き
さに切断し、焼成する工程を有することを特徴とする複
合積層セラミック部品の製造方法である。
It is an object of the present invention to eliminate the various problems and drawbacks of the conventional methods, and to construct a plurality of RCs by simultaneous firing at low temperatures in an oxidizing atmosphere, and to use a d' turtle body with a high dielectric constant. We provide compact ^density components that form larger capacitance capacitors or high-density, large-area mounting composite boards with sufficient mechanical strength, and improve workability and reliability by simplifying the process and reducing costs through simultaneous firing. The object of the present invention is to provide a composite laminated ceramic component having a capacitor, a resistor, and a conductor wiring, which can use a high conductivity conductor as a conductor and have improved functionality, and a method for manufacturing the same. , a dielectric, a resistor, and a conductor, each mixed with an organic substance and formed into a sheet or paste form, are integrally molded and fired, and one or more capacitor elements are formed inside. It is a composite laminated ceramic component characterized by comprising one or more resistance elements and a wiring conductor, and includes a step of forming an S dielectric raw sheet, a resistor raw sheet, and an insulator raw sheet, and an insulator raw sheet and Step 7 of drilling a through hole in the current-visiting material raw sheet, filling the through hole with a conductive material, and simultaneously forming a conductor layer on the surface of the resistor material raw sheet.
9 into the desired shape, and the through holes No. 41 are provided on the surface of the insulator green sheet in which the holes are filled with a thick physical substance or on the surface of the insulator green sheet without through holes. A composite laminated ceramic comprising the steps of laminating the raw sheets so that they are in contact with each other, forming a laminated body by thermo-compression bonding the respective raw sheets in layers, and cutting the laminated body into a predetermined size and firing the laminated body. This is a method for manufacturing parts.

以下、本発明について実施例1こよって詳細に説明する
0 実施例1゜ まず本発明で用いる絶縁体生シートは、酸化アルミニウ
ム40〜60重量%、結晶化カラス40〜60重14%
の組成範囲で総fi100%となるように選んだ混合粉
末をバインダー、有機溶媒、可塑剤と共に滉漿状にし、
ドクターブレード法等のスリップキャスティング製膜に
より20μm〜300μmの生シートをポリエステルフ
ィルム上に成形し剥離したのち所望の寸法にパンチング
してシートを得る。ここで用いた結晶化ガラス粉末の組
成は、酸化物換界表記に従ったとき酸化7む、酸比ホ・
り宋二酸化ケイ素、■族元素酸化物、Iv族元素(但し
縦索、り゛イ素、、鉛は除く)酸化−をそれぞれ重量比
3〜65チ、2〜50%、4〜65%、01〜50係、
0.02〜20%の組成範囲でajtzoo=4とtよ
るように選んだ組成物で構成されている。
Hereinafter, the present invention will be explained in detail using Example 1.0 Example 1 First, the insulating green sheet used in the present invention was made of aluminum oxide 40-60% by weight, crystallized glass 40-60% by weight
A mixed powder selected to have a total fi of 100% within the composition range is made into a paste with a binder, an organic solvent, and a plasticizer,
A raw sheet of 20 μm to 300 μm is formed on a polyester film by slip casting film forming such as a doctor blade method, peeled off, and then punched to a desired size to obtain a sheet. The composition of the crystallized glass powder used here is 7% oxidation and 7% acid ratio according to the oxide exchange boundary notation.
Silicon dioxide, Group I element oxides, and Group IV elements (excluding vertical lines, silicon, and lead) oxidized in weight ratios of 3 to 65%, 2 to 50%, and 4 to 65%, respectively. 01-50 section,
It is composed of a composition selected such that ajtzoo=4 and t in a composition range of 0.02 to 20%.

誘電体生シートはFetus、pbo、Nb*08、W
OIの粉末を所定量秤量し、ボールミル混合してろ過乾
燥後700〜800℃で予焼を行なったのちボールミル
粉砕した粉末をバインダー45 m f(j媒、可塑剤
と共に混合し混漿状にして絶縁体生シートの作製と同様
にドクターブレード法等のスリップキャスティング製膜
により10μm〜2001J1+のシー・トを得た。こ
こで用いた6電体拐料は、PI)(Fe+/zllJt
) +/z) Os  Pb (F e 2/s ・W
 +/a ) Os二元系複合ペロブスカイト化合物と
なるように原イ(を秤量した。
Dielectric raw sheet is Fetus, pbo, Nb*08, W
A predetermined amount of OI powder was weighed, mixed in a ball mill, filtered and dried, and pre-baked at 700 to 800°C. A sheet of 10 μm to 2001J1+ was obtained by slip casting film formation using a doctor blade method, etc. in the same manner as in the preparation of the insulator green sheet.
) +/z) Os Pb (F e 2/s ・W
+/a) The raw material (was weighed to form an Os binary composite perovskite compound).

また、抵抗体生シートは二酸化ルテニウム粉末と絶縁体
生シートの作製に用いた結晶化カラス粉末とをそれぞれ
重量比10:90〜50二!50  の範囲で所望の抵
抗値か得られるように混合し、エチルセルソルブ、ブチ
ルノクルヒトール、ブチルフタリル酸ブチルおよびポリ
ヒニルブチラール尋を加えて泥漿化し、」二連同様にf
#膜し20μm〜200μmのシートを得た。
In addition, the raw resistor sheet contains the ruthenium dioxide powder and the crystallized glass powder used for producing the raw insulator sheet in a weight ratio of 10:90 to 50, respectively! Mix to obtain the desired resistance value in the range of 50%, add ethyl cellosolve, butylnoclichtol, butyl butylphthalate, and polyhinylbutyral fat to form a slurry, and repeat in the same manner as above.
# A sheet with a thickness of 20 μm to 200 μm was obtained.

!8層および信号線に用いる導体は、Al1% Ag1
pd、pt等の金属の単体もしくはこれらを1以上含ん
だ合金粉末を有機ビヒクルと伴に混練しペースト状1こ
したものを使用した。
! The conductor used for the 8th layer and signal line is Al1% Ag1
Single metals such as PD and PT or alloy powders containing one or more of these metals were kneaded together with an organic vehicle to form a paste.

第5図〜第14図は本発明の1実施例による複合積層セ
ラミック部品とその製造方法を示したものである。各図
の(a’lは生シートの平面図、(ト))は断面図であ
る0製膜した絶縁体シートを所望の寸法にパンチングし
て第5図に示す絶縁体止シー) 20としてオリ用する
。才だ第6図に示す抵抗体生シート2工を準備する。
5 to 14 show a composite laminated ceramic component and a method of manufacturing the same according to one embodiment of the present invention. In each figure, (a'l is a plan view of the green sheet, and (g) is a cross-sectional view.) The formed insulator sheet is punched to desired dimensions and the insulator sheet shown in Figure 5 is used as 20. Ori use. Prepare two raw resistor sheets shown in Figure 6.

一力製膜した豹電体生ンートを第7図に示すように所望
の寸法1こパンチングして誘電体生シート22を得る。
As shown in FIG. 7, the dielectric raw sheet 22 is obtained by punching the dielectric raw sheet 22 to a desired size as shown in FIG.

次に金型1ノ−ザーおよびドリル等を用い通をもたすた
めのスルーホール%を形成する。ここで形成するスルー
ホール径は最小100μmまで可能であった。誘電体生
シートに関しても同様の手段でコンデンサー用内部電極
の導通のためのスルーホール23を形成する(第9図)
。一方抵抗体生シート21を所望の抵抗値が得られるよ
うに第10図に示したように設計寸法にパンチングおよ
び切断して抵抗体生シート片24を形成する。
Next, a through hole is formed using a mold 1 noser, a drill, etc. to provide a through hole. The diameter of the through hole formed here could be up to a minimum of 100 μm. Through-holes 23 for conducting the internal electrodes of the capacitor are formed using the same method for the dielectric raw sheet (Fig. 9).
. On the other hand, the resistor raw sheet 21 is punched and cut into designed dimensions as shown in FIG. 10 so as to obtain a desired resistance value, thereby forming a resistor raw sheet piece 24.

次に、第11図に示すようにスルーホールを設けた絶縁
体生シート上に信号線、シールド線用の導体層25をス
クリーン印刷法等により形成すると同時にスルーホール
部分に導体を埋め込む。導体としてはAu、Ag、Pc
t、pt等の金属の単体もしくはこれらを1以上含んだ
合金からなるペーストを使用した。
Next, as shown in FIG. 11, a conductor layer 25 for signal lines and shield lines is formed on the insulating green sheet provided with through holes by screen printing or the like, and at the same time, conductors are embedded in the through holes. As a conductor, Au, Ag, Pc
A paste consisting of a single metal such as T or PT or an alloy containing one or more of these metals was used.

また絶縁体生シートのスルーホール部分とその近傍に導
体を形成したものも作製した。
We also fabricated a raw insulator sheet with a conductor formed in the through-hole area and its vicinity.

スルーホール23を形成した誘電体生シート22に対し
ても第12図に示すようコンデン→J−用内部電極た導
体をスクリーン印刷等により印刷すると同時にスルーホ
ールお部分に上下電極の導通をもたせるために埋め込む
。一方所定寸法にパンチングおよび切断した抵抗体シー
ト片Uを第13図のように絶縁体生シート上へ接着又は
熱プレス等により貼り合せ一体化したシートを得る。
As shown in FIG. 12, on the dielectric green sheet 22 with the through-holes 23 formed, a conductor for the internal electrodes for condensation → J- is printed by screen printing or the like, and at the same time, in order to provide continuity between the upper and lower electrodes at the through-hole portions. Embed in. On the other hand, as shown in FIG. 13, resistor sheet pieces U punched and cut into predetermined dimensions are laminated onto a raw insulator sheet by adhesive or hot press to obtain an integrated sheet.

次に第14図Iこ示すように第11図、第12図および
第13図のそれぞれのシートおよび積層体の厚みを住 調整するための第5図の絶縁体舛隼二千シート及びスル
ーポール部分とその近傍に導体を形成した絶縁体生シー
トを100〜130℃の温度で圧力200〜300 K
97−で積層プレスした。第14図において多数枚積み
重ねたffj電体生シート22の上下に導体層26は焼
結後コンデンサー形成部分32(図に破線で示す)とな
り、スルーホールおおよび導体層を経由して外部端子用
導体Jfia 33 iこつながっている。
Next, as shown in FIG. 14, the insulator sheets and through poles in FIG. 5 are used to adjust the thickness of the sheets and laminates in FIGS. A raw insulator sheet with a conductor formed in the area and its vicinity is heated at a temperature of 100 to 130°C and a pressure of 200 to 300 K.
97- was laminated and pressed. In Fig. 14, the conductor layers 26 on the upper and lower sides of the FFJ electric raw material sheets 22 stacked in large numbers become capacitor forming portions 32 (indicated by broken lines in the figure) after sintering, and are connected to external terminals via through holes and conductor layers. The conductor Jfia 33 is connected.

生 また几uO菅系抵抗体処+−守シ−ト24も81層およ
び焼成す・ることにより抵抗部分31 (図で破線で示
ず部分)が形成できスルーボール23 r++よひ橢1
体稼等により、外部へ導かれている。このように積層熱
圧着した積層体を所望の寸法にしJト勇し、7ALS図
に示した温度プロファイルによって焼成した。焼成プロ
ファイルは3・つの工程から成っており、脱バインダ一
工程、仮焼成工程および本焼成工程である。脱バインダ
ーは、最高400℃の温度て3時間保持し、仮焼成は8
0Q’Ctた木1,11ε成は900″Cの各温度で連
続炉を使用した。
By forming the 81 layers of the raw UO tube-based resistor sheet 24 and firing it, the resistance portion 31 (portion not shown by the broken line in the figure) can be formed.
They are led to the outside world by their physical performance, etc. The laminate thus laminated and thermocompressed was made into a desired size and fired according to the temperature profile shown in Figure 7ALS. The firing profile consists of three steps: a binder removal step, a preliminary firing step, and a main firing step. Binder removal is held at a maximum temperature of 400°C for 3 hours, and pre-calcination is performed at 8
A continuous furnace was used at each temperature of 900''C for 0Q'Ct wood 1,11ε.

本発明は、900℃という従来に比して低い温度で抵抗
体、U電体、絶縁体、および導体を仮台化して同時焼成
費jようことにより抵抗、コンランリー、信号線、シー
ルド層等を含めた火合偵11☆セラミック部品を作製す
ることが出来た。
The present invention makes it possible to temporarily form resistors, U electric bodies, insulators, and conductors at a temperature as low as 900 degrees Celsius compared to conventional methods, and simultaneously fire the resistors, conductors, signal lines, shield layers, etc. We were able to fabricate 11☆ ceramic parts for the Fire Detective, including the following.

実施例2 本例の複合8L層セラミック部品の製造工程は大部分実
施例1て説明した工程と五復づ−るか、実施例1て用い
た生シートを積層する際槓バ近体の両面lこ外部端子用
導体層を設けた第16図に示1ようは構造の複合積層中
ラミック部品を得ることか出来る。この場合、積層部品
の上下面を有効に利用すると走が出来るため、より高密
度で微小な複合積層セラミック部品となる利点がある。
Example 2 The manufacturing process of the composite 8L layer ceramic component of this example is mostly the same as the process described in Example 1, or when the raw sheets used in Example 1 are laminated, both sides of the laminate and the near body are It is possible to obtain a laminated composite laminated component having the structure shown in FIG. 16, in which a conductor layer for external terminals is provided. In this case, by effectively utilizing the upper and lower surfaces of the laminated component, it is possible to run, which has the advantage of producing a higher-density and finer composite laminated ceramic component.

本発明の実施例により得たコンデンサ、抵抗、導体付複
合積層セラミック部品中に形成したコンデンサの容量と
しては、約1 n I;’/wn’ 程度であり一例と
して最大10μFのコンデン→Jを形成した。
The capacitance of the capacitor, resistor, and capacitor formed in the composite laminated ceramic component with conductor obtained according to the embodiment of the present invention is about 1 n I;'/wn', and as an example, a maximum of 10 μF capacitor→J is formed. did.

高BM1体材料としてはP b (F e ’1/2 
・Nb II2 )Os−Pb (Fe 2/3 ・V
i l/s ) Q、二元系複合ペロブスカイト化合物
以外にも850℃〜950℃程度で焼結出来る材料であ
れば使用は可能である。
As a high BM 1-body material, P b (F e '1/2
・Nb II2 ) Os-Pb (Fe 2/3 ・V
i l/s ) Q. In addition to the binary composite perovskite compound, any material that can be sintered at about 850°C to 950°C can be used.

以上のように本発明の積層構造のコンデンサ、抵抗及び
導体配線を有する複合積層セラミック部品は酸化性界囲
気下で900℃程度の低温で同時焼成して複数個の几C
を構成することが可能で、また大容量のコンデンサを形
成した小型高密度な部品あるいは、機械的強度の十分な
高密度大面積実装用複合基板が得られ、工程の簡略化、
コスト低下等で作業性、信頼性の向上を実現でき、高導
電率導体の利用が可能である等の利煮がある。
As described above, the composite laminated ceramic component having the laminated structure of the capacitor, resistor, and conductor wiring of the present invention is produced by simultaneously firing at a low temperature of about 900°C in an oxidizing ambient atmosphere, and then forming a plurality of ceramics.
It is also possible to construct small, high-density components with large capacitors formed, or composite boards with sufficient mechanical strength for high-density, large-area mounting, simplifying the process,
There are advantages such as lower cost, improved workability and reliability, and the ability to use conductors with high electrical conductivity.

また本発明の複合MP部品はテレビ用チ。−す+、FM
チー−チー自動車用各種回路等あらゆる電子回路に利用
可能である。
The composite MP component of the present invention is also suitable for use in televisions. -S+, FM
It can be used in all kinds of electronic circuits such as various circuits for Qi-Chi automobiles.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来部品の断面4S第2図、H’t :3図は
従来部品の余1視図、第4図は従来部品の断面口、第5
図〜・第13図(オ木発明の実施例1(−よるゆr]豊
層セラミック、部品の各製造工程を示す図。 第1−1図C:【実施例1の完成部品の模式的内FiK
 Ifノア 1lii図、第15図は水沢、明の711
−品の焼成プロファイル、第16図は実施例2の完成部
品の模式的内部NJi而し]であるO Mにおいて J・・・・・・アルミナシート、  2・・・・・・、
!、Q、 体1.3・・・・・・コンデンザ形成部分、
  4・・・・・・誘”i[i、 4 I?j、  り
・・・・・・抵抗体、II・・・・・・外部電極、 J
2・・・・・・抵抗、1:3・・・・・・積層コンテ′
ンサ、14・・・・・・コノラン“す゛川内部電極、1
5・・・・・・討↑E体、1G・・・・・・絶縁体、 
20・・・・・・絶縁体生シート、2ト・・・・・1)
(抗体生シート、22・・・・・M 電f本生シート、
23・・・・・・スルーポール24・・・・・・抵抗体
生シート片、25.26・・・・・・導体層、31・・
・・・・抵抗形成部分、32・・・・・・コンデンサ形
成部分、3;3・・・・・・外部端子用導体層。
Figure 1 is a cross-sectional view of a conventional part; Figure 2 is a cross-sectional view of the conventional part;
Figures ~ Figure 13 (Example 1 of Oki Invention (-Yoruyur) A diagram showing each manufacturing process of rich layered ceramic parts. Figure 1-1C: [Schematic diagram of completed parts of Example 1 Inner FiK
If Noah Figure 1lii, Figure 15 is Mizusawa, Ming 711
- firing profile of the product, Fig. 16 is a schematic internal view of the completed part of Example 2] J... Alumina sheet, 2...
! , Q, Body 1.3...Condenser forming part,
4...I"i[i, 4 I?j, Ri...Resistor, II...External electrode, J
2...Resistance, 1:3...Laminated container'
Nsa, 14... Conoran "Sukawa Internal Electrode, 1"
5...Discussion↑E body, 1G...Insulator,
20...Insulator raw sheet, 2 tons...1)
(Antibody raw sheet, 22...M electric fon raw sheet,
23... Through pole 24... Resistor raw sheet piece, 25.26... Conductor layer, 31...
...Resistance forming part, 32... Capacitor forming part, 3; 3... Conductor layer for external terminal.

Claims (1)

【特許請求の範囲】 (1)絶縁体、誘電体、抵抗体、導体がそれぞれ治機物
と混合され、シート状又はペースト状になったものが一
体に成型され、焼成されてなる積層焼結体であって、そ
の内部1こ1以上のコンデンサ素子と1以上の抵抗素子
と配線用導電体を備えてなることを特徴とする腹合積層
セラミック部品(2)誘電体層と抵抗体層はそれぞれ1
層以上であり、誘電体層の両面にはコンデンサ用電極が
形成されており、該電極は誘電体層及び絶縁体層中Zこ
形成されたスルーホール中に充填、形成された導電体と
導電体層とを介して該積層焼結体表面に形成された外部
端子用導体層に接続されており、抵抗体層にも電極が接
続し、該電極は前記積層焼結と同様に接続されているこ
とを特徴とする特許請求の範囲第1項記載の複合偵屑セ
ラミック部品。 (3)銹電体生シートと抵抗体生シートおよび絶縁体生
シートを形成する工程と絶縁体生シートおよび誘電体生
シートにスルーホールを穿設して該スルーホールに導電
性物質を充填すると同時に導体層を表面に形成する工程
と抵抗体生シートを所望の形状Iこ切断し、前記スルー
ホールが設けられ孔中に導電性物質が充填された絶縁体
生シート面又はスルーホールを設けていない絶縁体生シ
ート面に接するよう1こ積層する工程とそれぞれの生シ
ートを積層熱圧着して積層体を形成する工程と該積層体
を所定の大きさに切断し、焼成する工程を有することを
%敵とする複合積屓七ラミック部品の製造方法。
[Scope of Claims] (1) Laminated sintered material in which insulators, dielectrics, resistors, and conductors are mixed with electrical equipment and formed into a sheet or paste, which is then integrally molded and fired. (2) A dielectric layer and a resistor layer, which are characterized by having one or more capacitor elements, one or more resistor elements, and a wiring conductor inside. 1 each
The capacitor electrodes are formed on both sides of the dielectric layer, and the electrodes are filled with through holes formed in the dielectric layer and the insulator layer, and are connected to the conductor formed therein. The resistor layer is connected to the external terminal conductor layer formed on the surface of the laminated sintered body through the body layer, and an electrode is also connected to the resistor layer, and the electrode is connected in the same manner as in the laminated sintered body layer. A composite ceramic part according to claim 1, characterized in that: (3) Steps of forming electric raw sheets, resistor raw sheets, and insulator raw sheets, and forming through-holes in the insulator raw sheets and dielectric raw sheets and filling the through-holes with a conductive material. At the same time, a step of forming a conductive layer on the surface and cutting the raw resistor sheet into a desired shape and providing the surface of the raw insulator sheet with the through holes and the holes filled with a conductive material or through holes are performed. The method includes the steps of laminating one insulator green sheet so as to be in contact with the surface of the green insulator sheet, forming a laminate by laminating and thermocompressing each green sheet, and cutting the laminate into a predetermined size and firing it. A method of manufacturing composite laminated lamic parts using % as enemy.
JP57126176A 1982-07-20 1982-07-20 Composite laminated ceramic part and method of producing same Pending JPS5917232A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57126176A JPS5917232A (en) 1982-07-20 1982-07-20 Composite laminated ceramic part and method of producing same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57126176A JPS5917232A (en) 1982-07-20 1982-07-20 Composite laminated ceramic part and method of producing same

Publications (1)

Publication Number Publication Date
JPS5917232A true JPS5917232A (en) 1984-01-28

Family

ID=14928558

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57126176A Pending JPS5917232A (en) 1982-07-20 1982-07-20 Composite laminated ceramic part and method of producing same

Country Status (1)

Country Link
JP (1) JPS5917232A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6178116A (en) * 1984-09-25 1986-04-21 日本電気株式会社 Multilayer hybrid electronic component
JPS6179218A (en) * 1984-09-26 1986-04-22 日本電気株式会社 Multilayer hybrid electronic component
JPS62102596A (en) * 1985-10-29 1987-05-13 松下電器産業株式会社 Manufacture of ceramic multilayer wiring substrate
JPS6416670U (en) * 1987-07-21 1989-01-27
JPS6447099A (en) * 1987-08-18 1989-02-21 Nec Corp Ceramic composite substrate
JPH01312896A (en) * 1988-06-09 1989-12-18 Murata Mfg Co Ltd Ceramic multilayer substrate
JPH0415906A (en) * 1990-05-09 1992-01-21 Toko Inc Manufacture of laminated electronic parts
JPH0433397A (en) * 1990-05-30 1992-02-04 Fujitsu Ltd Manufacture of ceramic substrate
US6563058B2 (en) 2000-03-10 2003-05-13 Ngk Insulators, Ltd. Multilayered circuit board and method for producing the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5378100A (en) * 1976-12-22 1978-07-11 Hitachi Ltd High permittivity thick film capacitor paste compound
JPS56142622A (en) * 1980-04-07 1981-11-07 Tdk Electronics Co Ltd Method of manufacturing composite part

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5378100A (en) * 1976-12-22 1978-07-11 Hitachi Ltd High permittivity thick film capacitor paste compound
JPS56142622A (en) * 1980-04-07 1981-11-07 Tdk Electronics Co Ltd Method of manufacturing composite part

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6178116A (en) * 1984-09-25 1986-04-21 日本電気株式会社 Multilayer hybrid electronic component
JPS6179218A (en) * 1984-09-26 1986-04-22 日本電気株式会社 Multilayer hybrid electronic component
JPS62102596A (en) * 1985-10-29 1987-05-13 松下電器産業株式会社 Manufacture of ceramic multilayer wiring substrate
JPS6416670U (en) * 1987-07-21 1989-01-27
JPS6447099A (en) * 1987-08-18 1989-02-21 Nec Corp Ceramic composite substrate
JPH0525399B2 (en) * 1987-08-18 1993-04-12 Nippon Electric Co
JPH01312896A (en) * 1988-06-09 1989-12-18 Murata Mfg Co Ltd Ceramic multilayer substrate
JPH0415906A (en) * 1990-05-09 1992-01-21 Toko Inc Manufacture of laminated electronic parts
JPH0614495B2 (en) * 1990-05-09 1994-02-23 東光株式会社 Method for manufacturing laminated electronic component
JPH0433397A (en) * 1990-05-30 1992-02-04 Fujitsu Ltd Manufacture of ceramic substrate
US6563058B2 (en) 2000-03-10 2003-05-13 Ngk Insulators, Ltd. Multilayered circuit board and method for producing the same

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