JPH03280496A - Electronic copmponent mounting structure and method of packaging - Google Patents
Electronic copmponent mounting structure and method of packagingInfo
- Publication number
- JPH03280496A JPH03280496A JP2080437A JP8043790A JPH03280496A JP H03280496 A JPH03280496 A JP H03280496A JP 2080437 A JP2080437 A JP 2080437A JP 8043790 A JP8043790 A JP 8043790A JP H03280496 A JPH03280496 A JP H03280496A
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- electronic components
- chip
- substrates
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 15
- 238000004806 packaging method and process Methods 0.000 title abstract 2
- 239000004020 conductor Substances 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims description 60
- 238000010030 laminating Methods 0.000 claims description 5
- 238000005476 soldering Methods 0.000 abstract description 5
- 238000003780 insertion Methods 0.000 abstract 1
- 230000037431 insertion Effects 0.000 abstract 1
- 239000000919 ceramic Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000004040 coloring Methods 0.000 description 1
- 239000006071 cream Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、多層基板にチップ状の電子部品を実装する構
造及び実装方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a structure and a mounting method for mounting chip-shaped electronic components on a multilayer board.
（従来の技術）
近年、電子回路の小型化、高密度化に伴って、複数枚の
基板を積層してなる多層基板が多く用いられている。な
かでもセラミック多層基板は導体パターンを形成する際
に、高密度化が可能なため広く採用されている。また、
積層中に抵抗器やコンデンサ等の部品を内蔵し、より高
密度な部品実装を図った多層基板も知られている。(Prior Art) In recent years, with the miniaturization and increase in density of electronic circuits, multilayer substrates formed by laminating a plurality of substrates are often used. Among these, ceramic multilayer substrates are widely used because they allow for higher density when forming conductor patterns. Also,
Multilayer boards are also known in which parts such as resistors and capacitors are built into the laminated layers to achieve higher density mounting of parts.
一方、基板に実装される電子部品自体の形状も小型化さ
れ、半導体電子部品においては基板上にチップ状の電子
部品を搭載すると共に、この電子部品と基板に形成され
た導体パターンとの間をワイヤーボンディングによって
接続し、電子部品の高密度実装を図っている。On the other hand, the shape of the electronic components themselves mounted on the substrate has become smaller, and in semiconductor electronic components, chip-shaped electronic components are mounted on the substrate, and the distance between the electronic components and the conductor pattern formed on the substrate is reduced. Connections are made using wire bonding, allowing for high-density mounting of electronic components.
さらに、基板へのチップ状電子部品の高密度実装を図る
ための技術としてＴ Ａ Ｂ （Ｔａｐｅ ＡｕｔＯｆ
ｆｌａｔｅｄ Ｂｏｎｄｉｎｇ）技術か知られている。Furthermore, TAB (Tape OutOf
flat bonding) technology is known.
これは第２ａ図に示すように、長いフィルムキャリヤ１
の１駒ごとにフィルムリード２を形成し、フィルムリー
ド２にチップ状の電子部品３をインナーリードボンディ
ングして、電子部品３の運搬を自動的に行う。さらに、
第２ｂ図に示すように、この電子部品３を基板４に実装
する際には、フィルムキャリヤ１からフィルムリード２
の部分を含めて電子部品３を切り離し、基板４に形成さ
れた導体パタン５にフィルムリード２を半田付けによっ
てアウターリードボンディングする。これにより、前述
したようにフィルムリード２か接続されたチップ状の電
子部品３を自動的に運搬することができる。This is shown in Figure 2a, with a long film carrier 1.
A film lead 2 is formed for each frame, a chip-shaped electronic component 3 is bonded to the film lead 2 by inner lead bonding, and the electronic component 3 is automatically transported. moreover,
As shown in FIG. 2b, when mounting this electronic component 3 on the board 4, from the film carrier 1 to the film lead 2,
The electronic component 3 including the part is separated, and the film lead 2 is outer lead bonded to the conductor pattern 5 formed on the substrate 4 by soldering. Thereby, as described above, the chip-shaped electronic component 3 connected to the film lead 2 can be automatically transported.
さらに、基板４への実装の際にワイヤーボンデインクを
行わずにすむので、第２ｂ図に示すようにチップ状の電
子部品３を積み重ねて実装することができ、部品の実装
密度を高めることができる。Furthermore, since there is no need to perform wire bonding when mounting on the board 4, chip-shaped electronic components 3 can be stacked and mounted as shown in FIG. 2b, and the mounting density of components can be increased. can.
（発明が解決しようとする課題）
前述したＴＡＢ技術によって基板４上の少ない面積内に
多数のチップ状電子部品３を実装することが可能となっ
た。しかしながら、基板４上に電子部品３を積み重ねて
いるので、部品実装高さが増加し、電子回路全体の形状
を小型にすることができないという問題点があった。(Problems to be Solved by the Invention) The TAB technique described above has made it possible to mount a large number of chip-shaped electronic components 3 within a small area on the substrate 4. However, since the electronic components 3 are stacked on the board 4, there is a problem in that the component mounting height increases and the overall shape of the electronic circuit cannot be made smaller.
本発明の目的は上記の問題点に鑑み、多層基板の少ない
面積内に複数のチップ状電子部品を高密度実装すること
ができると共に、部品実装高さを低減できる多層基板の
電子部品実装構造及びその実装方法を提供することにあ
る。In view of the above-mentioned problems, an object of the present invention is to provide an electronic component mounting structure for a multilayer board that can mount a plurality of chip-shaped electronic components at a high density within a small area of a multilayer board and reduce the height of component mounting. The purpose is to provide an implementation method.
（課題を解決するための手段）
本発明は上記の目的を達成するために、請求項（１）で
は、所定の導体パターンが形成された複数枚の基板を積
層してなる多層基板に、複数のチップ状の電子部品を実
装する多層基板の電子部品実装構造であって、前記電子
部品の実装位置に対応して所定形状の貫通孔を有し、該
貫通孔が対応するように隣接して積層された複数枚の基
板と、前記貫通孔に挿入され、前記基板の積層方向に所
定間隔をあけて重置された複数のチップ状の電子部品と
、該複数の電子部品のそれぞれを所定の基板の導体パタ
ーンに接続する複数のフィルムリードとからなる多層基
板の電子部品実装構造を提案する。(Means for Solving the Problems) In order to achieve the above object, the present invention provides a multilayer substrate formed by laminating a plurality of substrates each having a predetermined conductor pattern formed thereon. An electronic component mounting structure of a multilayer board on which a chip-shaped electronic component is mounted, which has a through hole of a predetermined shape corresponding to the mounting position of the electronic component, and the through hole is adjacent so as to correspond to the mounting position of the electronic component. A plurality of stacked substrates, a plurality of chip-shaped electronic components inserted into the through holes and placed one on top of the other at predetermined intervals in the stacking direction of the substrates, and each of the plurality of electronic components in a predetermined manner. We propose an electronic component mounting structure on a multilayer board consisting of a plurality of film leads connected to the conductor pattern of the board.
また、請求項（２）では、所定の導体パターンが形成さ
れた複数枚の基板を積層してなる多層基板に複数のチッ
プ状の電子部品を実装する多層基板の電子部品実装方法
であって、前記複数枚の基板のそれぞれに、前記電子部
品の実装位置に対応して所定形状の貫通孔を形成すると
共に、前記各基板の所定位置にスルーホールを形成し、
前記各基板のそれぞれに所定の導体パターンを形成する
と共に、前記複数枚の基板を隣接させ、かつ前記各基板
の貫通孔を対応させ、該複数枚の基板を積層して前記複
数の貫通孔からなる部品配置孔を有する多層基板を形成
した後、フィルムリードにインナーリードボンディング
されたチップ状の電子部品を前記部品配置孔に挿入し、
該電子部品のフィルムリード゛を対応する基板の導体？
々ターンにアウターリードボンディングし、この後、該
電子部品に所定間隔をあけて、同様にフィルムリードに
インナーリードボンディングされた他のチップ状の電子
部品を重置し、該電子部品のフィルムリードを対応する
基板の導体パターンにアウターリードボンディングする
多層基板の電子部品実装方法を提案する。Further, claim (2) provides a method for mounting electronic components on a multilayer board, in which a plurality of chip-shaped electronic components are mounted on a multilayer board formed by laminating a plurality of boards on which predetermined conductor patterns are formed, forming a through hole of a predetermined shape in each of the plurality of substrates corresponding to a mounting position of the electronic component, and forming a through hole at a predetermined position of each of the substrates;
A predetermined conductive pattern is formed on each of the substrates, the plurality of substrates are arranged adjacent to each other, and the through holes of the respective substrates are made to correspond to each other, and the plurality of substrates are stacked and the through holes are connected to each other. After forming a multilayer board having a component placement hole, inserting a chip-shaped electronic component with inner lead bonding to a film lead into the component placement hole,
Is the film lead of the electronic component the conductor of the corresponding board?
After that, another chip-shaped electronic component, which is similarly bonded to the film lead, is placed on the electronic component at a predetermined interval, and the film lead of the electronic component is bonded to the outer lead. We propose a method for mounting electronic components on a multilayer board by outer lead bonding to the conductor pattern of the corresponding board.
（作 用）
本発明の請求項（１）によれば、貫通孔を対応させて複
数枚の基板が積層される。また、前記貫通孔にチップ状
の電子部品が挿入され、該電子部品は対応する基板の導
体パターンにフィルムリードを介して接続される。さら
に、この電子部品に対して、前記基板の積層方向に所定
間隔をあけて他のチップ状の電子部品が重置され、該電
子部品は対応する基板の導体パターンにフィルムリード
を介して接続される。同様にして、１つの貫通孔に所定
個数の電子部品が挿入され、フィルムリードを介して対
応する基板の導体パターンに接続される。(Function) According to claim (1) of the present invention, a plurality of substrates are stacked with corresponding through holes. Further, a chip-shaped electronic component is inserted into the through hole, and the electronic component is connected to a conductive pattern of a corresponding board via a film lead. Furthermore, other chip-shaped electronic components are superimposed on this electronic component at predetermined intervals in the stacking direction of the substrate, and the electronic component is connected to the conductor pattern of the corresponding substrate via a film lead. Ru. Similarly, a predetermined number of electronic components are inserted into one through hole and connected to the corresponding conductor pattern of the board via the film lead.
また、請求項（２）によれば、複数枚の基板のそれぞれ
に、電子部品の実装位置に対応して所定形状の貫通孔が
形成されると共に、各基板のそれぞれの所定位置にスル
ーホールが形成され、さらに所定の導体パターンが形成
される。この後、前記貫通孔を対応させて、前記複数枚
の基板が隣接され、これら複数枚の基板が積層されて多
層基板が形成される。この後、フィルムリードにインナ
ーリードボンディングされたチップ状の電子部品が前記
複数の貫通孔からなる部品配置孔に挿入され、該電子部
品のフィルムリードが対応する基板の導体パターンにア
ウターリードボンディングされる。Further, according to claim (2), a through hole of a predetermined shape is formed in each of the plurality of substrates corresponding to the mounting position of the electronic component, and a through hole is formed in a predetermined position of each of the plurality of substrates. A predetermined conductor pattern is then formed. Thereafter, the plurality of substrates are placed adjacent to each other with the through holes corresponding to each other, and the plurality of substrates are stacked to form a multilayer substrate. Thereafter, a chip-shaped electronic component with inner lead bonding to the film lead is inserted into the component placement hole made up of the plurality of through holes, and the film lead of the electronic component is outer lead bonded to the corresponding conductor pattern of the board. .
さらに、この電子部品に所定間隔をあけて、同様にフィ
ルムリードにインナーリードボンディングされた他のチ
ップ状の電子部品が重置され、該電子部品のフィルムリ
ードが対応する基板の導体パターンにアウターリードボ
ンディングされる。Furthermore, another chip-shaped electronic component, which is similarly bonded to the film lead with the inner lead, is placed on top of this electronic component at a predetermined interval, and the film lead of the electronic component is attached to the corresponding conductor pattern of the board with the outer lead. Bonded.
（実施例）
第１ａ図は本発明の一実施例の要部を示す側面断面図、
第１ｂ図は一実施例を示す分解斜視図である。図におい
て、１０はセラミック材からなる５枚の基板１１〜１５
を積層してなる多層基板である。最上層に位置する第１
の基板１１と、この第１の基板１１の下側に積層された
第２乃至第５の基板１２〜１５のそれぞれには、チップ
状の電子部品１６．１７の実装位置に対応して所定形状
の貫通孔１１ａ、１２ａ、１３ａ、１４ａ、１５ａが形
成されている。本実施例では、これらの貫通孔１１ａ、
１２ａ、１３ａ、１４ａ、１５ａに２個のチップ状電子
部品１６．１７を重ねて挿入し、実装している。即ち、
第１乃至第３の基板１１〜１３のそれぞれには、下側に
位置する電子部品１６の形状よりも大きく、かつ電子部
品１７を挿入可能な形状の貫通孔１１ａ、１２ａ、１３
ａが形成されている。第４及び第５の基板１４，１５に
は貫通孔１１ａ、１２ａ、１３ａよりも小さく、かつ電
子部品１７を挿入可能な貫通孔１４ａ１５ａか形成され
ている。これらの貫通孔１１ａ。(Embodiment) FIG. 1a is a side sectional view showing the main part of an embodiment of the present invention.
FIG. 1b is an exploded perspective view showing one embodiment. In the figure, 10 indicates five substrates 11 to 15 made of ceramic material.
It is a multilayer board made by laminating layers. The first layer located on the top layer
The substrate 11 and the second to fifth substrates 12 to 15 stacked below the first substrate 11 each have a predetermined shape corresponding to the mounting position of the chip-shaped electronic components 16 and 17. Through holes 11a, 12a, 13a, 14a, and 15a are formed. In this embodiment, these through holes 11a,
Two chip-shaped electronic components 16 and 17 are inserted and mounted in layers 12a, 13a, 14a, and 15a. That is,
Each of the first to third substrates 11 to 13 has through holes 11a, 12a, 13 which are larger than the shape of the electronic component 16 located below and have a shape into which the electronic component 17 can be inserted.
a is formed. A through hole 14a15a is formed in the fourth and fifth substrates 14 and 15, which is smaller than the through holes 11a, 12a, and 13a, and into which the electronic component 17 can be inserted. These through holes 11a.
１２ａ、１３ａ、１４ａ、１５ａが連結されて部品配置
孔１８か形成される。また各基板１１〜１５のそれぞれ
には、所定位置に複数のスルーホール１９か形成される
と共に、所定の導体パターン２０が形成されている。12a, 13a, 14a, and 15a are connected to form a component placement hole 18. Further, in each of the substrates 11 to 15, a plurality of through holes 19 are formed at predetermined positions, and a predetermined conductor pattern 20 is also formed.
さらに、多層基板１０へは前述したＴＡＢ技術によって
電子部品１６．１７が実装される。即ち、第２ａ図に示
すフィルムキャリヤ１によって搬送された電子部品１６
は、フィルムキャリヤ１からフレームリード２の部分を
含めて切り離され、部品配置孔１８の下部に挿入された
後、フレームリード２が貫通孔１４ａの周縁部、即ち第
４の基板１４の上面に形成された導体パターン２０に半
田付けによってアウターリードボンディングされる。Further, electronic components 16 and 17 are mounted on the multilayer board 10 using the TAB technique described above. That is, the electronic component 16 transported by the film carrier 1 shown in FIG. 2a
is separated from the film carrier 1 including the frame lead 2 portion and inserted into the lower part of the component placement hole 18, and then the frame lead 2 is formed on the periphery of the through hole 14a, that is, on the upper surface of the fourth substrate 14. The outer lead is bonded to the conductor pattern 20 by soldering.
このとき、電子部品１６とフレームリード２とのインナ
ーリードボンディング部分は上側に位置される。また、
電子部品１６．１７の表面及びインナーリードボンディ
ング部分には絶縁のため予めエポキシ系保護樹脂Ｅが塗
布されている。この後、前述と同様にして電子部品１７
が電子部品１６の上部に所定間隔をあけて重置され、こ
の電子部品１７のフレームリード２は貫通孔１１ａの周
縁部、即ち第１の基板１１の上面に形成された導体７寸
ターン２０にアウターリードボンディングされる。At this time, the inner lead bonding portion between the electronic component 16 and the frame lead 2 is located on the upper side. Also,
Epoxy-based protective resin E is applied in advance to the surfaces and inner lead bonding parts of the electronic components 16 and 17 for insulation. After this, the electronic component 17 is
are placed on top of the electronic component 16 at a predetermined interval, and the frame lead 2 of the electronic component 17 is connected to the 7-inch conductor turn 20 formed on the periphery of the through hole 11a, that is, on the top surface of the first substrate 11. Outer lead bonding is performed.
次に、前述した構成における多層基板１０への電子部品
１６．１７の実装方法を説明する。Next, a method for mounting the electronic components 16 and 17 on the multilayer board 10 in the above-described configuration will be described.
まず、高温度で焼結する前のセラミ・ンクからなる第１
乃至第５の基板１１〜１５のそれぞれに金型を用いて所
定のスルーホール１９を形成する。First, the first layer consists of ceramic ink before being sintered at high temperature.
Predetermined through holes 19 are formed in each of the fifth substrates 11 to 15 using a mold.
また、これと同時に第１乃至第５の基板１１〜１５のそ
れぞれに前述した貫通孔１１ａ、’１２ａ。At the same time, the through holes 11a and '12a described above are formed in each of the first to fifth substrates 11 to 15.
１３ａ、１４ａ、１５ａを形成する。この後、各基板１
１〜１５の表面にＡｇ系ペースト及びＡｕペーストを用
いて、所定の導体パターン２０をスクリーン印刷すると
共に、各スルーホール１９の内部にＡｇ系ペーストを充
填する。13a, 14a, and 15a are formed. After this, each board 1
A predetermined conductor pattern 20 is screen-printed on the surface of each of the through holes 1 to 15 using an Ag-based paste and an Au paste, and the inside of each through-hole 19 is filled with the Ag-based paste.
次に、第１乃至第５の基板１１〜１５を前述した順序で
積層して圧着する。さらに、脱ノくインダ処理を行った
後、積層した第１乃至第５の基板１１〜１５を所定温度
、例えば９４０°Ｃの温度で焼結する。次いで第１及び
第５の基板１１．１５の表面に電極、抵抗及びオーバー
コートガラス等（図示せず）を印刷し、乾燥し、焼成し
て多層基板１０を形成する。この後、前記電極上に半田
スクリーンを用いてクリーム半田を印刷し、コンデンサ
等の部品（図示せず）をマウントした後、図示せぬりフ
ロー装置によて半田付けを行う。Next, the first to fifth substrates 11 to 15 are stacked and pressure-bonded in the above-described order. Further, after performing a de-inder treatment, the laminated first to fifth substrates 11 to 15 are sintered at a predetermined temperature, for example, 940°C. Next, electrodes, resistors, overcoat glass, etc. (not shown) are printed on the surfaces of the first and fifth substrates 11.15, dried, and fired to form the multilayer substrate 10. After that, cream solder is printed on the electrodes using a solder screen, parts such as a capacitor (not shown) are mounted, and soldering is performed using a coloring flow device (not shown).
一方、チップ状の電子部品１６．１７は周知の転写バン
ブ方式によってフィルムキャリヤ１のフィルムリード２
にインナーリードボンディングされる。この後、電子部
品１６．１７の表面及びインナーリードボンディング部
分にエポキシ系保護樹脂Ｅを塗布する。次いで、電子部
品１６．１７の電気的な検査を行った後、部品配置孔１
８の下部に挿入される電子部品１６をフィルムキャリヤ
１からフィルムリード２を含めて切り離すと共に、図示
せぬ搬送装置によって、切り離された電子部品１６を真
空吸着して多層基板１０の部品配置孔１８の位置に搬送
し、部品配置孔１８の下部に挿入する。さらに、フィル
ムリード２と第４の基板１４の上面に形成された導体パ
ターン２０との位置合わせを行い、半田付けによってア
ウターリドボンディングする。On the other hand, chip-shaped electronic components 16 and 17 are transferred to the film lead 2 of the film carrier 1 by a well-known transfer bump method.
Inner lead bonding is performed. After this, an epoxy-based protective resin E is applied to the surfaces of the electronic components 16 and 17 and the inner lead bonding portions. Next, after electrically inspecting the electronic components 16 and 17, the component placement holes 1
The electronic component 16 to be inserted into the lower part of the multilayer substrate 10 is separated from the film carrier 1 including the film lead 2, and the separated electronic component 16 is vacuum-suctioned by a conveying device (not shown) to the component placement hole 18 of the multilayer substrate 10. and insert it into the lower part of the component placement hole 18. Further, the film lead 2 and the conductor pattern 20 formed on the upper surface of the fourth substrate 14 are aligned, and outer lead bonding is performed by soldering.
次に、前述と同様にして電子部品１７をフィルムキャリ
ヤ１から切り離し、部品配置孔１８に挿入して電子部品
１６の上に所定間隔をあけて重置する。さらに、電子部
品１７のフィルムリードと第１の基板１１の上面に形成
された導体／＜ターン２０との位置合せを行い、アウタ
ーリードボンディングする。この後、電子部品１６．１
７の表面にシリコーン樹脂（図示せず）を塗布する。Next, in the same manner as described above, the electronic component 17 is separated from the film carrier 1, inserted into the component placement hole 18, and placed on top of the electronic component 16 at a predetermined interval. Further, the film lead of the electronic component 17 and the conductor/< turn 20 formed on the upper surface of the first substrate 11 are aligned, and outer lead bonding is performed. After this, electronic parts 16.1
Apply silicone resin (not shown) to the surface of 7.
前述したように、本実施例によれば、多層基板の少ない
面積内に複数のチップ状電子部品１６゜１７を高密度で
実装することができる。さらに、前記電子部品１６．１
７の実装高さを従来よりも低減することができるので、
電子回路全体の形状を小型にすることが可能となる。As described above, according to this embodiment, a plurality of chip-shaped electronic components 16 and 17 can be mounted at high density within a small area of a multilayer board. Furthermore, the electronic component 16.1
Since the mounting height of 7 can be reduced compared to the conventional one,
It becomes possible to reduce the size of the entire electronic circuit.
尚、本実施例では、第１乃至第５の基板１１〜１５によ
って多層基板１０を構成したが、これに限定されること
はない。In this embodiment, the multilayer substrate 10 is composed of the first to fifth substrates 11 to 15, but the present invention is not limited to this.
また、本実施例では２個のチップ状電子部品１６．１７
を積み重ねて貫通孔１１ａ、１２ａ。In addition, in this embodiment, two chip-shaped electronic components 16 and 17 are used.
are stacked to form through holes 11a and 12a.
１３ａに挿入し、多層基板１０に実装したが、２個以上
の電子部品を積み重ねて実装するようにしても同様の効
果を得ることができる。13a and mounted on the multilayer board 10, the same effect can be obtained even if two or more electronic components are stacked and mounted.
さらに、本実施例ではセラミックによって多層基板１０
を形成したが、これに限定されないことは言うまでもな
いことである。Furthermore, in this embodiment, the multilayer substrate 10 is made of ceramic.
, but it goes without saying that it is not limited to this.
（発明の効果）
以上説明したように本発明の請求項（１）によれは、基
板に形成された貫通孔に複数のチップ状の電子部品が積
み重ねて挿入実装されるので、多層基板の少ない面積内
に複数のチップ状電子部品を高密度実装することができ
る。さらに、部品実装高さを低減できるので、電子回路
全体の形状を小型にすることができる。(Effects of the Invention) As explained above, according to claim (1) of the present invention, a plurality of chip-shaped electronic components are stacked and inserted into the through-hole formed in the board, so that the multilayer board can be used easily. A plurality of chip-shaped electronic components can be mounted with high density within an area. Furthermore, since the component mounting height can be reduced, the overall shape of the electronic circuit can be made smaller.
また、請求項（２）によれば、多層基板に部品配置孔を
容易に形成することができる。さらに、フィルムリード
によってチップ状の電子部品を前記多層基板の導体パタ
ーンに接続しているので、前記部品配置孔に複数のチッ
プ状電子部品を挿入して実装することができる。これに
より、前記多層基板の少ない面積内に複数のチップ状電
子部品を高密度実装することができると共に、部品実装
高さを低減できるので、電子回路全体の形状を小型にす
ることができるという非常に優れた効果を発揮するもの
である。Moreover, according to claim (2), component placement holes can be easily formed in the multilayer board. Furthermore, since the chip-shaped electronic components are connected to the conductor pattern of the multilayer board by the film lead, it is possible to insert and mount a plurality of chip-shaped electronic components into the component placement holes. This makes it possible to mount a plurality of chip-shaped electronic components at high density within a small area of the multilayer board, and also to reduce the component mounting height, making it possible to reduce the size of the entire electronic circuit. It exhibits excellent effects.
第１ａ図は本発明の一実施例の要部を示す側面断面図、
第１ｂ図は一実施例を示す分解斜視図、第２ａ図はＴＡ
Ｂ技術を説明する図、第２ｂ図はＴＡＢ技術による部品
実装例を示す図である。
１・・・フィルムキャリヤ、２・・・フィルムリード、
１０・・・多層基板、１１〜１５・・・第１乃至第５の
基板、ｌｌａ、１２ａ、１３ａ、１４ａ、１５ａ・・・
貫通孔、１６．１７・・・チップ状電子部品、１８・・
・部品配置孔、１９・・・スルーホール、２０・・・導
体パターン。
実施例を〒です分解１（祝図
第１ｂ図FIG. 1a is a side sectional view showing essential parts of an embodiment of the present invention;
Figure 1b is an exploded perspective view showing one embodiment, Figure 2a is a TA
FIG. 2b, which is a diagram explaining the B technique, is a diagram showing an example of component mounting using the TAB technique. 1... Film carrier, 2... Film lead,
10... Multilayer substrate, 11-15... First to fifth substrate, lla, 12a, 13a, 14a, 15a...
Through hole, 16.17... Chip-shaped electronic component, 18...
- Component placement hole, 19...Through hole, 20...Conductor pattern. The example is shown in Figure 1.
Claims (2)
積層してなる多層基板に、複数のチップ状の電子部品を
実装する多層基板の電子部品実装構造であって、 前記電子部品の実装位置に対応して所定形状の貫通孔を
有し、該貫通孔が対応するように隣接して積層された複
数枚の基板と、 前記貫通孔に挿入され、前記基板の積層方向に所定間隔
をあけて重置された複数のチップ状の電子部品と、 該複数の電子部品のそれぞれを所定の基板の導体パター
ンに接続する複数のフィルムリードとからなる、 ことを特徴とする多層基板の電子部品実装構造。(1) An electronic component mounting structure of a multilayer substrate in which a plurality of chip-shaped electronic components are mounted on a multilayer substrate formed by laminating a plurality of substrates on which predetermined conductor patterns are formed, wherein the electronic components are mounted. A plurality of substrates having through-holes of a predetermined shape corresponding to positions and stacked adjacently so that the through-holes correspond to each other; An electronic component on a multilayer board, comprising: a plurality of chip-shaped electronic components stacked one on top of the other; and a plurality of film leads that connect each of the plurality of electronic components to a conductor pattern on a predetermined board. Implementation structure.
積層してなる多層基板に複数のチップ状の電子部品を実
装する多層基板の電子部品実装方法であって、 前記複数枚の基板のそれぞれに、前記電子部品の実装位
置に対応して所定形状の貫通孔を形成すると共に、 前記各基板の所定位置にスルーホールを形成した後、 前記各基板のそれぞれに所定の導体パターンを形成する
と共に、 前記複数枚の基板を隣接させ、かつ前記各基板の貫通孔
を対応させ、該複数枚の基板を積層して前記複数の貫通
孔からなる部品配置孔を有する多層基板を形成した後、 フィルムリードにインナーリードボンディングされたチ
ップ状の電子部品を前記部品配置孔に挿入し、 該電子部品のフィルムリードを対応する基板の導体パタ
ーンにアウターリードボンディングし、この後、該電子
部品に所定間隔をあけて、同様にフィルムリードにイン
ナーリードボンディングされた他のチップ状の電子部品
を重置し、 該電子部品のフィルムリードを対応する基板の導体パタ
ーンにアウターリードボンディングする、ことを特徴と
する多層基板の電子部品実装方法。(2) A method for mounting electronic components on a multilayer board, in which a plurality of chip-shaped electronic components are mounted on a multilayer board formed by stacking a plurality of boards on which predetermined conductive patterns are formed, the method comprising: forming a through hole of a predetermined shape in each of them corresponding to the mounting position of the electronic component, and forming a through hole in a predetermined position of each of the substrates, and then forming a predetermined conductive pattern on each of the substrates. Also, after placing the plurality of substrates adjacent to each other and making the through holes of each substrate correspond to each other, and stacking the plurality of substrates to form a multilayer substrate having a component placement hole made of the plurality of through holes, A chip-shaped electronic component with inner lead bonding to a film lead is inserted into the component placement hole, the film lead of the electronic component is outer lead bonded to the corresponding conductor pattern of the board, and then the electronic component is attached at a predetermined interval. , and place another chip-shaped electronic component similarly inner lead bonded to the film lead, and outer lead bonding of the film lead of the electronic component to the corresponding conductor pattern of the board. A method for mounting electronic components on a multilayer board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2080437A JPH0734511B2 (en) | 1990-03-28 | 1990-03-28 | Electronic component mounting structure of multilayer board and mounting method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2080437A JPH0734511B2 (en) | 1990-03-28 | 1990-03-28 | Electronic component mounting structure of multilayer board and mounting method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03280496A true JPH03280496A (en) | 1991-12-11 |
| JPH0734511B2 JPH0734511B2 (en) | 1995-04-12 |
Family
ID=13718239
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2080437A Expired - Lifetime JPH0734511B2 (en) | 1990-03-28 | 1990-03-28 | Electronic component mounting structure of multilayer board and mounting method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0734511B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0730059A (en) * | 1993-06-24 | 1995-01-31 | Nec Corp | Multichip module |
| US5886874A (en) * | 1995-11-02 | 1999-03-23 | Mitsubishi Denki Kabushiki Kaisha | IC card |
| WO2006025084A1 (en) * | 2004-08-30 | 2006-03-09 | Spansion Llc | Carrier arrangement for stacked semiconductor device, process for producing same, and process for producing stacked semiconductor device |
| US9281302B2 (en) | 2014-02-20 | 2016-03-08 | International Business Machines Corporation | Implementing inverted master-slave 3D semiconductor stack |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021217326A1 (en) * | 2020-04-27 | 2021-11-04 | 宏启胜精密电子(秦皇岛)有限公司 | Embedded circuit board and method for manufacturing same |
-
1990
- 1990-03-28 JP JP2080437A patent/JPH0734511B2/en not_active Expired - Lifetime
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0730059A (en) * | 1993-06-24 | 1995-01-31 | Nec Corp | Multichip module |
| US5886874A (en) * | 1995-11-02 | 1999-03-23 | Mitsubishi Denki Kabushiki Kaisha | IC card |
| WO2006025084A1 (en) * | 2004-08-30 | 2006-03-09 | Spansion Llc | Carrier arrangement for stacked semiconductor device, process for producing same, and process for producing stacked semiconductor device |
| JPWO2006025084A1 (en) * | 2004-08-30 | 2008-07-31 | スパンション エルエルシー | Carrier structure for stacked semiconductor device, manufacturing method thereof, and manufacturing method of stacked semiconductor device |
| US7489029B2 (en) | 2004-08-30 | 2009-02-10 | Spansion Llc | Carrier structure for stacked-type semiconductor device, method of producing the same, and method of fabricating stacked-type semiconductor device |
| JP4613367B2 (en) * | 2004-08-30 | 2011-01-19 | スパンション エルエルシー | Carrier structure for stacked semiconductor device, manufacturing method thereof, and manufacturing method of stacked semiconductor device |
| US9142440B2 (en) | 2004-08-30 | 2015-09-22 | Cypess Semiconductor Corporation | Carrier structure for stacked-type semiconductor device, method of producing the same, and method of fabricating stacked-type semiconductor device |
| US9281302B2 (en) | 2014-02-20 | 2016-03-08 | International Business Machines Corporation | Implementing inverted master-slave 3D semiconductor stack |
| US10068886B2 (en) | 2014-02-20 | 2018-09-04 | International Business Machines Corporation | Implementing inverted master-slave 3D semiconductor stack |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0734511B2 (en) | 1995-04-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6760227B2 (en) | Multilayer ceramic electronic component and manufacturing method thereof | |
| JP2001308548A (en) | Multilayer printed circuit board, manufacturing method thereof and bga semiconductor package formed utilizing the same | |
| EP0272046A2 (en) | Circuit arrangement including a composite ceramic substrate | |
| JPH06120670A (en) | Multilayer wiring board | |
| US6676784B2 (en) | Process for the manufacture of multilayer ceramic substrates | |
| JP3886307B2 (en) | Flexible wiring board package and manufacturing method thereof | |
| JPH03280496A (en) | Electronic copmponent mounting structure and method of packaging | |
| JP2873645B2 (en) | Manufacturing method of ceramic multilayer wiring board | |
| JP2004056115A (en) | Multilayer wiring board | |
| JPH06275774A (en) | Connection device of circuit unit and circuit module using the connection device | |
| US7820490B2 (en) | Method for LTCC circuitry | |
| JPH03280495A (en) | Electronic component mounting structure and method of packaging | |
| JPH08191186A (en) | Multilayered wiring board | |
| JPH02164096A (en) | Multilayer electronic circuit board and its manufacture | |
| JPH04118987A (en) | Mounting method for chip component | |
| US5506754A (en) | Thermally matched electronic components | |
| JPH0714110B2 (en) | Multilayer ceramic substrate | |
| JPH06124850A (en) | Laminated composite electronic component | |
| JPH0230199B2 (en) | FUKUGOPURINTOHAISENBANNOSEIZOHOHO | |
| JPS614267A (en) | Three-dimensional mounting circuit module | |
| JPH0314292A (en) | Manufacture of high-density mounting module | |
| JPH05166672A (en) | Composite part | |
| JPH01191491A (en) | Multiple circuit board | |
| JPS6175596A (en) | Manufacture of through hole multilayer circuit board | |
| JPH03136396A (en) | Electronic circuit component, manufacture thereof and electronic circuit apparatus |