JP2873645B2 - Manufacturing method of ceramic multilayer wiring board - Google Patents
Manufacturing method of ceramic multilayer wiring boardInfo
- Publication number
- JP2873645B2 JP2873645B2 JP4156186A JP15618692A JP2873645B2 JP 2873645 B2 JP2873645 B2 JP 2873645B2 JP 4156186 A JP4156186 A JP 4156186A JP 15618692 A JP15618692 A JP 15618692A JP 2873645 B2 JP2873645 B2 JP 2873645B2
- Authority
- JP
- Japan
- Prior art keywords
- hole
- filled
- ceramic
- ceramic multilayer
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、通信機器等の電子回路
モジュールに用いられるセラミック多層配線基板の製造
方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of a ceramic multilayer wiring board used for an electronic circuit module of a communication device or the like.
It is about the method .
【０００２】[0002]
【従来の技術】従来のセラミック配線基板の外部回路へ
の接続構造は、配線導体にリードピンを接続したセラミ
ックフラットパッケージ形、またはリードピンを付けな
い面実装用のスルーホールめっきを施した孔部をセンタ
ー分割して側面の端子とする形とがある。図３は従来の
面実装形セラミック配線基板の平面図であり、１は端子
となっているスルーホールめっき孔部、２はスルーホー
ルめっきに連続したランド、３は回路パターン部（印刷
配線導体パターン）、４はセラミック基板である。図４
は従来技術によるスルーホールめっき孔の形成工程の断
面図であり、（Ａ）は孔加工したセラミック基板、
（Ｂ），（Ｄ）はスルーホールめっきの導体ペースト印
刷を行っているところを示す図であり、それぞれ表面か
らと、裏面からの印刷の状態を示す。（Ｃ），（Ｅ）は
スルーホールめっきの導体ペースト印刷後の状態を示す
図である。図において、５は導通ペースト、６は印刷用
スクリーン、７はスキージである。Connecting structure to the Prior Art external circuit of the conventional ceramic wiring substrate is a ceramic flat package type of connecting the lead pins to the wiring conductor, or hole portion subjected to scan Ruhoru plating for surface mounting that without the lead pin center There is a form that is divided into side terminals. FIG. 3 is a plan view of a conventional surface-mount type ceramic wiring board. 1 is a through-hole plating hole serving as a terminal, 2 is a land continuous with through-hole plating , and 3 is a circuit pattern portion (printed wiring conductor pattern). ), 4 is a ceramic substrate. FIG.
2A is a cross-sectional view of a process of forming a through-hole plating hole according to a conventional technique, and FIG.
(B), or (D) is a diagram showing the place where doing conductor paste mark <br/> printing of through-hole plating, respectively surface
And the state of printing from the back side. (C), (E) is a figure which shows the state after printing the conductor paste of through-hole plating . In the figure, 5 is a conductive paste, 6 is a printing screen, and 7 is a squeegee.
【０００３】[0003]
【発明が解決しようとする課題】しかし、このような従
来の製造方法による製品の構成では、次のような欠点が
ある。 （イ）リードピン接続形はピン接合部分が大きく、実装
面積が大きい。 （ロ）リードピン接続構造ではリフローはんだ付けがで
きない。 （ハ）スルーホールめっき分割端子形ではスルーホール
めっき部分の導通の信頼性が良くない。 （ニ）スルーホールめっき形は孔の周囲にランドが必要
なため小形化の障害になる。However, the structure of a product by such a conventional manufacturing method has the following disadvantages. (A) The lead pin connection type has a large pin joint and a large mounting area. (B) Reflow soldering is not possible with the lead pin connection structure. (C) through-hole nest Ruhoru plated split pin-shaped
The reliability of conduction of the plated part is not good. (D) Through-hole plating requires land around the hole, which is an obstacle to miniaturization.
【０００４】本発明の目的は、スルーホールめっき孔分
割形端子の導通信頼性が良くないという問題点を解消
し、さらに小形化できる外部回路接続用端子をもったセ
ラミック多層配線基板の製造方法を提供することにあ
る。[0004] It is an object of the present invention to provide a plated through hole.
Eliminates the problem of poor reliability of split terminals
And to provide a method of manufacturing a cell <br/> ceramic multilayer wiring board having an external circuit connection terminals that can be downsized.
【０００５】[0005]
【課題を解決するための手段】本発明のセラミック多層
配線基板の製造方法は、複数のセラミックグリーンシー
トのそれぞれに、内部導通用ビアホール孔と孔埋め分割
端子部用の孔をあけ、内層回路パターンの導体ペースト
を被着するとともに前記ビアホール孔と孔埋め分割端子
部用の孔に該導体ペーストを充填して乾燥した後、多層
に積層して焼成し、次に、上面と下面に印刷導体配線パ
ターンを印刷・焼成し、次に、導体が充填された前記孔
埋め分割端子部用の孔の中央部で切断することによって
周縁部に複数の外部回路接続用端子が配置されたセラミ
ック多層配線基板が得られることを特徴とするものであ
る。According to the present invention, there is provided a method of manufacturing a ceramic multilayer wiring board comprising a plurality of ceramic green sheets.
In each of the above, the via hole for internal conduction and the hole filling division
Drill holes for the terminals, and paste the conductor for the inner layer circuit pattern.
And the via-hole hole and the hole-filled split terminal.
After filling and drying the conductive paste in the holes for
And fired, then print printed wiring on top and bottom
The turn is printed and fired, then the hole filled with conductor
By cutting at the center of the hole for the buried split terminal part
A ceramic with a plurality of external circuit connection terminals on the periphery
A multi-layer wiring board is obtained .
【０００６】[0006]
【実施例】図１は本発明の方法によって作った製品の斜
視図（Ａ）と平面図（Ｂ）である。図において、１２は
セラミック多層基板、３は回路パターン部（印刷配線導
体パターン）、１１は孔埋め分割端子部である。1 is a perspective view (A) and a plan view (B) of a product made by the method of the present invention. In the figure, 12 is a ceramic multilayer substrate, 3 is a circuit pattern portion (printed wiring conductor pattern), and 11 is a hole-filled divided terminal portion.
【０００７】図２は、本発明の実施例を示す説明図であ
り、孔埋め分割端子部の形成工程を示す断面図であり、
（Ａ）は孔加工したグリーンシート１５を示す図、
（Ｂ）は孔１４に印刷により導体ペースト１５を充填
（孔埋め）している図、（Ｃ）はそれらを積層した図、
（Ｄ）は焼成により一体化して一枚のセラミック多層基
板にしたものを示し、この後孔埋め部分を分割して図１
のように完成する。図において、１１は孔埋め分割端子
部、１２はセラミック多層基板、１３はセラミックグリ
ーンシート（焼成前のシート）、１４は孔埋め分割端子
部とするための孔、１５は導体ペースト、１６は印刷用
スクリーン、１７はスキージ、１８は導体ペースト充填
用平板、１９は内層パターンである。FIG. 2 is an explanatory view showing an embodiment of the present invention .
FIG. 3 is a cross-sectional view illustrating a step of forming a hole-filled divided terminal portion
(A) is a diagram showing a green sheet 15 in which holes have been drilled.
(B) is a diagram in which the conductive paste 15 is filled (filled) by printing in the holes 14 , (C) is a diagram in which they are laminated,
FIG. 1D shows a single ceramic multi-layer substrate integrated by firing , and then the hole-filled portion is divided into FIG.
It is completed as of. In the figure, reference numeral 11 denotes a filled terminal.
Parts, 12 ceramic multilayer substrate, a ceramic green sheet (before sintering sheet) 13, 14 holes filled split pin
Hole for the parts, 15 conductive paste, the printing screen 16, 17 squeegee 18 conductive paste filling plates 19 is the inner layer patterns.
【０００８】次に図２に従って本発明の実施例の製造工
程を説明する。 （Ａ） セラミックグリーンシート１３に、内部導通用
ビアホール（ＶＩＡ ＨＯＬＥ）孔と孔埋め分割端子部
用の孔１４をあける。ビアホールはセラミックグリーン
シート１３の一部の層間の内部導通のための小孔であり
図示は省略した。また、孔埋め分割端子部用の孔１４は
積層後の最上層と最下層とを導通させセンタ分割して側
面の端子部とする孔である。例えば、ビアホール孔径：
φ０．１〜０．３mm（グリーンシートの厚み等で変わ
る）、スルーホール孔径：φ０．５〜０．８mmである。 （Ｂ） ビアホール孔と同時に孔埋め分割端子部用の孔
１４にも導体ペーストを充填した後ペーストを乾燥させ
る。この充填から乾燥までは、導体ペーストが孔から落
下するのを防止するために、平滑な板１８（セラミッ
ク，ガラス等）を台としてグリーンシート１３の下に敷
く。 （Ｃ） 各層の内層回路パターンの印刷を行い、導体ペ
ーストを乾燥させ、積層する。 （Ｄ） ８５０℃〜９００℃で一定焼成した後、表面回
路パターン（表裏）を印刷・焼成する。この場合、表面
及び裏面の回路パターン印刷は、端子部用の孔１ ４が既
に、導体ペーストが焼成されて孔埋めされているので、
孔を気にせず平滑な基板として容易に行うことができ
る。 （Ｅ） ダイヤモンドカッター等によるダイシングによ
り、面付けされたモジュールを個々に切断する（図１参
照）。この場合、モジュール毎の分割は、電極端子部と
する孔１４の充填導体を半分に切る必要があるので、従
来のスクライブラインによる折り曲げ分割はできない。Next, the manufacturing process of the embodiment of the present invention will be described with reference to FIG. (A) In the ceramic green sheet 13, a via hole (VIA HOLE) for internal conduction and a hole-filled divided terminal portion are provided.
Holes 14 for use . The via holes are small holes for internal conduction between some layers of the ceramic green sheet 13 and are not shown. In addition, the hole 14 for the hole-filling division terminal portion is connected to the uppermost layer and the lowermost layer after lamination to divide the center and divide the side.
It is a hole to be a terminal part of the surface . For example, via hole diameter:
φ0.1 to 0.3 mm (varies depending on the thickness of the green sheet, etc.), and through-hole hole diameter: φ0.5 to 0.8 mm. (B) Holes for split-filled terminal portions at the same time as via holes
14 is filled with the conductive paste, and then the paste is dried. From the filling to the drying, in order to prevent the conductive paste from dropping from the holes , a flat plate 18 (ceramic, glass, etc.) is laid under the green sheet 13 as a base. (C) The inner layer circuit pattern of each layer is printed, and the conductor paste is dried and laminated. (D) After constant firing at 850 ° C. to 900 ° C., the surface circuit pattern (front and back) is printed and fired. In this case, the circuit pattern printing surface <br/> and back surfaces, holes 1 4 already in the terminal portion
Since the conductor paste is fired and filled with holes ,
It can be easily performed as a smooth substrate without concern for the holes. (E) The imposed modules are individually cut by dicing with a diamond cutter or the like (see FIG. 1). In this case, the division for each module is
Since it is necessary to cut the filled conductor of the hole 14 to be cut in half, the conventional scribe line cannot be bent and divided.
【０００９】[0009]
【発明の効果】本発明を実施することにより、次のよう
な利点がある。 （イ） 端子部１１は孔埋め（充填）焼成されるので、
断線の恐れがない。 （ロ） 孔埋めのため、この外部電極端子が基板面に対
し平滑になるので本発明により作成したモジュールを主
基板への実装（はんだ付け）が容易になる。 （ハ） 孔埋め分割端子部の周囲にはランドがないため
小形化できる。 （ニ） 製造の最初の段階で孔埋めしてしまうので、そ
の後の内層回路パターン及び表面パターンの導体印刷が
容易になる。The present invention has the following advantages. (A) Since the terminal portion 11 is filled (filled) and fired ,
There is no risk of disconnection. (B) Since the external electrode terminals become smooth with respect to the substrate surface due to the filling of the holes, the module prepared according to the present invention can be easily mounted (soldered) on the main substrate. (C) around the hole filling dividing terminal portion can miniaturization because the land is not. (D) Since the holes are filled in the initial stage of the manufacturing, conductor printing of the inner layer circuit pattern and the surface pattern thereafter becomes easy.
【図１】本発明の方法によって作られた製品の斜視図と
平面図である。FIG. 1 is a perspective view and a plan view of a product made by the method of the present invention.
【図２】本発明の実施例を示す製作工程の説明図であ
る。FIG. 2 is an explanatory diagram of a manufacturing process showing an example of the present invention.
【図３】従来のセラミック配線基板の平面図である。FIG. 3 is a plan view of a conventional ceramic wiring board.
【図４】従来の製作工程の説明図である。FIG. 4 is an explanatory view of a conventional manufacturing process.
１ スルーホールめっき孔部 ２ スルーホールめっきに連続したランド ３ 回路パターン部 ４ セラミック基板 ５ 導体ペースト ６ 印刷用スクリーン ７ スキージ １１ 孔埋め分割端子部 １２ セラミック多層基板 １３ セラミックグリーンシート １４ 孔埋め用分割端子部用の孔 １５ 導体ペースト １６ 印刷用スクリーン １７ スキージ １８ 導体ペースト充填用平板 １９ 内層パターンDESCRIPTION OF SYMBOLS 1 Through-hole plating hole part 2 Land connected to through-hole plating 3 Circuit pattern part 4 Ceramic substrate 5 Conductor paste 6 Printing screen 7 Squeegee 11 Filled division terminal part 12 Ceramic multilayer board 13 Ceramic green sheet 14 Divided terminal for hole filling Holes for parts 15 Conductive paste 16 Printing screen 17 Squeegee 18 Flat plate for filling conductive paste 19 Inner layer pattern
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭63−268293（ＪＰ，Ａ) 特開 昭48−98362（ＪＰ，Ａ) 特開 昭57−52187（ＪＰ，Ａ) 特開 昭63−204693（ＪＰ，Ａ) 実開 平１−157468（ＪＰ，Ｕ) 実開 昭61−81131（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.6，ＤＢ名) H05K 3/46 H05K 1/11 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-268293 (JP, A) JP-A-48-98362 (JP, A) JP-A-57-52187 (JP, A) JP-A 63-268187 204693 (JP, A) JP-A 1-157468 (JP, U) JP-A 61-81131 (JP, U) (58) Fields investigated (Int. Cl. 6 , DB name) H05K 3/46 H05K 1 / 11
Claims (1)
ぞれに、内部導通用ビアホール孔と孔埋め分割端子部用
の孔をあけ、内層回路パターンの導体ペーストを被着す
るとともに前記ビアホール孔と孔埋め分割端子部用の孔
に該導体ペーストを充填して乾燥した後、多層に積層し
て焼成し、次に、上面と下面に印刷導体配線パターンを
印刷・焼成し、次に、導体が充填された前記孔埋め分割
端子部用の孔の中央部で切断することによって周縁部に
複数の外部回路接続用端子が配置されたセラミック多層
配線基板が得られることを特徴とするセラミック多層配
線基板の製造方法。 1. A plurality of ceramic green sheets
For the internal conduction via hole and the hole-filled split terminal part, respectively.
And apply the conductive paste for the inner layer circuit pattern.
And the via hole hole and the hole for the filled terminal portion.
After filling and drying the conductive paste, laminated in multiple layers
Firing, and then apply printed conductor wiring patterns on the upper and lower surfaces.
Printing and firing, then the hole filling division filled with conductor
By cutting at the center of the terminal hole,
Ceramic multilayer with multiple external circuit connection terminals
Ceramic multilayer arrangement characterized by obtaining a wiring board
Manufacturing method of wire substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4156186A JP2873645B2 (en) | 1992-05-25 | 1992-05-25 | Manufacturing method of ceramic multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4156186A JP2873645B2 (en) | 1992-05-25 | 1992-05-25 | Manufacturing method of ceramic multilayer wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05327222A JPH05327222A (en) | 1993-12-10 |
| JP2873645B2 true JP2873645B2 (en) | 1999-03-24 |
Family
ID=15622251
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4156186A Expired - Lifetime JP2873645B2 (en) | 1992-05-25 | 1992-05-25 | Manufacturing method of ceramic multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2873645B2 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0738217A (en) * | 1993-07-22 | 1995-02-07 | Nec Corp | Ceramic board |
| KR20020065261A (en) * | 2001-02-06 | 2002-08-13 | 전자부품연구원 | ceramic piled components and method of manufacturing thereof |
| JP2003008239A (en) * | 2001-06-21 | 2003-01-10 | Ibiden Co Ltd | Multilayer printed wiring board |
| KR20040023407A (en) * | 2002-09-11 | 2004-03-18 | 현대모비스 주식회사 | Broken Type PCB |
| KR100489820B1 (en) | 2002-11-19 | 2005-05-16 | 삼성전기주식회사 | Ceramic Multilayer Substrate and its Manufacturing Process |
| KR100495211B1 (en) * | 2002-11-25 | 2005-06-14 | 삼성전기주식회사 | Ceramic multilayer board and its manufacture |
| JP5952039B2 (en) * | 2012-03-15 | 2016-07-13 | 住友精密工業株式会社 | Discharge cell and ozone gas generator |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4898362A (en) * | 1972-03-29 | 1973-12-13 | ||
| JPS6181131U (en) * | 1984-11-02 | 1986-05-29 | ||
| JPS63268293A (en) * | 1987-04-27 | 1988-11-04 | Matsushita Electric Ind Co Ltd | Manufacture of thick film circuit substrate |
| JPH0346518Y2 (en) * | 1988-11-24 | 1991-10-01 |
-
1992
- 1992-05-25 JP JP4156186A patent/JP2873645B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05327222A (en) | 1993-12-10 |
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