JPH10289837A - Laminated electronic parts - Google Patents

Laminated electronic parts

Info

Publication number
JPH10289837A
JPH10289837A JP9097666A JP9766697A JPH10289837A JP H10289837 A JPH10289837 A JP H10289837A JP 9097666 A JP9097666 A JP 9097666A JP 9766697 A JP9766697 A JP 9766697A JP H10289837 A JPH10289837 A JP H10289837A
Authority
JP
Japan
Prior art keywords
substrate
external electrodes
chip capacitor
electrodes
electronic component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9097666A
Other languages
Japanese (ja)
Inventor
Harufumi Bandai
Norio Sakai
治文 萬代
範夫 酒井
Original Assignee
Murata Mfg Co Ltd
株式会社村田製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Mfg Co Ltd, 株式会社村田製作所 filed Critical Murata Mfg Co Ltd
Priority to JP9097666A priority Critical patent/JPH10289837A/en
Publication of JPH10289837A publication Critical patent/JPH10289837A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide laminated electronic parts allowed to be miniaturized and narrowed at their packaging intervals at the time of packaging them on a printed board. SOLUTION: A chip capacitor 10 to be laminated electronic parts has a substrate 11 formed by laminating plural sheet layers 11a to 11e consisting of ceramics and external electrodes 13a, 13b connected to inner electrodes 12a to 12d, formed on the sheet layers 11b to 11e and exposed only to one end face 111 of the substrate 11 by vertically dividing a via hole electrode obtained by filling a through hole with conductive past. In the case of packaging the chip capacitor 10 on a printed board, the end face 111 forming the external electrodes 13a, 13b becomes a packaging face.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【0001】[0001]
【発明の属する技術分野】本発明は、積層電子部品に関
し、特に基板の1つの端面にのみ複数の外部電極を備
え、その端面を、実装基板に実装する際の実装面とする
積層電子部品に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated electronic component, and more particularly to a laminated electronic component provided with a plurality of external electrodes only on one end face of a substrate and having the end face as a mounting surface when mounted on a mounting board. .
【0002】[0002]
【従来の技術】チップ抵抗やチップコンデンサに代表さ
れる積層電子部品は、電子機器の小型化や高性能化に不
可欠であり、その高密度化・高性能化が一層求められて
いる。この要求にともない、最近では、図5に示すよう
な、セラミックからなる複数のシート層(51a〜51
e)を積層して形成される基板51を有し、シート層5
1b〜51e上に形成された内部電極52a〜52dを
ビアホール電極53a、53bにより基板51の裏面に
引き出し、ビアホール電極53a、53bの引き出され
た部分に外部電極54a、54bを接続させるチップコ
ンデンサ50が提案されている。この際、図示していな
いが、チップコンデンサ50の裏面が実装面となり、外
部電極54a、54bとプリント基板上の配線パターン
とをはんだ等で接続することにより、チップコンデンサ
50がプリント基板上に実装されることとなる。
2. Description of the Related Art Multilayer electronic components typified by chip resistors and chip capacitors are indispensable for miniaturization and high performance of electronic devices, and higher densities and higher performance are increasingly required. In response to this demand, recently, a plurality of ceramic sheet layers (51a to 51a) as shown in FIG.
e) having a substrate 51 formed by laminating
A chip capacitor 50 connects internal electrodes 52a to 52d formed on 1b to 51e to the rear surface of the substrate 51 by via-hole electrodes 53a and 53b, and connects external electrodes 54a and 54b to the extracted portions of the via-hole electrodes 53a and 53b. Proposed. At this time, although not shown, the back surface of the chip capacitor 50 becomes a mounting surface, and the external electrodes 54a and 54b are connected to the wiring patterns on the printed board by soldering or the like, so that the chip capacitor 50 is mounted on the printed board. Will be done.
【0003】しかしながら、図5のチップコンデンサ5
0の構造では、基板51の端面とビアホール電極53a
との間隔をL1、ビアホール電極53aの直径をL2と
すると、シート層51a〜51dに形成された内部電極
52a〜52dをビアホール電極53a、53bにより
裏面に引き出すため、外部電極を基板の側面にスクリー
ン印刷等により直接設ける場合と比べ、基板51の端面
とビアホール電極53aとの間隔L1、ビアホール電極
53aの半径L2/2が必要となり、基板51の横方向
が(L1+L2/2)×2分大きくなるという問題があ
った。例えば、L1を約0.1mm、L2を約0.1m
mとすると、基板51の横方向を約0.3mm大きくす
る必要がある。
However, the chip capacitor 5 shown in FIG.
0, the end face of the substrate 51 and the via hole electrode 53a
Assuming that the distance between the external electrodes is L1 and the diameter of the via hole electrode 53a is L2, the internal electrodes 52a to 52d formed on the sheet layers 51a to 51d are drawn out to the back surface by the via hole electrodes 53a and 53b. Compared with the case where the substrate 51 is directly provided by printing or the like, the distance L1 between the end face of the substrate 51 and the via hole electrode 53a and the radius L2 / 2 of the via hole electrode 53a are required, and the lateral direction of the substrate 51 is increased by (L1 + L2 / 2) × 2. There was a problem. For example, L1 is about 0.1 mm, L2 is about 0.1 m
Assuming that m, the lateral direction of the substrate 51 needs to be increased by about 0.3 mm.
【0004】この問題点を解決するために、図6に示す
ように、特開平7−297080号で開示されているよ
うなチップコンデンサが提案されている。図6におい
て、チップコンデンサ60は、セラミックからなる複数
のシート層(61a〜61e)を積層して形成される基
板61と、シート層61b〜61eに形成された内部電
極62a〜62dに接続されるとともに、導体ペースト
からなる導電体をスルーホール内に充填して、そのスル
ーホール内の導電体を基板61の相対する2つの端面に
露出された外部電極63a、63bとを有する。そし
て、チップコンデンサ60の外部電極63a、63bと
プリント基板64上の配線パターン65とをはんだ66
で接続することにより、チップコンデンサ60がプリン
ト基板64上に実装されることとなる。
To solve this problem, as shown in FIG. 6, a chip capacitor as disclosed in Japanese Patent Application Laid-Open No. 7-297080 has been proposed. In FIG. 6, a chip capacitor 60 is connected to a substrate 61 formed by laminating a plurality of ceramic sheet layers (61a to 61e) and internal electrodes 62a to 62d formed on the sheet layers 61b to 61e. In addition, a conductor made of a conductive paste is filled in the through-hole, and the conductor in the through-hole has external electrodes 63a and 63b exposed at two opposite end surfaces of the substrate 61. Then, the external electrodes 63a and 63b of the chip capacitor 60 and the wiring pattern 65 on the printed circuit board 64 are soldered to each other.
Thus, the chip capacitor 60 is mounted on the printed circuit board 64.
【0005】このチップコンデンサ60の場合には、外
部電極63a、63bが、スルーホール内の導電体を基
板61の相対する2つの端面に露出させることにより形
成されているため、図5のチップコンデンサ50と比
べ、基板51の端面とビアホール電極53aとの間隔L
1、ビアホール電極53aの半径L2/2が不必要とな
り、その結果、図5のチップコンデンサ50と比べ、
(L1+L2/2)×2の分、基板61の横方向が小さ
くなる。
In the case of the chip capacitor 60, since the external electrodes 63a and 63b are formed by exposing the conductors in the through holes to two opposing end surfaces of the substrate 61, the chip capacitor 60 shown in FIG. 50, the distance L between the end face of the substrate 51 and the via-hole electrode 53a
1. The radius L2 / 2 of the via hole electrode 53a becomes unnecessary, and as a result, compared with the chip capacitor 50 of FIG.
The lateral direction of the substrate 61 is reduced by (L1 + L2 / 2) × 2.
【0006】[0006]
【発明が解決しようとする課題】ところが、上記の従来
のチップコンデンサに代表される積層電子部品において
は、はんだを用いて、積層電子部品をプリント基板上に
実装する際に、積層電子部品の外部電極とプリント基板
上の配線パターンとの間に、はんだフィレットが必要と
なる。したがって、回路パターンを基板の端面からはん
だフィレットの分(図6中のL3)だけ大きくする必要
があるため、それぞれの積層電子部品の実装間隔を狭め
ることが困難で、その結果、プリント基板が大きくなる
という問題があった。
However, in a multilayer electronic component typified by the above-mentioned conventional chip capacitor, when the multilayer electronic component is mounted on a printed circuit board using solder, an external component of the multilayer electronic component is not provided. A solder fillet is required between the electrode and the wiring pattern on the printed circuit board. Therefore, it is necessary to increase the circuit pattern from the end face of the board by the solder fillet (L3 in FIG. 6), and it is difficult to reduce the mounting interval between the respective laminated electronic components. There was a problem of becoming.
【0007】本発明は、このような問題点を解決するた
めになされたものであり、小型化が可能であり、かつプ
リント基板に実装する際にその実装間隔を狭めることが
できる積層電子部品を提供することを目的とする。
SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and it is an object of the present invention to provide a multilayer electronic component which can be reduced in size and can reduce the mounting interval when mounted on a printed circuit board. The purpose is to provide.
【0008】[0008]
【課題を解決するための手段】上述する問題点を解決す
るため本発明の積層電子部品は、誘電材料及び磁性材料
の少なくとも一方からなる複数のシート層を積層してな
る基板と、該基板の内部に形成される複数の内部電極
と、該内部電極に接続されるとともに、前記基板の1つ
の端面にのみ形成される複数の外部電極とを備え、前記
外部電極を備える前記基板の端面が、実装基板に実装す
る際の実装面となることを特徴とする。
In order to solve the above-mentioned problems, a laminated electronic component according to the present invention comprises: a substrate having a plurality of sheet layers made of at least one of a dielectric material and a magnetic material; A plurality of internal electrodes formed therein, and a plurality of external electrodes connected to the internal electrodes and formed only on one end surface of the substrate, the end surface of the substrate including the external electrodes, It is characterized by being a mounting surface when mounting on a mounting board.
【0009】本発明の電子回路部品によれば、基板の1
つの端面にのみ複数の外部電極を設け、その端面を実装
面とするため、積層電子部品の外部電極とプリント基板
上の配線パターンとの間のはんだフィレットをなくする
ことができる。
According to the electronic circuit component of the present invention, one of the substrates
Since a plurality of external electrodes are provided only on one end face and the end face is used as a mounting surface, a solder fillet between the external electrodes of the multilayer electronic component and the wiring pattern on the printed board can be eliminated.
【0010】[0010]
【発明の実施の形態】以下、図面を参照して本発明の実
施例を説明する。図1に、本発明の積層電子部品の一実
施例の分解斜視図を示す。積層電子部品であるチップコ
ンデンサ10は、セラミックからなる複数のシート層
(11a〜11f)を積層して形成される基板11と、
シート層11b〜11e上に形成された内部電極12a
〜12dに接続されるとともに、基板11の1つの端面
111にのみ形成された外部電極13a、13bとを有
する。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an exploded perspective view of one embodiment of the laminated electronic component of the present invention. A chip capacitor 10 that is a multilayer electronic component includes a substrate 11 formed by stacking a plurality of sheet layers (11a to 11f) made of ceramic;
Internal electrode 12a formed on sheet layers 11b to 11e
12d and external electrodes 13a and 13b formed only on one end face 111 of the substrate 11.
【0011】そして、図2に示すように、チップコンデ
ンサ10の外部電極13a、13bが形成された端面1
11を実装面として、外部電極13a、13bと実装基
板であるプリント基板1上の配線パターン2とをはんだ
3で接続することにより、チップコンデンサ10がプリ
ント基板1上に実装されることとなる。
Then, as shown in FIG. 2, the end face 1 of the chip capacitor 10 on which the external electrodes 13a and 13b are formed.
The chip capacitor 10 is mounted on the printed circuit board 1 by connecting the external electrodes 13 a and 13 b to the wiring pattern 2 on the printed circuit board 1 as the mounting board with solder 3 using the mounting surface 11 as a mounting surface.
【0012】次に、チップコンデンサ10の製造方法に
ついて説明する。まず、セラミックからなる複数のマザ
ーシート層を用意する。次いで、それらのマザーシート
層にパンチング加工することによりスルーホールを形成
し、導体ペーストをスクリーン印刷することにより内部
電極12a〜12dとなる導電層を形成する。なお、こ
の導体ペーストを印刷する際、スルーホール内に導体ペ
ーストからなる導電体が充填され、各マザーシート層上
の導電層がスルーホール内の導電体を介して接続される
こととなる。
Next, a method of manufacturing the chip capacitor 10 will be described. First, a plurality of mother sheet layers made of ceramic are prepared. Next, through holes are formed in the mother sheet layers by punching, and conductive layers to be the internal electrodes 12a to 12d are formed by screen-printing a conductive paste. When this conductor paste is printed, the conductors made of the conductor paste are filled in the through holes, and the conductor layers on the respective mother sheet layers are connected via the conductors in the through holes.
【0013】次いで、それらの複数のマザーシート層を
積層してマザー基板を形成した後、基板11の1つの端
面111にのみ、スルーホール内の導電体が露出される
ように各ブロックに切断する。次いで、基板11、内部
電極12a〜12dとなるシート層上の導電層及び外部
電極13a、13bとなるスルーホール内の導電体を一
体焼成する。これにより、実装面となる基板11の端面
111にのみ形成される外部電極13a、13bを備え
るチップコンデンサ10が完成する。
Next, after laminating the plurality of mother sheet layers to form a mother substrate, the mother substrate is cut into blocks so that the conductor in the through hole is exposed only on one end face 111 of the substrate 11. . Next, the substrate 11, the conductive layers on the sheet layers to be the internal electrodes 12a to 12d, and the conductors in the through holes to be the external electrodes 13a and 13b are integrally fired. Thus, the chip capacitor 10 including the external electrodes 13a and 13b formed only on the end face 111 of the substrate 11 serving as a mounting surface is completed.
【0014】上述の実施例の積層電子部品であるチップ
コンデンサによれば、基板の1つの端面にのみ複数の外
部電極を設けているため、図6の従来のチップコンデン
サ60と比べ、実装面となる端面に相対する端面におい
て、ビアホール電極の半径L2/2が不必要となる。
According to the chip capacitor which is a multilayer electronic component of the above-described embodiment, since a plurality of external electrodes are provided only on one end surface of the substrate, the mounting surface is smaller than that of the conventional chip capacitor 60 shown in FIG. In the end face opposite to the end face, the radius L2 / 2 of the via hole electrode is unnecessary.
【0015】その結果、従来のチップコンデンサ60
(図6)と比べ、L2/2の分、横方向を小さくするこ
とができる。逆に、同じ大きさの場合には、内部電極を
大きくすることができるため、その分、チップコンデン
サの容量値を大きくすることができる。
As a result, the conventional chip capacitor 60
Compared to (FIG. 6), the horizontal direction can be reduced by L2 / 2. Conversely, in the case of the same size, the internal electrodes can be made large, and accordingly, the capacitance value of the chip capacitor can be made large.
【0016】また、外部電極が設けられる端面を実装面
とするため、チップコンデンサの外部電極とプリント基
板上の配線パターンとの間のはんだフィレットをなくす
ることができる。したがって、配線パターンをチップコ
ンデンサの端面よりも大きくする必要がなく、複数のチ
ップコンデンサをプリント基板に実装する際に、その実
装間隔を狭めることができ、チップコンデンサの実装密
度が向上する。その結果、プリント基板の小型化が可能
となる。
Further, since the end surface on which the external electrodes are provided is used as the mounting surface, a solder fillet between the external electrodes of the chip capacitor and the wiring pattern on the printed circuit board can be eliminated. Therefore, it is not necessary to make the wiring pattern larger than the end surface of the chip capacitor, and when mounting a plurality of chip capacitors on a printed circuit board, the mounting interval can be reduced, and the mounting density of the chip capacitors is improved. As a result, the size of the printed circuit board can be reduced.
【0017】なお、上述の実施例では、積層電子部品が
チップコンデンサの場合について説明したが、図3に示
すように、セラミックからなる複数のシート層(21a
〜21j)を積層して形成される基板21に、複数の内
部電極22a〜22hで形成される複数のコンデンサC
1〜C4が内蔵されたコンデンサアレイ部品への応用も
可能である。この際、コンデンサC1は内部電極22
a、22bで、コンデンサC2は内部電極22c、22
dで、コンデンサC3は内部電極22e、22fで、コ
ンデンサC4は内部電極22g、22hで、それぞれ形
成される。
In the above-described embodiment, the case where the multilayer electronic component is a chip capacitor is described. However, as shown in FIG. 3, a plurality of ceramic sheet layers (21a) are formed.
To 21j), a plurality of capacitors C formed by a plurality of internal electrodes 22a to 22h are formed on a substrate 21 formed by stacking
Application to a capacitor array component in which 1 to C4 are built is also possible. At this time, the capacitor C1 is connected to the internal electrode 22.
a, 22b, the capacitor C2 is connected to the internal electrodes 22c, 22c.
At d, the capacitor C3 is formed by the internal electrodes 22e and 22f, and the capacitor C4 is formed by the internal electrodes 22g and 22h.
【0018】この場合には、基板21の内部でそれぞれ
のコンデンサC1〜C4を接続するビアホール電極が必
要ないため、コンデンサアレイ部品20の小型化が可能
となる。したがって、プリント基板(図示せず)のより
小型化が可能となる。
In this case, since there is no need for via-hole electrodes for connecting the respective capacitors C1 to C4 inside the substrate 21, the size of the capacitor array component 20 can be reduced. Therefore, the size of the printed circuit board (not shown) can be further reduced.
【0019】また、図4に示すチップコンデンサ30の
ように、基板31を構成する複数のシート層31a〜3
1hのうち、内部電極32a〜32dが形成されていな
いシート層31bにも、外部電極33a、33bを設
け、チップコンデンサ30の外部電極33a、33bを
大きくしてもよい。この場合には、積層電子部品30の
外部電極33a、33bが大きくなるため、外部電極3
3a、33bとプリント基板上の回路パターン(図示せ
ず)との接着強度が向上する。
Further, as shown in FIG. 4, a plurality of sheet layers 31a to 31
In 1h, the external electrodes 33a and 33b may be provided also on the sheet layer 31b where the internal electrodes 32a to 32d are not formed, and the external electrodes 33a and 33b of the chip capacitor 30 may be enlarged. In this case, since the external electrodes 33a and 33b of the multilayer electronic component 30 become large, the external electrodes 3
The bonding strength between 3a, 33b and a circuit pattern (not shown) on the printed board is improved.
【0020】また、図示していないが、積層電子部品
が、チップ抵抗、チップインダクタ、抵抗アレイ部品、
インダクタアレイ部品及びそれらの複合部品である場合
も応用が可能である。
Although not shown, the multilayer electronic component includes a chip resistor, a chip inductor, a resistor array component,
The present invention can be applied to inductor array components and composite components thereof.
【0021】さらに、スルーホール内に導体ペーストか
らなる導電体を充填して、そのスルーホール内の導電体
を基板の端面にのみ露出させ、外部電極を形成する場合
について説明したが、スルーホールの壁面に導体ペース
トからなる導電層を塗布して、そのスルーホール壁面の
導電層を基板の1つの端面にのみ露出させ、外部電極を
形成してもよい。
Further, a case has been described in which a conductor made of a conductive paste is filled in the through-hole, and the conductor in the through-hole is exposed only at the end face of the substrate to form an external electrode. An external electrode may be formed by applying a conductive layer made of a conductive paste on the wall surface and exposing the conductive layer on the through-hole wall surface to only one end surface of the substrate.
【0022】また、積層電子部品の製造方法として、マ
ザー基板を各ブロックに切断した後、基板、内部電極と
なるシート層上の導電層、及び外部電極となるスルーホ
ール内の導電体を一体焼成する場合について説明した
が、マザー基板、内部電極となるシート層上の導電層及
び外部電極となるスルーホール内の導電体を一体焼成し
た後、マザー基板を各ブロックに切断しても同様の効果
が得られる。
As a method of manufacturing a laminated electronic component, a mother substrate is cut into blocks, and then the substrate, a conductive layer on a sheet layer serving as an internal electrode, and a conductor in a through hole serving as an external electrode are integrally fired. However, the same effect can be obtained even if the mother substrate, the conductive layer on the sheet layer serving as the internal electrode, and the conductor in the through hole serving as the external electrode are integrally fired, and then the mother substrate is cut into blocks. Is obtained.
【0023】[0023]
【発明の効果】本発明の積層電子部品によれば、基板の
1つの端面にのみ複数の外部電極を設けているため、従
来の積層電子部品と比べ、横方向を小さくすることがで
きる。
According to the multilayer electronic component of the present invention, since a plurality of external electrodes are provided only on one end face of the substrate, the lateral direction can be reduced as compared with the conventional multilayer electronic component.
【0024】また、外部電極が設けられる端面を実装面
とするため、積層電子部品の外部電極とプリント基板上
の配線パターンとの間のはんだフィレットをなくするこ
とができる。したがって、配線パターンを積層電子部品
の端部よりも大きくする必要がなく、複数の積層電子部
品をプリント基板に実装する際に、その実装間隔を狭め
ることができ、積層電子部品の実装密度が向上する。そ
の結果、プリント基板の小型化が可能となる。
Further, since the end surface on which the external electrodes are provided is a mounting surface, a solder fillet between the external electrodes of the laminated electronic component and the wiring pattern on the printed board can be eliminated. Therefore, it is not necessary to make the wiring pattern larger than the end of the multilayer electronic component, and when mounting a plurality of multilayer electronic components on a printed circuit board, the mounting interval can be narrowed, and the mounting density of the multilayer electronic component is improved. I do. As a result, the size of the printed circuit board can be reduced.
【図面の簡単な説明】[Brief description of the drawings]
【図1】本発明の積層電子部品に係る一実施例の分解斜
視図である。
FIG. 1 is an exploded perspective view of an embodiment according to a multilayer electronic component of the present invention.
【図2】図1の積層電子部品をプリント基板に実装した
場合の断面図である。
FIG. 2 is a cross-sectional view when the multilayer electronic component of FIG. 1 is mounted on a printed circuit board.
【図3】本発明の積層電子部品に係る別の実施例の分解
斜視図である。
FIG. 3 is an exploded perspective view of another embodiment of the multilayer electronic component of the present invention.
【図4】本発明の積層電子部品に係るさらに別の実施例
の分解斜視図である。
FIG. 4 is an exploded perspective view of still another embodiment according to the multilayer electronic component of the present invention.
【図5】従来の積層電子部品を示す断面図である。FIG. 5 is a sectional view showing a conventional laminated electronic component.
【図6】従来の別の積層電子部品を示す断面図である。FIG. 6 is a sectional view showing another conventional laminated electronic component.
【符号の説明】[Explanation of symbols]
10、20、30 積層電子部品 11、21、31 基板 11a〜11f、21a〜21j、31a〜31h
シート層 111 端面(実装面) 12a〜12d、22a〜22h、32a〜32d
内部電極 13a、13b、23a〜23h、33a、33b
外部電極
10, 20, 30 Multilayer electronic components 11, 21, 31 Substrates 11a to 11f, 21a to 21j, 31a to 31h
Sheet layer 111 End surface (mounting surface) 12a to 12d, 22a to 22h, 32a to 32d
Internal electrodes 13a, 13b, 23a to 23h, 33a, 33b
External electrode

Claims (1)

    【特許請求の範囲】[Claims]
  1. 【請求項1】 誘電材料及び磁性材料の少なくとも一方
    からなる複数のシート層を積層してなる基板と、該基板
    の内部に形成される複数の内部電極と、該内部電極に接
    続されるとともに、前記基板の1つの端面にのみ形成さ
    れる複数の外部電極とを備え、 前記外部電極を備える前記基板の端面が、実装基板に実
    装する際の実装面となることを特徴とする積層電子部
    品。
    A substrate formed by laminating a plurality of sheet layers made of at least one of a dielectric material and a magnetic material, a plurality of internal electrodes formed inside the substrate, and connected to the internal electrodes; A multilayer electronic component, comprising: a plurality of external electrodes formed only on one end surface of the substrate; and an end surface of the substrate including the external electrodes serving as a mounting surface when mounted on a mounting substrate.
JP9097666A 1997-04-15 1997-04-15 Laminated electronic parts Pending JPH10289837A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9097666A JPH10289837A (en) 1997-04-15 1997-04-15 Laminated electronic parts

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9097666A JPH10289837A (en) 1997-04-15 1997-04-15 Laminated electronic parts

Publications (1)

Publication Number Publication Date
JPH10289837A true JPH10289837A (en) 1998-10-27

Family

ID=14198372

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9097666A Pending JPH10289837A (en) 1997-04-15 1997-04-15 Laminated electronic parts

Country Status (1)

Country Link
JP (1) JPH10289837A (en)

Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002057066A (en) * 2000-08-10 2002-02-22 Taiyo Yuden Co Ltd Chip array and its manufacturing method
JP2007005788A (en) * 2005-06-22 2007-01-11 Samsung Electro Mech Co Ltd Built-in vertical electrode lamination component and method for manufacturing same
JP2007049142A (en) * 2005-08-03 2007-02-22 Samsung Electronics Co Ltd Chip type electric element and liquid crystal display module containing it
US20140177128A1 (en) * 2012-12-20 2014-06-26 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic electronic component
JP2014165350A (en) * 2013-02-26 2014-09-08 Murata Mfg Co Ltd Process of manufacturing multilayer ceramic electronic component
US8879238B2 (en) 2012-12-11 2014-11-04 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic capacitor and method of manufacturing the same
US8913367B2 (en) 2012-12-11 2014-12-16 Samsung Electro-Mechanics Co., Ltd. Multilayered ceramic capacitor and method of manufacturing the same
KR20140144058A (en) 2013-06-10 2014-12-18 삼성전기주식회사 Multi-layered ceramic capacitor and board for mounting the same
KR20150017966A (en) 2013-08-08 2015-02-23 삼성전기주식회사 Multi-layered ceramic capacitor and board for mounting the same
KR20150019732A (en) 2013-08-14 2015-02-25 삼성전기주식회사 Multi-layered ceramic capacitor and board for mounting the same
US9001491B2 (en) 2012-12-18 2015-04-07 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic capacitor and circuit board with multilayer ceramic capacitor mounted thereon
US9087647B2 (en) 2012-12-11 2015-07-21 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic capacitor and method of manufacturing the same
US9165715B2 (en) 2012-12-10 2015-10-20 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic capacitor with electrodes having lead-out parts and method of manufacturing the same
US9218910B2 (en) 2012-12-21 2015-12-22 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic capacitor, manufacturing method of the same, and circuit board with multilayer ceramic capacitor mounted thereon
US9336950B2 (en) 2012-12-20 2016-05-10 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic capacitor having electrode lead outs that are overlapped and have curved surfaces, and method of manufacturing the same
US9336945B2 (en) 2013-10-28 2016-05-10 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic capacitor
US9412503B2 (en) 2013-02-28 2016-08-09 Murata Manufacturing Co., Ltd. Electronic component including outer electrodes provided on end portions of a surface of an electronic component body
US9424990B2 (en) 2013-05-21 2016-08-23 Samsung Electro-Mechanics Co., Ltd. Multilayered ceramic capacitor and board for mounting the same
US9576732B2 (en) 2013-05-21 2017-02-21 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic capacitor and mounting board therefor
US20170278631A1 (en) * 2016-03-22 2017-09-28 Samsung Electro-Mechanics Co., Ltd. Capacitor and method of manufacturing same
KR20170128183A (en) 2017-11-10 2017-11-22 삼성전기주식회사 Multi-layered ceramic capacitor, and manufacturing method of the same
US10028381B2 (en) 2015-07-17 2018-07-17 Samsung Electro-Mechanics Co., Ltd. Composite electronic component and board having the same
US10057988B2 (en) 2016-07-13 2018-08-21 Samsung Electro-Mechanics Co., Ltd. Multilayer capacitor and board having the same
US10121596B2 (en) 2015-12-11 2018-11-06 Murata Manufacturing Co., Ltd. Multilayer ceramic capacitor
US10312024B2 (en) 2015-12-03 2019-06-04 Murata Manufacturing Co., Ltd. Multilayer ceramic electronic component
US10522290B2 (en) 2015-12-03 2019-12-31 Murata Manufacturing Co., Ltd. Multilayer ceramic electronic component

Cited By (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002057066A (en) * 2000-08-10 2002-02-22 Taiyo Yuden Co Ltd Chip array and its manufacturing method
JP2007005788A (en) * 2005-06-22 2007-01-11 Samsung Electro Mech Co Ltd Built-in vertical electrode lamination component and method for manufacturing same
JP2007049142A (en) * 2005-08-03 2007-02-22 Samsung Electronics Co Ltd Chip type electric element and liquid crystal display module containing it
US9165715B2 (en) 2012-12-10 2015-10-20 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic capacitor with electrodes having lead-out parts and method of manufacturing the same
US9087647B2 (en) 2012-12-11 2015-07-21 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic capacitor and method of manufacturing the same
US8879238B2 (en) 2012-12-11 2014-11-04 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic capacitor and method of manufacturing the same
US8913367B2 (en) 2012-12-11 2014-12-16 Samsung Electro-Mechanics Co., Ltd. Multilayered ceramic capacitor and method of manufacturing the same
US9001491B2 (en) 2012-12-18 2015-04-07 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic capacitor and circuit board with multilayer ceramic capacitor mounted thereon
US9230738B2 (en) * 2012-12-20 2016-01-05 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic electronic component including a lateral surface and internal electrodes having different distances from the lateral surface
US9336950B2 (en) 2012-12-20 2016-05-10 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic capacitor having electrode lead outs that are overlapped and have curved surfaces, and method of manufacturing the same
US20140177128A1 (en) * 2012-12-20 2014-06-26 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic electronic component
US9218910B2 (en) 2012-12-21 2015-12-22 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic capacitor, manufacturing method of the same, and circuit board with multilayer ceramic capacitor mounted thereon
JP2014165350A (en) * 2013-02-26 2014-09-08 Murata Mfg Co Ltd Process of manufacturing multilayer ceramic electronic component
US9412503B2 (en) 2013-02-28 2016-08-09 Murata Manufacturing Co., Ltd. Electronic component including outer electrodes provided on end portions of a surface of an electronic component body
US9424990B2 (en) 2013-05-21 2016-08-23 Samsung Electro-Mechanics Co., Ltd. Multilayered ceramic capacitor and board for mounting the same
US9576732B2 (en) 2013-05-21 2017-02-21 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic capacitor and mounting board therefor
KR20140144058A (en) 2013-06-10 2014-12-18 삼성전기주식회사 Multi-layered ceramic capacitor and board for mounting the same
US9589728B2 (en) 2013-06-10 2017-03-07 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic capacitor and board for mounting the same
US9384893B2 (en) 2013-08-08 2016-07-05 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic capacitor and board having the same mounted thereon
KR20150017966A (en) 2013-08-08 2015-02-23 삼성전기주식회사 Multi-layered ceramic capacitor and board for mounting the same
KR20150019732A (en) 2013-08-14 2015-02-25 삼성전기주식회사 Multi-layered ceramic capacitor and board for mounting the same
US9336951B2 (en) 2013-08-14 2016-05-10 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic capacitor and board for mounting the same
US9336945B2 (en) 2013-10-28 2016-05-10 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic capacitor
US10028381B2 (en) 2015-07-17 2018-07-17 Samsung Electro-Mechanics Co., Ltd. Composite electronic component and board having the same
US10312024B2 (en) 2015-12-03 2019-06-04 Murata Manufacturing Co., Ltd. Multilayer ceramic electronic component
US10522290B2 (en) 2015-12-03 2019-12-31 Murata Manufacturing Co., Ltd. Multilayer ceramic electronic component
US10121596B2 (en) 2015-12-11 2018-11-06 Murata Manufacturing Co., Ltd. Multilayer ceramic capacitor
US10062506B2 (en) * 2016-03-22 2018-08-28 Samsung Electro-Mechanics Co., Ltd. Capacitor and method of manufacturing same
US20170278631A1 (en) * 2016-03-22 2017-09-28 Samsung Electro-Mechanics Co., Ltd. Capacitor and method of manufacturing same
US10978250B2 (en) 2016-03-22 2021-04-13 Samsung Electro-Mechanics Co., Ltd. Method of manufacturing capacitor
US10057988B2 (en) 2016-07-13 2018-08-21 Samsung Electro-Mechanics Co., Ltd. Multilayer capacitor and board having the same
KR20170128183A (en) 2017-11-10 2017-11-22 삼성전기주식회사 Multi-layered ceramic capacitor, and manufacturing method of the same

Similar Documents

Publication Publication Date Title
JPH10289837A (en) Laminated electronic parts
KR20040043736A (en) Ceramic Multilayer Substrate and its Manufacturing Process
US20040111880A1 (en) Multilayer electronic part and method of producing the same
JPH10294565A (en) Multilayer circuit substrate
JP2873645B2 (en) Manufacturing method of ceramic multilayer wiring board
JP2656585B2 (en) Integrated circuit components and their mounting structures
US5682674A (en) Dielectric filter and method of manufacturing the same
JP2003347160A (en) Multiple capacitor
JPH10200008A (en) Multilayer circuit board and manufacture thereof
JPH0897603A (en) Laminated dielectric filter
KR100397741B1 (en) Resonator
KR100558443B1 (en) Outer Terminal Structure of Low Temperature Co-fired Ceramic Substrate and the Manufacturing Process
JP2003282357A (en) Capacitor array
JPH10335822A (en) Multilayered ceramic circuit board
JPH077270A (en) Ceramic multilayer circuit board
JP2003273521A (en) Method for manufacturing ceramic multilayer substrate
JPH0945830A (en) Chip electronic component
JPH05166672A (en) Composite part
JPH11162782A (en) Laminated electronic part array
KR19990079689A (en) Manufacturing method of laminated ceramic parts
JP3161197B2 (en) Electronic component mounting structure
JP2005285994A (en) Surface-mounted multiple capacitor
JPH0572177U (en) Circuit module with multi-layer substrate
JP2005285993A (en) Surface-mounted multiple capacitor
JPH10190307A (en) High frequency module

Legal Events

Date Code Title Description
A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20040113