JP2606110B2 - Multilayer substrate and method of manufacturing the same - Google Patents

Multilayer substrate and method of manufacturing the same

Info

Publication number
JP2606110B2
JP2606110B2 JP5314762A JP31476293A JP2606110B2 JP 2606110 B2 JP2606110 B2 JP 2606110B2 JP 5314762 A JP5314762 A JP 5314762A JP 31476293 A JP31476293 A JP 31476293A JP 2606110 B2 JP2606110 B2 JP 2606110B2
Authority
JP
Japan
Prior art keywords
substrate
layer
semiconductor
bonding pad
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP5314762A
Other languages
Japanese (ja)
Other versions
JPH07169873A (en
Inventor
道則 小木曽
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP5314762A priority Critical patent/JP2606110B2/en
Publication of JPH07169873A publication Critical patent/JPH07169873A/en
Application granted granted Critical
Publication of JP2606110B2 publication Critical patent/JP2606110B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/10175Flow barriers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/38Effects and problems related to the device integration
    • H01L2924/384Bump effects
    • H01L2924/3841Solder bridging
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007Surface contacts, e.g. bumps
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、半導体のフリップチッ
プ実装に用いられる多層基板およびその製造方法に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer substrate used for flip-chip mounting of a semiconductor and a method of manufacturing the same.

【0002】[0002]

【従来の技術】従来、この種のフリップチップ実装はワ
イヤーを用いたマニュアルボンディングに比べ低コス
ト、生産性の向上が図れる等の利点を有するため、広く
使用されている。
2. Description of the Related Art Conventionally, flip-chip mounting of this type has been widely used because it has advantages such as lower cost and higher productivity than manual bonding using wires.

【0003】図5は従来のフリップチップ実装に用いら
れる基板およびその実装方法を説明する断面図である。
図5(a)に示すように、半導体11には電極2が設け
られている。次に図5(b)において、まず、この電極
12上に球状の半田バンプ13を形成する。半導体11
が実装される基板14には、半田バンプ13を介して電
極12と電気的に接続されるボンディングパッド15が
設けられている(なお、同図においては多層基板の第1
層基板のみ基盤14として示されている)。また、基板
14には半導体11を基板14に実装する際に、溶融し
た半田バンプ13がボンディングパッド15以外の回路
およびパターンに流れ込むのを防止するための厚膜ガラ
ス16が形成されている。この厚膜ガラス16は多層基
板における基板焼成処理の後にガラスペーストを塗布
し、焼成することにより形成される。
FIG. 5 is a cross-sectional view for explaining a conventional substrate used for flip-chip mounting and a mounting method thereof.
As shown in FIG. 5A, an electrode 2 is provided on a semiconductor 11. Next, in FIG. 5B, first, a spherical solder bump 13 is formed on the electrode 12. Semiconductor 11
Is mounted on a substrate 14 provided with bonding pads 15 that are electrically connected to the electrodes 12 via the solder bumps 13 (note that in FIG.
Only the layer substrate is shown as substrate 14). Further, a thick film glass 16 for preventing the molten solder bumps 13 from flowing into circuits and patterns other than the bonding pads 15 when the semiconductor 11 is mounted on the substrate 14 is formed on the substrate 14. The thick film glass 16 is formed by applying a glass paste and firing after the substrate firing process on the multilayer substrate.

【0004】このような構成において、半導体11を半
田バンプ13がボンディングパッド15上に接触するよ
うに基板14上に重ね合わせ、基板の低面より加熱す
る。この加熱により半田バンプが溶融し、電極12とボ
ンディングパッド15とは電気的に接続される。
In such a configuration, the semiconductor 11 is superimposed on the substrate 14 so that the solder bumps 13 are in contact with the bonding pads 15, and the semiconductor 11 is heated from a lower surface of the substrate. The heating melts the solder bumps, and the electrodes 12 and the bonding pads 15 are electrically connected.

【0005】また、この種の半導体が実装される基板お
よびその製造方法に関しては、例えば、1992年6月
19日公開の特開平4−171891号公報(文献1)
記載の構造および製造方法が知られている。この文献1
には、多層プリント配線板の表面中央部に凹部を有し、
縦断面がU字形である凹部の低面および側面を含む全面
に銅メッキが施された表面実装パッドが設けられた多層
プリント配線板が記載されている。
A substrate on which this type of semiconductor is mounted and a method of manufacturing the same are disclosed in, for example, Japanese Patent Application Laid-Open No. H4-171891, published June 19, 1992 (Document 1).
The described structures and manufacturing methods are known. This document 1
Has a recess at the center of the surface of the multilayer printed wiring board,
There is described a multilayer printed wiring board provided with copper-plated surface mounting pads on the entire surface including the lower surface and side surfaces of a concave portion having a U-shaped vertical section.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、図5に
示したフリップチップ実装に用いられる基板は基板焼成
後に厚膜ガラスを形成させるため、2度も基板を焼成し
なくてはならなく、製造工程が複雑である。また、ボン
ディングパッドと厚膜ガラスとの位置関係を正確に合わ
せる必要があるにもかかわらず、基板焼成時に基板を構
成するグリーンシートが縮むために、整合が不可能であ
る。
However, since the substrate used for flip-chip mounting shown in FIG. 5 forms a thick film glass after the substrate is baked, the substrate must be baked twice and the manufacturing process Is complicated. In addition, although the positional relationship between the bonding pad and the thick film glass needs to be accurately adjusted, the alignment is not possible because the green sheet constituting the substrate shrinks at the time of firing the substrate.

【0007】一方、文献1記載の基板およびその製造方
法は製造工程が非常に複雑であり、生産効率が低下する
という問題を有する。
On the other hand, the substrate and the method for manufacturing the substrate described in Document 1 have a problem that the manufacturing process is very complicated and the production efficiency is reduced.

【0008】本発明は上述した問題を解決し、半導体と
基盤との位置合わせが容易でしかも製造が容易なフリッ
プチップ実装用基板およびその製造方法を提供すること
にある。
An object of the present invention is to solve the above-mentioned problems and to provide a flip-chip mounting substrate and a method of manufacturing the flip-chip mounting substrate, in which the alignment between the semiconductor and the substrate is easy and the manufacturing is easy.

【0009】[0009]

【課題を解決するための手段】そこで、本発明では、多
層基板において、バンプ電極が電気的に接続するボンデ
ィングパッドの位置に整合するボンディングパッドを有
する層の基板より上位の層の基板にホールを設けること
により上記目的を達成している。
Therefore, according to the present invention, in a multilayer substrate, a hole is formed in a substrate of a layer higher than a substrate having a bonding pad matching a position of a bonding pad electrically connected to a bump electrode. The above-mentioned object is achieved by providing.

【0010】[0010]

【実施例】次に本発明について図面を参照して詳細に説
明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to the drawings.

【0011】まずはじめに、半導体と多層基板とのフリ
ップチップ実装方法について説明する。以下、本発明の
特徴である半導体と多層基板上のボンディングパッドと
の電気的接続構造および方法が理解し易いように3層か
らなる多層基板を例にとり説明する。
First, a method of flip-chip mounting a semiconductor and a multilayer substrate will be described. Hereinafter, a multi-layer substrate composed of three layers will be described as an example so that the electrical connection structure and method between the semiconductor and the bonding pads on the multi-layer substrate, which are features of the present invention, can be easily understood.

【0012】図1は、本発明の半導体のフリップチップ
実装方法を説明する断面図である。
FIG. 1 is a sectional view for explaining a flip-chip mounting method of a semiconductor according to the present invention.

【0013】図1において、図(a)は実装される半導
体1を示しており、従来の技術として図5で示した半導
体11と同様のものを用いる。図(b)は半田バンプ3
が形成された半導体1と、半導体1を実装するセラミッ
ク多層基板4を示している。図(b)において、基板4
の第1層7には、第2層8に設けられたボンディングパ
ッド5と対応する位置にホール6が設けられている。ま
た、同図には記載されていないが、第2および3層基
板、8および9は、各層に設けられたビアホールに導体
ペーストを充満させ、基板を焼成することにより電気的
に接続されている。また、第1および2の層基板、7お
よび8は前述した焼成により接合されている。
In FIG. 1, FIG. 1A shows a semiconductor 1 to be mounted, and a semiconductor similar to the semiconductor 11 shown in FIG. 5 is used as a conventional technique. Figure (b) shows solder bump 3
1 shows a semiconductor 1 on which a semiconductor layer 1 is formed and a ceramic multilayer substrate 4 on which the semiconductor 1 is mounted. In FIG.
The first layer 7 has a hole 6 at a position corresponding to the bonding pad 5 provided on the second layer 8. Although not shown in the figure, the second and third layer substrates 8 and 9 are electrically connected by filling the via holes provided in each layer with a conductive paste and firing the substrate. . The first and second layer substrates 7 and 8 are joined by the above-described firing.

【0014】このような構成において、まず、半田バン
プ3を、ボンディングパッド5上に接触するようにホー
ル6に挿入し、同図の矢印方向に半導体1と多層基板4
とを重ね合わせる。次に、多層基板4に下面より熱を加
えることにより半田バンプ3が溶融し、電極2とボンデ
ィングパッド5とは電気的に接続される。この時、第2
層8に設けられたボンディングパッド5以外の回路およ
びパターンには溶融した半田は流れ込まない。これは、
第1層7のホール6以外の部分が従来の技術として図5
で説明した厚膜ガラス16と同じ作用を有するからであ
る。
In such a configuration, first, the solder bump 3 is inserted into the hole 6 so as to be in contact with the bonding pad 5, and the semiconductor 1 and the multilayer substrate 4 are inserted in the direction of the arrow in FIG.
And overlap. Next, by applying heat to the multilayer substrate 4 from below, the solder bumps 3 are melted, and the electrodes 2 and the bonding pads 5 are electrically connected. At this time, the second
The molten solder does not flow into circuits and patterns other than the bonding pads 5 provided on the layer 8. this is,
The portion of the first layer 7 other than the hole 6 is a conventional technology shown in FIG.
This is because it has the same action as the thick film glass 16 described in (1).

【0015】次に、本発明による多層基板およびその製
造方法について図2および3を用いて説明する。
Next, a multilayer substrate and a method of manufacturing the same according to the present invention will be described with reference to FIGS.

【0016】まず、図(a)に示したグリーンシート1
0にパンチングにより穴をあけることによりホール6を
形成し、第1層基板7を得る。次に図(c)に示すよう
に第2層基板8に回路パターン18を形成するととも
に、半導体1の半田バンプ3と接触する部分にボンディ
ングパッド5を設ける。また、第3層基板9と電気的接
続を得るためのビアホール17を回路パターン18の端
部に設け、内部にはタングステン等の導体ペーストを充
填する。図(d)に示す第3層基板9には、第2層基板
8と同様に回路パターン18を設けるとともに、第2層
基板のビアホール17の位置と対応する位置に接続部1
9を設ける。
First, the green sheet 1 shown in FIG.
Holes 6 are formed by punching holes at 0 to obtain a first layer substrate 7. Next, as shown in FIG. 1C, a circuit pattern 18 is formed on the second layer substrate 8, and a bonding pad 5 is provided in a portion of the semiconductor 1 that contacts the solder bump 3. Further, via holes 17 for obtaining electrical connection with the third layer substrate 9 are provided at the ends of the circuit pattern 18, and the inside is filled with a conductive paste such as tungsten. A circuit pattern 18 is provided on the third layer substrate 9 shown in FIG. 4D in the same manner as the second layer substrate 8, and the connection portion 1 is provided at a position corresponding to the position of the via hole 17 on the second layer substrate.
9 is provided.

【0017】次に、図2に示した第1層〜第3層基板7
〜9を積み重ね、積層された基板を焼成することにより
第1層〜第3層からなる多層基板4を得る。なお、ホー
ル6を有する第1層基板7と第2層基板8との積層方法
は、図3に示すように、ホール6とボンディングパッド
5との位置が整合するように同図矢印の方向に積層す
る。
Next, the first to third layer substrates 7 shown in FIG.
9 are stacked and the laminated substrate is fired to obtain a multilayer substrate 4 including first to third layers. The method of laminating the first layer substrate 7 having the holes 6 and the second layer substrate 8 is as shown in FIG. 3 so that the positions of the holes 6 and the bonding pads 5 are aligned in the direction of the arrow in FIG. Laminate.

【0018】次に、図4を参照して本発明の第2の実施
例を説明する。図(b)に示すように、多層基板4の第
2および3層基板7および8には、各ボンディングパッ
ド5が設けられている。また、半田バンプ3とボンディ
ングパッド5とが電気的に接続されるよう第1および2
層基板7および8にホール6が設けられている。ただ
し、第2基板8には回路パターンが形成されているた
め、この回路パターンとホール6が交叉しないようにホ
ール6が設けられている。各層基板上のボンディングパ
ッド5、ホール6、および回路パターンの形成方法は第
1の実施例と全く同様である。また、実装方法について
も同様である。
Next, a second embodiment of the present invention will be described with reference to FIG. As shown in FIG. 2B, bonding pads 5 are provided on the second and third layer substrates 7 and 8 of the multilayer substrate 4. The first and second solder bumps 3 and the bonding pads 5 are electrically connected to each other.
Holes 6 are provided in layer substrates 7 and 8. However, since a circuit pattern is formed on the second substrate 8, the holes 6 are provided so that the circuit patterns do not cross the holes 6. The method of forming the bonding pads 5, holes 6, and circuit patterns on each layer substrate is exactly the same as in the first embodiment. The same applies to the mounting method.

【0019】[0019]

【発明の効果】以上説明したように、本発明による多層
基板では、下位層にバンプ電極が電気的に接続されるボ
ンディングパッドが設けられ、上位層に、ボンディング
パッドの対応する位置にホールが設けられているため、
従来のように、上位層に半田流れ防止用の厚膜ガラスを
形成させる必要がなく、1度の基板焼成で多層基板を得
ることができる。また、ボンディングパッドと厚膜ガラ
スとの位置関係の整合を行う必要がない。このため、フ
リップチップ実装用多層基板の製造工程が大幅に簡略化
でき、生産効率が向上するという効果を有する。
As described above, in the multilayer substrate according to the present invention, bonding pads for electrically connecting the bump electrodes are provided in the lower layer, and holes are provided in the upper layer at positions corresponding to the bonding pads. Has been
Unlike the related art, it is not necessary to form a thick film glass for preventing solder flow on the upper layer, and a multilayer substrate can be obtained by one firing of the substrate. Further, there is no need to match the positional relationship between the bonding pad and the thick film glass. For this reason, the manufacturing process of the multilayer substrate for flip-chip mounting can be greatly simplified, and there is an effect that the production efficiency is improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例を説明する第2層基板のみに
ボンディングパッドがある場合の半導体のフリップチッ
プ実装を説明する断面図。
FIG. 1 is a cross-sectional view illustrating flip-chip mounting of a semiconductor in a case where a bonding pad is provided only on a second layer substrate for explaining an embodiment of the present invention.

【図2】本発明の一実施例である多層基板およびその製
造方法を説明する斜視図。
FIG. 2 is a perspective view illustrating a multilayer substrate according to one embodiment of the present invention and a method for manufacturing the same.

【図3】図2に示した多層基板の第1層基板を積層する
状態を示す斜視図。
FIG. 3 is a perspective view showing a state in which a first layer substrate of the multilayer substrate shown in FIG. 2 is stacked;

【図4】本発明の第2の実施例を説明する多層基板の第
2および3層基板にボンディングパッドを有する多層基
板およびその実装方法を説明する断面図。
FIG. 4 is a cross-sectional view illustrating a multi-layer board having bonding pads on second and third-layer boards of a multi-layer board for explaining a second embodiment of the present invention and a mounting method thereof.

【図5】従来のフリップチップ実装に用いられる基板お
よびその実装方法を説明する断面図。
FIG. 5 is a cross-sectional view illustrating a substrate used for conventional flip chip mounting and a mounting method thereof.

【符号の説明】[Explanation of symbols]

1 半導体 2 電極 3 半田バンプ 4 多層基板 5 ボンディングパッド 6 ホール 7 第1層基板 8 第2層基板 9 第3層基板 10 グリーンシート 11 半導体 12 電極 13 半田バンプ 14 基板 15 ボンディングパッド 16 厚膜ガラス 17 ビアホール 18 回路 19 接続部 Reference Signs List 1 semiconductor 2 electrode 3 solder bump 4 multilayer substrate 5 bonding pad 6 hole 7 first layer substrate 8 second layer substrate 9 third layer substrate 10 green sheet 11 semiconductor 12 electrode 13 solder bump 14 substrate 15 bonding pad 16 thick glass 17 Via hole 18 Circuit 19 Connection

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H05K 3/34 507 H01L 23/12 N ──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 6 Identification code Agency reference number FI Technical display location H05K 3/34 507 H01L 23/12 N

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 半導体の電極と接続される第1のボンデ
ィングパットを有する第3層の基板と、 該第3層の基板上に配置され、前記第1のボンディング
パットの対応する位置に第1のホールを有するととも
に、前記第1のホールが形成された位置とは異なる位置
に前記電極に接続される第2のボンディングパットを有
する第2層の基板とを備え、さらに、 前記第2層基板の上に配置され、前記第1のホールおよ
び前記第2のボンディングパットの対応する位置に第2
のホールを有する第1層の基板を 備えていることを特徴とする多層基板。
1. A third layer substrate having a first bonding pad connected to a semiconductor electrode, and a first bonding pad disposed on the third layer substrate and corresponding to a first bonding pad at a position corresponding to the first bonding pad. And a second-layer substrate having a second bonding pad connected to the electrode at a position different from the position where the first hole is formed, further comprising: And a second hole at a corresponding position of the first hole and the second bonding pad.
A multilayer substrate, comprising: a first layer substrate having a hole.
【請求項2】 半導体の多層基板へのフリップチップ
装構造において、 前記半導体に設けられた電極上の半田バンプが、請求項
1記載の多層基板の前記第1のホールおよび前記第2の
ホールにそれぞれ挿入され、 前記多層基板が加熱、冷却されて、前記半田バンプによ
り前記電極が前記第1のボンディングパッドと前記第2
のボンディングパットに電気的に接続されていることを
特徴とするフリップチップ実装構造。
2. The flip- chip mounting structure of a semiconductor on a multilayer substrate, wherein the solder bumps on the electrodes provided on the semiconductor are formed on the first hole and the solder hole on the multilayer substrate according to claim 1. The multilayer board is heated and cooled by inserting the electrodes into the second holes, and the electrodes are connected to the first bonding pads and the second bonding pads by the solder bumps.
A flip- chip mounting structure, wherein the flip- chip mounting structure is electrically connected to the bonding pad.
【請求項3】 請求項1記載の多層基板は、少なくとも
前記第2層の基板および前記第3層の基板にビアホール
を有し、 前記ビアホールに導体ペーストを充填する工程と、 前記第1層から前記第3層までの基板を位置合わせして
積層させる工程と、 積層された前記第1層から第3層までの3枚の基板を焼
成する工程と を含むことを特徴とする請求項1記載の多層基板の製造
方法。
3. The multi-layer substrate according to claim 1, wherein at least the second layer substrate and the third layer substrate have via holes, and the via holes are filled with a conductive paste; 2. The method according to claim 1, further comprising: aligning and stacking the substrates up to the third layer; and firing the three substrates from the first layer to the third layer. 3. Production method of a multilayer substrate.
JP5314762A 1993-12-15 1993-12-15 Multilayer substrate and method of manufacturing the same Expired - Fee Related JP2606110B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5314762A JP2606110B2 (en) 1993-12-15 1993-12-15 Multilayer substrate and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5314762A JP2606110B2 (en) 1993-12-15 1993-12-15 Multilayer substrate and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JPH07169873A JPH07169873A (en) 1995-07-04
JP2606110B2 true JP2606110B2 (en) 1997-04-30

Family

ID=18057282

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5314762A Expired - Fee Related JP2606110B2 (en) 1993-12-15 1993-12-15 Multilayer substrate and method of manufacturing the same

Country Status (1)

Country Link
JP (1) JP2606110B2 (en)

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US7297572B2 (en) 2001-09-07 2007-11-20 Hynix Semiconductor, Inc. Fabrication method for electronic system modules
US6927471B2 (en) * 2001-09-07 2005-08-09 Peter C. Salmon Electronic system modules and method of fabrication
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CN110690129A (en) * 2019-09-24 2020-01-14 浙江集迈科微电子有限公司 Three-dimensional heterogeneous stacking method with anti-overflow tin structure
CN110690129B (en) * 2019-09-24 2021-05-28 浙江集迈科微电子有限公司 Three-dimensional heterogeneous stacking method with anti-overflow tin structure

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