JPS6242539Y2 - - Google Patents
Info
- Publication number
- JPS6242539Y2 JPS6242539Y2 JP1981013018U JP1301881U JPS6242539Y2 JP S6242539 Y2 JPS6242539 Y2 JP S6242539Y2 JP 1981013018 U JP1981013018 U JP 1981013018U JP 1301881 U JP1301881 U JP 1301881U JP S6242539 Y2 JPS6242539 Y2 JP S6242539Y2
- Authority
- JP
- Japan
- Prior art keywords
- insulating substrate
- insulating
- integrated circuit
- hybrid integrated
- substrates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 27
- 239000011347 resin Substances 0.000 claims description 15
- 229920005989 resin Polymers 0.000 claims description 15
- 239000004020 conductor Substances 0.000 claims description 11
- 239000003990 capacitor Substances 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910001369 Brass Inorganic materials 0.000 description 1
- 229910000906 Bronze Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000010951 brass Substances 0.000 description 1
- 239000010974 bronze Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 238000004132 cross linking Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
Description
【考案の詳細な説明】 本考案は混成集積回路に関するものである。[Detailed explanation of the idea] The present invention relates to hybrid integrated circuits.
一般に混成集積回路は第1図および第2図に示
すようにアルミナなどの絶縁基板1の表面に銀、
パラジウム−銀などの配線導体層および抵抗体層
をスクリーン印刷法によつて順次印刷、焼成して
形成し、これに半導体、コンデンサなどからなる
チツプ状の個別部品および引出端子2を装着し、
それぞれはんだで接続した後、デイツプ法、粉体
塗装法などによつて外装樹脂3を被覆して構成さ
れていた。 Generally, a hybrid integrated circuit has silver or silver on the surface of an insulating substrate 1 made of alumina or the like, as shown in FIGS. 1 and 2.
A wiring conductor layer and a resistor layer made of palladium-silver or the like are sequentially printed and fired using a screen printing method, and chip-shaped individual parts made of semiconductors, capacitors, etc. and lead-out terminals 2 are attached thereto.
After each connection is made with solder, the exterior resin 3 is coated using a dip method, a powder coating method, or the like.
しかし第1図に示すようなシングルインライン
形の混成集積回路においては、集積素子数や塔載
部品点数が多くなると製品の高さが大になり固定
が不安定になる。また第2図に示すようなデユア
ルインライン形の混成集積回路においては、上述
のような場合引出端子2の引出方向が絶縁基板1
の面に対して垂直に導出されているので樹脂3が
塗布し難い欠点があつた。 However, in a single in-line type hybrid integrated circuit as shown in FIG. 1, as the number of integrated elements and components increases, the height of the product increases and the fixation becomes unstable. Furthermore, in a dual-in-line type hybrid integrated circuit as shown in FIG.
Since the resin 3 is drawn out perpendicularly to the surface of the resin 3, it is difficult to apply the resin 3 thereto.
本考案は上述の欠点を除去し、品質が著しく向
上しかつ安価に製作できる混成集積回路を提供し
ようとするものである。 The present invention aims to eliminate the above-mentioned drawbacks and to provide a hybrid integrated circuit which has significantly improved quality and can be manufactured at low cost.
すなわち、配線導体層、抵抗体層、半導体コン
デンサなどからなる回路パターンを表面に形成
し、かつ所定の間隔をおいて平行に配置した複数
の絶縁基板と、該絶縁基板間に架橋した接続用フ
レームと、該絶縁基板に固定されかつ配線導体層
と接続した引出端子と、上記それぞれの絶縁基板
の表裏両面を被覆した外装樹脂とを具備してなる
混成集積回路である。 That is, a plurality of insulating substrates on which circuit patterns consisting of wiring conductor layers, resistor layers, semiconductor capacitors, etc. are formed and arranged in parallel at predetermined intervals, and a connection frame bridged between the insulating substrates. This is a hybrid integrated circuit comprising: a lead terminal fixed to the insulating substrate and connected to the wiring conductor layer; and an exterior resin covering both the front and back surfaces of each of the insulating substrates.
以下本考案を第3図〜第6図に示す実施例につ
いて説明する。 The present invention will be described below with reference to embodiments shown in FIGS. 3 to 6.
第3図は接続用フレーム4の斜視図で、該フレ
ーム4は銅、真鍮、リン青銅などの導体をプレス
して打ち抜いて形成されたもので、その両端部に
は絶縁基板1を挿入し挾持できる凹部4′が設け
られている。 FIG. 3 is a perspective view of the connection frame 4. The frame 4 is formed by pressing and punching a conductor such as copper, brass, or phosphor bronze, and the insulating substrate 1 is inserted into both ends of the frame 4. A recess 4' is provided.
まずアルミナなどからなる2枚の絶縁基板5に
上述と同様にしてそれぞれ配線導体層6、抵抗体
層を形成した回路パターンに、半導体、コンデン
サを装着し、該絶縁基板5に設けた配線導体層6
の引出部に引出端子2を装着するとともに、第4
図および第5図に示すように2枚の絶縁基板5を
背面に絶縁基板などを挟まず所定の間隔Lを設け
て平行に配置して接続用フレーム4を架橋し、溶
融はんだに浸漬するなどしてそれぞれ接続部を電
気的に接続する。これによりそれぞれの絶縁基板
5に引出端子2が固定されるとともに接続用フレ
ーム4によつて2枚の絶縁基板5が保持される。
また配線導体層6と接続用フレーム4がはんだに
よつて接続できるので、2枚の絶縁基板5間が電
気的にも接続されることになる。次いで第6図に
示すようにデイツプ法、粉体塗装法などにより上
記絶縁基板5に外装樹脂3を塗布、硬化すること
により上記平行に配置した絶縁基板の間を外装樹
脂3で充填せず、それぞれの絶縁基板5の表裏両
面を外装樹脂3によつて被覆して完成する。 First, a semiconductor and a capacitor are attached to a circuit pattern in which a wiring conductor layer 6 and a resistor layer are respectively formed on two insulating substrates 5 made of alumina or the like in the same manner as described above, and a wiring conductor layer provided on the insulating substrate 5. 6
At the same time as attaching the drawer terminal 2 to the drawer part of the fourth
As shown in FIG. 5 and FIG. 5, two insulating substrates 5 are arranged in parallel with a predetermined distance L between them without sandwiching the insulating substrates on the back side, and the connecting frame 4 is bridged, and the connecting frame 4 is immersed in molten solder. to electrically connect the respective connection parts. As a result, the lead terminals 2 are fixed to the respective insulating substrates 5, and the two insulating substrates 5 are held by the connection frame 4.
Further, since the wiring conductor layer 6 and the connection frame 4 can be connected by solder, the two insulating substrates 5 are also electrically connected. Next, as shown in FIG. 6, the exterior resin 3 is applied to the insulating substrate 5 by dip method, powder coating method, etc. and cured, so that the space between the parallel insulating substrates is not filled with the exterior resin 3. Both the front and back surfaces of each insulating substrate 5 are coated with exterior resin 3 to complete the process.
本考案の混成集積回路は以上のようにして構成
されたものである。 The hybrid integrated circuit of the present invention is constructed as described above.
したがつて接続用フレーム4によつて絶縁基板
5間が所定の間隔Lを設けて平行に配置されるの
で、外装樹脂3を被覆する際、この間隔Lから外
装樹脂が容易に進入するため、絶縁基板5の背面
にも外装樹脂3が確実に被覆できるので、耐湿性
が著しく向上する、安定して固定できる、極めて
安価に生産できるなどの効果が生ずる。 Therefore, since the insulating substrates 5 are arranged in parallel with a predetermined distance L between them by the connecting frame 4, when covering the exterior resin 3, the exterior resin easily enters from this distance L. Since the back surface of the insulating substrate 5 can also be reliably coated with the exterior resin 3, effects such as significantly improved moisture resistance, stable fixing, and extremely low cost production are produced.
なお、上述の実施例は絶縁基板5間に架橋した
接続用フレーム4は金属製の導体について述べた
が、絶縁物であつてもよい。また接続用フレーム
の形状、架橋の位置など実施例に限定するもので
なく、絶縁基板5も3枚以上複数枚を上述と同様
に所定の間隔を設けて平行になるよう配置し、そ
れぞれを接続用フレームで架橋して同様に構成
し、より集積度の高いものを得ることもできる。
さらに樹脂ケースに収納し、これに樹脂を充填し
て構成したものも同様な効果を奏することはいう
までもない。 In the above embodiment, the connecting frame 4 bridged between the insulating substrates 5 is made of a metal conductor, but it may be made of an insulating material. Further, the shape of the connection frame and the position of the bridge are not limited to the examples, and three or more insulating substrates 5 are arranged in parallel with a predetermined interval in the same manner as described above, and each is connected. It is also possible to construct a similar structure by cross-linking with a frame for obtaining a higher degree of integration.
Furthermore, it goes without saying that similar effects can be obtained by storing the device in a resin case and filling the resin case.
叙上のように本考案の混成集積回路は品質なら
びに価格の面において極めて有利となり、工業的
ならびに実用的価値の大なるものである。 As mentioned above, the hybrid integrated circuit of the present invention is extremely advantageous in terms of quality and price, and has great industrial and practical value.
第1図および第2図は従来の混成集積回路の要
部切断斜視図、第3図は本考案に係る接続用フレ
ームの斜視図、第4図は本考案の混成集積回路の
組立要部の斜視図、第5図は本考案の混成集積回
路の外装前の側面図、第6図は本考案の混成集積
回路の完成側面図である。
2……引出端子、3……外装樹脂、4……接続
用フレーム、5……絶縁基板、6……配線導体
層。
1 and 2 are cutaway perspective views of the main parts of a conventional hybrid integrated circuit, FIG. 3 is a perspective view of a connection frame according to the present invention, and FIG. 4 is a main part of the assembly of the hybrid integrated circuit of the present invention. FIG. 5 is a side view of the hybrid integrated circuit of the present invention before packaging, and FIG. 6 is a completed side view of the hybrid integrated circuit of the present invention. 2... Output terminal, 3... Exterior resin, 4... Connection frame, 5... Insulating board, 6... Wiring conductor layer.
Claims (1)
どからなる回路パターンを表面に形成し、かつ背
面に絶縁基板などを挟まず、所定の間隔を設けて
平行に配置した複数の絶縁基板と、該絶縁基板間
に架橋した接続用フレームと、該絶縁基板に固定
されかつ配線導体層と接続した引出端子と、上記
平行に配置した絶縁基板の間を充填せず、それぞ
れの絶縁基板の表裏両面を被覆した外装樹脂とを
充填してなる混成集積回路。 A plurality of insulating substrates, each having a circuit pattern made of a wiring conductor layer, a resistor layer, a semiconductor, a capacitor, etc. formed on the surface and arranged in parallel at a predetermined interval without sandwiching an insulating substrate on the back side, and the insulating substrate Covering both the front and back of each insulating substrate without filling the space between the connecting frame bridged between the substrates, the pull-out terminal fixed to the insulating substrate and connected to the wiring conductor layer, and the insulating substrates arranged in parallel. A hybrid integrated circuit formed by filling an exterior resin.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1981013018U JPS6242539Y2 (en) | 1981-01-30 | 1981-01-30 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1981013018U JPS6242539Y2 (en) | 1981-01-30 | 1981-01-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57125548U JPS57125548U (en) | 1982-08-05 |
JPS6242539Y2 true JPS6242539Y2 (en) | 1987-10-31 |
Family
ID=29811112
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1981013018U Expired JPS6242539Y2 (en) | 1981-01-30 | 1981-01-30 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6242539Y2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006126399A (en) | 2004-10-28 | 2006-05-18 | Oki Data Corp | Display panel structure and image forming apparatus having display panel structure |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6020947Y2 (en) * | 1979-10-23 | 1985-06-22 | 富士通株式会社 | Hybrid IC |
-
1981
- 1981-01-30 JP JP1981013018U patent/JPS6242539Y2/ja not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS57125548U (en) | 1982-08-05 |
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