JPH02249291A - Printed wiring board - Google Patents

Printed wiring board

Info

Publication number
JPH02249291A
JPH02249291A JP7128389A JP7128389A JPH02249291A JP H02249291 A JPH02249291 A JP H02249291A JP 7128389 A JP7128389 A JP 7128389A JP 7128389 A JP7128389 A JP 7128389A JP H02249291 A JPH02249291 A JP H02249291A
Authority
JP
Japan
Prior art keywords
wiring board
printed wiring
copper foil
layers
face
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7128389A
Other languages
Japanese (ja)
Inventor
Osamu Gunji
郡司 修
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP7128389A priority Critical patent/JPH02249291A/en
Publication of JPH02249291A publication Critical patent/JPH02249291A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0296Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298Multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092Dispersed materials, e.g. conductive pastes or inks
    • H05K1/095Dispersed materials, e.g. conductive pastes or inks for polymer thick films, i.e. having a permanent organic polymeric binder

Abstract

PURPOSE:To sharply decrease interference between the signal lines of a wiring board and electrostatic induction and electromagnetic induction noises from the outside and facilitate installation and correction of a wiring by making the printed wiring board, forming insulating films of insulating varnish on the external layers thereof, applying conductive paste into face form on said insulat ing films, and forming shielding layers by heat treatment. CONSTITUTION:Layer-shaped copper foil pattern layers 2 are formed on prepreg (substrates) 1. The copper foil pattern layers 2 construct circuit patterns includ ing signal lines. A face pattern formed in one of copper foil layers 3 consisting of face patterns is made to be a power source line and the face pattern in the other copper foil layer is made to be a grounding line. After a printed wiring board is completed, insulating varnish is applied on to the copper foil pattern layers 2 formed on the surfaces of the prepreg 1, conductive paste is applied on to the insulating varnish 5, and face-shaped conductive films 6 are formed by heat treatment.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はプリント配線基板に関し、特に、高周波回路基
板に好適なプリント配線基板に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a printed wiring board, and particularly to a printed wiring board suitable for a high frequency circuit board.

〔従来技術〕[Prior art]

第6図は従来の多層プリント配線基板の一例を示したも
ので、同図に示すように、従来のプリント配線基板は、
絶縁層となるプリプレグ(基板本体)1の表面に信号線
、電源線、接地線等の銅箔パターン層2“を形成してな
る。
FIG. 6 shows an example of a conventional multilayer printed wiring board. As shown in the figure, the conventional printed wiring board is
A copper foil pattern layer 2'' for signal lines, power lines, ground lines, etc. is formed on the surface of a prepreg (substrate body) 1 serving as an insulating layer.

この種のプリント配線基板は低周波の場合には、基板内
部から発生する電磁誘導等による信号線間の電磁結合が
比較的小さく問題とならないが、動作周波数が高周波(
VHF)になるにつれて信号線間の電磁結合が密となる
ため、互いの信号が干渉し合い、この信号干渉が回路誤
動作の原因となると言う問題があった。また、基板に遮
蔽層がないと、電磁誘導、静電誘導等の外来ノイズを受
は易いと言う問題もあり、導電性のシールドケース等を
取り付ける等の処理を施す必要がある。一方、実開昭5
0−11160号公報等に示されるように、基板に遮蔽
層を設げた構造も多数提案されているが、構成が複雑化
してコストアップする不都合がある。
With this type of printed wiring board, when the operating frequency is low, the electromagnetic coupling between the signal lines due to electromagnetic induction generated from inside the board is relatively small and does not pose a problem, but when the operating frequency is high (
Since the electromagnetic coupling between the signal lines becomes denser as the frequency becomes higher (VHF), there is a problem in that the signals interfere with each other, and this signal interference causes circuit malfunction. Furthermore, if the board does not have a shielding layer, there is a problem in that it is susceptible to external noise such as electromagnetic induction and electrostatic induction, so it is necessary to take measures such as attaching a conductive shielding case or the like. On the other hand, Jikai Showa 5
As shown in Japanese Patent Application No. 0-11160, many structures in which a shielding layer is provided on a substrate have been proposed, but these have the disadvantage of complicating the structure and increasing costs.

そこで、実開昭63−60330号(昭和63年5月7
日出願)として、基板表面に電源線や接地線を面パター
ン状に形成したプリント配線基板を提案した。
Therefore, Utility Model No. 63-60330 (May 7, 1988)
The company proposed a printed wiring board with power supply lines and ground lines formed in a planar pattern on the surface of the board.

このプリント配線基板によると、電源線や接地線が遮蔽
効果を有するので、構成の複雑化、コストアップを抑え
ることができる。
According to this printed wiring board, since the power supply line and the ground line have a shielding effect, it is possible to suppress the complexity of the configuration and increase in cost.

〔発明が解決しようとする課題) しかし、実開昭63−60330号では、電源線や接地
線が基板と一体になっており、信号線が基板の内部に形
成されているため、布線の修正等が困難となる等の問題
があった。
[Problems to be Solved by the Invention] However, in Utility Model Application Publication No. 63-60330, the power supply line and the ground line are integrated with the board, and the signal line is formed inside the board, so wiring is difficult. There were problems such as making corrections difficult.

従って本発明の目的とするところは、プリント配線基板
の信号線間の干渉や外部からの静電誘導や電磁誘導ノイ
ズを大幅に減少させ、かつ、布線の配設・修正等を容易
に行えるプリント配線基板を提供することである。
Therefore, it is an object of the present invention to significantly reduce interference between signal lines on a printed wiring board, as well as external electrostatic induction and electromagnetic induction noise, and to facilitate wiring arrangement and modification. An object of the present invention is to provide a printed wiring board.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は前述した目的を実現するため、プリント配線基
板完成後に、プリント配線基板の外層に、絶縁塗料によ
り絶縁膜を形成後、絶縁膜上に導電性ペーストを面状に
施し、熱処理によって遮蔽層を形成したプリント配線基
板を提供するものである。
In order to achieve the above-mentioned object, the present invention forms an insulating film on the outer layer of the printed wiring board using an insulating paint after the printed wiring board is completed, and then applies a conductive paste on the insulating film in a planar manner, and then heat-treats it to form a shielding layer. The present invention provides a printed wiring board formed with the following.

即ち、本発明のプリント配線基板は、絶縁膜。That is, the printed wiring board of the present invention has an insulating film.

および、導電性ペーストを熱処理した導電体で基板の表
面を面状に覆い、かつ、前記導電体を多層プリント配線
基板の電源線や接地線等に接続することにより、信号線
のインピーダンスを下げ信号線間の電磁誘導による干渉
を防止し、かつ、基板の表面を電源電位や接地電位で覆
う箔状の導電体に遮蔽の役割を担わせ、誘導ノイズを大
幅に減少させるようにしたものである。前記導電体を基
板完成後に取付は可能とすることにより、布線の配設・
修正等を容易に行うことができる。
Then, by covering the surface of the board with a conductive material made of heat-treated conductive paste, and connecting the conductive material to the power supply line, grounding line, etc. of the multilayer printed wiring board, the impedance of the signal line is lowered and the signal This prevents interference due to electromagnetic induction between wires, and uses a foil-like conductor that covers the surface of the board with power supply potential and ground potential to play a shielding role, greatly reducing induced noise. . By making it possible to attach the conductor after the board is completed, wiring arrangement and
Corrections etc. can be easily made.

〔実施例〕〔Example〕

本発明の実施例を第1図〜第5図に基づき説明する。 Embodiments of the present invention will be described based on FIGS. 1 to 5.

第1図は本発明の第一の実施例を示す要部断面図である
。1は絶縁体よりなるプリプレグ(基板)で、プリプレ
グ1には層状の銅箔パターン層2が形成される。この銅
箔パターン層2は信号線を含む回路パターンを構成する
。3は面パターンで形成される銅箔層で、例えば、一方
に形成される面パターンが電源線となり、他方の面パタ
ーンが接地線となる。4は部品半田付部やスルーホール
等以外の部品の半田付時の半田付着防止を目的とするソ
ルダーレジストで電気的絶縁性を有する。5は基板完成
後、プリプレグ1の表面に形成された銅箔パターン層2
上に塗り付けられた絶縁塗料である。6は絶縁塗料5上
に導電性ペーストを塗り、熱処理によって作成した面状
の導電性膜である。
FIG. 1 is a sectional view of a main part showing a first embodiment of the present invention. Reference numeral 1 denotes a prepreg (substrate) made of an insulator, and a layered copper foil pattern layer 2 is formed on the prepreg 1. This copper foil pattern layer 2 constitutes a circuit pattern including signal lines. Reference numeral 3 denotes a copper foil layer formed in a plane pattern, for example, the plane pattern formed on one side becomes a power supply line, and the other plane pattern becomes a ground line. Reference numeral 4 is a solder resist that has electrical insulation properties and is intended to prevent solder adhesion during soldering of parts other than soldered parts and through holes. 5 is a copper foil pattern layer 2 formed on the surface of the prepreg 1 after the board is completed.
This is an insulating paint applied on top. 6 is a planar conductive film created by applying a conductive paste on the insulating paint 5 and subjecting it to heat treatment.

6の導電性膜はプリプレグl上および銅箔パターン1!
2上に絶縁塗料を介して設けても良い。また、プリプレ
グ1の表面は部品取付面や半田付面も兼ねる。
The conductive film 6 is on the prepreg l and the copper foil pattern 1!
It may be provided on 2 with an insulating paint interposed therebetween. Further, the surface of the prepreg 1 also serves as a component mounting surface and a soldering surface.

このような構成によれば、第1にはプリプレグ1の内層
や外層に信号線2を配し、さらに、後述するように、プ
リプレグ1の表面を銅箔等で覆うことで信号線の特性イ
ンピーダンスを小さくすることができる。これを第2図
、第3図に基づいて説明すると次のようになる。
According to such a configuration, firstly, the signal line 2 is arranged on the inner layer or outer layer of the prepreg 1, and furthermore, as described later, the characteristic impedance of the signal line is reduced by covering the surface of the prepreg 1 with copper foil or the like. can be made smaller. This will be explained as follows based on FIGS. 2 and 3.

第2図および第3図は、本実施例の信号線2をストリッ
プラインとしてモデル化したもので、第2図は不平衡形
ストリップラインとしてのモデル、第3図は平衡形スト
リップラインとしてのモデルを表す。一般に、第2図の
モデルではストリップラインの特性インピーダンスZ。
2 and 3 model the signal line 2 of this embodiment as a stripline. FIG. 2 is a model as an unbalanced stripline, and FIG. 3 is a model as a balanced stripline. represents. Generally, in the model shown in Figure 2, the characteristic impedance Z of the strip line.

は(1)式で表される。is expressed by equation (1).

ここでErはプリプレグ1の実効誘電率2Wは信号線等
をストリップラインとみなした時の導体幅Tは信号線等
をストリップラインとみなした時の導体厚、Hは不平衡
形ストリップラインのプリプレグ1の厚さである。
Here, Er is the effective permittivity of the prepreg 1, 2W is the conductor width when the signal line, etc. is considered as a strip line, T is the conductor thickness when the signal line, etc. is considered as a strip line, and H is the prepreg of the unbalanced strip line. The thickness is 1.

一方、第3図の平衡形ストリップラインのモデルでは、
特性インピーダンスZ0は(2)式で表される。
On the other hand, in the balanced strip line model shown in Figure 3,
Characteristic impedance Z0 is expressed by equation (2).

ここで、Lは平衡形ストリップラインのプリプレグ1の
厚さである。(1)式、(2)式から信号線を含む回路
パターン2をプリプレグ1の内・外層に形成し、電源線
3.接地線3を配置し、さらに、導電性膜6で覆うこと
により特性インピーダンスを小さくできる。その結果、
誘導される電圧が小さくなり信号間の電磁干渉を防止す
ることができる。
Here, L is the thickness of the prepreg 1 of the balanced stripline. From formulas (1) and (2), a circuit pattern 2 including signal lines is formed on the inner and outer layers of the prepreg 1, and a power supply line 3. The characteristic impedance can be reduced by arranging the ground line 3 and further covering it with the conductive film 6. the result,
The induced voltage is reduced, and electromagnetic interference between signals can be prevented.

前述したように、プリプレグ1の表面を電源線や接地線
等の導電性膜6で覆うために、この面が静電遮蔽の役割
をなし、外来ノイズに対する遮蔽や内部から発するノイ
ズの遮蔽効果が改善される。
As mentioned above, since the surface of the prepreg 1 is covered with the conductive film 6 such as the power line and the ground line, this surface plays the role of electrostatic shielding, and has the effect of shielding against external noise and noise emitted from inside. Improved.

また、導電性膜6は外部に塗り付けられるために、希望
する遮蔽効果に応じて導電性膜6の厚さ(電気抵抗)等
を変えることができる。従って、本実施例によれば、高
信頼性のプリント配線基板の製作が可能である。
Further, since the conductive film 6 is applied externally, the thickness (electrical resistance) etc. of the conductive film 6 can be changed depending on the desired shielding effect. Therefore, according to this embodiment, it is possible to manufacture a highly reliable printed wiring board.

第4図は本発明の第2の実施例を示すもので、本実施例
はプリプレグ1の内層に信号線等の銅箔パターンN2を
複数層形成する他に、各銅箔パターン層2の上下に電源
線あるいは接地線の面パターン銅箔N3を配したもので
、さらに、基板完成後、電源線や接地線等の導電性膜6
で覆ったものである。この実施例は第1の実施例より更
にインピーダンスを低くすることが可能でより高信頼性
を有する多層プリント配線基板を提供することができる
FIG. 4 shows a second embodiment of the present invention. In this embodiment, in addition to forming multiple layers of copper foil patterns N2 such as signal lines on the inner layer of the prepreg 1, A surface pattern copper foil N3 for the power supply line or ground line is arranged on the surface, and after the board is completed, a conductive film 6 for the power supply line or the ground line is arranged.
It is covered with This embodiment can lower impedance even further than the first embodiment, and can provide a multilayer printed wiring board with higher reliability.

第5図は本発明の第3の実施例を示すもので第1の実施
例に対し、部品(デバイス)7の取付完了後に部品等を
覆うように絶縁塗料5および導電性ペーストによる導電
性膜6を形成したものであり、部品の外来ノイズの影響
を軽減できる。
FIG. 5 shows a third embodiment of the present invention. In contrast to the first embodiment, a conductive film made of an insulating paint 5 and a conductive paste is formed to cover the parts (devices) 7 after installation is completed. 6, which can reduce the effects of external noise on the components.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明のプリント配線基板によれ
ば、プリント配線基板完成後に、プリント配線基板の外
層に、絶縁塗料により絶縁膜を形成後、絶縁膜上に導電
性ペーストを面状に施し、熱処理によって遮蔽層を形成
したため、プリント配線基板の信号線間の干渉や外部か
らの静電誘導や電磁誘導ノイズを大幅に減少させ、かつ
、布線の配設・修正等を容易に行うことができた。
As explained above, according to the printed wiring board of the present invention, after the printed wiring board is completed, an insulating film is formed on the outer layer of the printed wiring board using an insulating paint, and then a conductive paste is applied in a planar manner on the insulating film. By forming a shielding layer through heat treatment, interference between signal lines on the printed wiring board and external electrostatic induction and electromagnetic induction noise can be significantly reduced, and wiring can be easily arranged and modified. was completed.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の第1の実施例を示す要部断面図。第2
図は本発明の詳細な説明するために多層プリント配線基
板を不平衡形ストリップラインとしてモデル化した説明
図。第3図は本発明の詳細な説明するために多層プリン
ト配線基板を平衡形ストリップラインとしてモデル化し
た説明図。第4図は本発明の第2の実施例を示す要部断
面図。第5図は本発明の第3の実施例を示す要部断面図
。第6図は従来のプリント配線基板の一例を示す要部断
面図である。 符号の説明 ■−・−一−−−・−プリプレグ(基板)2−・−・−
・−信号線を含む回路パターン層2°−一一一一・・信
号線を含む回路パターン層3−・−−−−−・−電源線
あるいは接地線の面パターン層4−−−−−・−・−ソ
ルダーレジスト5・−・−−−−−一−−絶縁塗料 6−・・・・−−一−−−導電性膜
FIG. 1 is a sectional view of essential parts showing a first embodiment of the present invention. Second
The figure is an explanatory diagram in which a multilayer printed wiring board is modeled as an unbalanced strip line in order to explain the present invention in detail. FIG. 3 is an explanatory diagram in which a multilayer printed wiring board is modeled as a balanced strip line for detailed explanation of the present invention. FIG. 4 is a sectional view of a main part showing a second embodiment of the present invention. FIG. 5 is a sectional view of main parts showing a third embodiment of the present invention. FIG. 6 is a sectional view of a main part of an example of a conventional printed wiring board. Explanation of symbols■−・−1−−−・−Prepreg (substrate) 2−・−・−
・-Circuit pattern layer including signal lines 2°-1111・・Circuit pattern layer 3 including signal lines・−−−−−・−Plane pattern layer 4 of power supply line or ground line−−−−−・−・−Solder resist 5・−・−−−−−1−−Insulating paint 6−・・−−1−−−Conductive film

Claims (1)

【特許請求の範囲】[Claims] (1)プリント配線基板完成後に、プリント配線基板の
外層に、絶縁塗料により絶縁膜を形成後、絶縁膜上に導
電性ペーストを面状に施し、熱処理によって遮蔽層を形
成したことを特徴とするプリント配線基板。
(1) After the printed wiring board is completed, an insulating film is formed on the outer layer of the printed wiring board using an insulating paint, a conductive paste is applied in a planar manner on the insulating film, and a shielding layer is formed by heat treatment. printed wiring board.
JP7128389A 1989-03-23 1989-03-23 Printed wiring board Pending JPH02249291A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7128389A JPH02249291A (en) 1989-03-23 1989-03-23 Printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7128389A JPH02249291A (en) 1989-03-23 1989-03-23 Printed wiring board

Publications (1)

Publication Number Publication Date
JPH02249291A true JPH02249291A (en) 1990-10-05

Family

ID=13456223

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7128389A Pending JPH02249291A (en) 1989-03-23 1989-03-23 Printed wiring board

Country Status (1)

Country Link
JP (1) JPH02249291A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005019582A (en) * 2003-06-25 2005-01-20 Sony Corp High-speed signal circuit board and method of improving signal transmission property thereof
JP2011040785A (en) * 1998-12-02 2011-02-24 Teradyne Inc Printed circuit board assembly
WO2011129299A1 (en) * 2010-04-15 2011-10-20 信越ポリマー株式会社 Printed wiring board and method of manufacturing thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011040785A (en) * 1998-12-02 2011-02-24 Teradyne Inc Printed circuit board assembly
JP2005019582A (en) * 2003-06-25 2005-01-20 Sony Corp High-speed signal circuit board and method of improving signal transmission property thereof
JP4496721B2 (en) * 2003-06-25 2010-07-07 ソニー株式会社 High speed signal circuit board and method for improving signal transmission characteristics thereof.
WO2011129299A1 (en) * 2010-04-15 2011-10-20 信越ポリマー株式会社 Printed wiring board and method of manufacturing thereof
JP2011228342A (en) * 2010-04-15 2011-11-10 Shin Etsu Polymer Co Ltd Printed wiring board and manufacturing method thereof
US9006581B2 (en) 2010-04-15 2015-04-14 Shin-Etsu Polymer Co., Ltd. Printed wiring board and method of manufacture thereof

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