JPH02249290A - Printed wiring board - Google Patents

Printed wiring board

Info

Publication number
JPH02249290A
JPH02249290A JP1071282A JP7128289A JPH02249290A JP H02249290 A JPH02249290 A JP H02249290A JP 1071282 A JP1071282 A JP 1071282A JP 7128289 A JP7128289 A JP 7128289A JP H02249290 A JPH02249290 A JP H02249290A
Authority
JP
Japan
Prior art keywords
copper foil
wiring board
printed wiring
line
prepreg
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1071282A
Other languages
Japanese (ja)
Inventor
Osamu Gunji
郡司 修
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP1071282A priority Critical patent/JPH02249290A/en
Publication of JPH02249290A publication Critical patent/JPH02249290A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0296Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298Multilayer circuits

Landscapes

  • Structure Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

PURPOSE:To sharply decrease interference between the signal lines of a printed wiring board and electrostatic induction and electromagnetic induction noises from the outside and facilitate installation and correction of a wiring by making the printed wiring board and then adhering conductors of copper foil, etc., having potential as low as the grounding or power source potential to the external layers of the printed wiring board. CONSTITUTION:Layer-shaped copper foil pattern layers 2 are formed on prepreg (substrates) 1. the copper foil pattern layers 2 construct circuit patterns including signal lines. A face pattern formed in one of copper foil layers 3 consisting of face patterns is made to be a power source line and the face pattern in the other copper foil layer is made to be a grounding line. After a wiring board is completed, the surfaces of the prepreg 1 are covered by copper foil faces 5 of the power source line and the grounding line.

Description

【発明の詳細な説明】 〔産業上の利用分野] 本発明はプリント配線基板に関し、特に、高周波回路基
板に好適なプリント配線基板に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a printed wiring board, and particularly to a printed wiring board suitable for a high frequency circuit board.

〔従来技術] 第7図は従来の多層プリント配線基板の一例を示したも
ので、同図に示すように、従来のプリント配線基板は、
絶縁層となるプリプレグ(基板本体〕1の表面に信号線
、電源線、接地線等の銅箔パターン層2°を形成してな
る。
[Prior Art] FIG. 7 shows an example of a conventional multilayer printed wiring board. As shown in the figure, the conventional printed wiring board has
A copper foil pattern layer 2° for signal lines, power lines, ground lines, etc. is formed on the surface of a prepreg (substrate body) 1 serving as an insulating layer.

この種のプリント配線基板は低周波の場合には、基板内
部から発生する電磁誘導等による信号線間の電磁結合が
比較的小さく問題とならないが、動作周波数が高周波(
VHF)になるにつれて信号線間の電磁結合が密となる
ため、互いの信号が干渉し合い、この信号干渉が回路誤
動作の原因となると言う問題があった。また、基板に遮
蔽層がないと、電磁誘導、静電誘導等の外来ノイズを受
は易いと言う問題もあり、導電性のシールドケース等を
取り付ける等の処理を施す必要がある。一方、実開昭5
0−11160号公報等に示されるように、基板に遮蔽
層を設けた構造も多数提案されているが、構成が複雑化
してコストアップする不都合がある。
With this type of printed wiring board, when the operating frequency is low, the electromagnetic coupling between the signal lines due to electromagnetic induction generated from inside the board is relatively small and does not pose a problem, but when the operating frequency is high (
Since the electromagnetic coupling between the signal lines becomes denser as the frequency becomes higher (VHF), there is a problem in that the signals interfere with each other, and this signal interference causes circuit malfunction. Furthermore, if the board does not have a shielding layer, there is a problem in that it is susceptible to external noise such as electromagnetic induction and electrostatic induction, so it is necessary to take measures such as attaching a conductive shielding case or the like. On the other hand, Jikai Showa 5
As shown in Japanese Patent No. 0-11160, many structures in which a shielding layer is provided on a substrate have been proposed, but these have the disadvantage of complicating the structure and increasing costs.

そこで、実開昭63−60330号(昭和63年5月7
日出ll1)として、基板表面に電源線や接地線を面パ
ターン状に形成したプリント配線基板を提案した。
Therefore, Utility Model No. 63-60330 (May 7, 1988)
As Hinode II1), we proposed a printed wiring board in which power lines and ground lines are formed in a planar pattern on the surface of the board.

が遮蔽効果を有するので、構成の複雑化、コストアップ
を抑えることができる。
has a shielding effect, so it is possible to suppress the complexity of the configuration and increase in cost.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、実開昭63−60330号では、電源線や接地
線が基板と一体になっており、信号線が基板の内部に形
成されているため、布線の修正等が困難となる等の問題
があった。
However, in Utility Model Application Publication No. 63-60330, the power line and ground line are integrated with the board, and the signal line is formed inside the board, which makes it difficult to modify the wiring. was there.

従って本発明の目的とするところは、プリント配線基板
の信号線間の干渉や外部からの静電誘導や電磁誘導ノイ
ズを大幅に減少させ、かつ、布線の配設・修正等を容易
に行えるプリント配線基板を提供することである。
Therefore, it is an object of the present invention to significantly reduce interference between signal lines on a printed wiring board, as well as external electrostatic induction and electromagnetic induction noise, and to facilitate wiring arrangement and modification. An object of the present invention is to provide a printed wiring board.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は前述した目的を実現するため、プリント配線基
板完成後に、プリント配線基板の外層に、接地電位ある
いは電源電位に落とした銅箔等の導電体を貼り合わせる
ようにしたプリント配線基板を提供するものである。
In order to achieve the above-mentioned object, the present invention provides a printed wiring board in which, after the printed wiring board is completed, a conductive material such as copper foil, which has been lowered to the ground potential or power supply potential, is bonded to the outer layer of the printed wiring board. It is something.

即ち、本発明のプリント配線基板は、多層プリント配線
基板の電源線や接地線等に接続した銅箔等の導電体を使
用し基板表面を面状に覆うことにより、信号線のインピ
ーダンスを下げ信号線間の電磁誘導による干渉を防止し
、かつ、基板の表面を電源電位や接地電位で覆う箔状の
導電体に遮蔽の役割を担わせ、誘導ノイズを大幅に減少
させるようにしたものである。前記導電体を基板完成後
に取付は可能とすることにより、布線の配設・修正等を
容易に行うことができる。
That is, the printed wiring board of the present invention lowers the impedance of the signal line by covering the surface of the board with a conductive material such as copper foil connected to the power line, ground line, etc. of the multilayer printed wiring board. This prevents interference due to electromagnetic induction between wires, and uses a foil-like conductor that covers the surface of the board with power supply potential and ground potential to play a shielding role, greatly reducing induced noise. . By making it possible to attach the conductor after the board is completed, it is possible to easily arrange and modify the wiring.

〔実施例〕〔Example〕

本発明の実施例を第1図〜第6図に基づき説明する。 Embodiments of the present invention will be described based on FIGS. 1 to 6.

第1図は本発明の第一の実施例を示す要部断面図である
。1は絶縁体よりなるプリプレグ(基板)で、プリプレ
グ1には層状の銅箔パターン層2が形成される。この銅
箔パターン層2は信号線を含む回路パターンを構成する
。3は面パターンで形成される銅箔層で、例えば、一方
に形成される面パターンが電源線となり、他方の面パタ
ーンが接地線となる。4は部品半田付部やスルーホール
等以外の部品の半田付時の半田付着防止を目的とするソ
ルダーレジストで電気的絶縁性を有する。5は基板完成
後に基板の外表面に貼り付けられる導電体(銅箔等)で
あり、電源線や接地線となり、前記電線線3.接地線3
に接続される。従って、電線線3.接地線3は、後述す
るように、特性インピーダンスを低下させる機能を有す
るが、外部遮蔽層としての機能を有する必要がないため
、図示したように内層部に設けることができる。プリプ
レグ1の表面は部品取付面や半田付面も兼ねる。
FIG. 1 is a sectional view of a main part showing a first embodiment of the present invention. Reference numeral 1 denotes a prepreg (substrate) made of an insulator, and a layered copper foil pattern layer 2 is formed on the prepreg 1. This copper foil pattern layer 2 constitutes a circuit pattern including signal lines. Reference numeral 3 denotes a copper foil layer formed in a plane pattern, for example, the plane pattern formed on one side becomes a power supply line, and the other plane pattern becomes a ground line. Reference numeral 4 is a solder resist that has electrical insulation properties and is intended to prevent solder adhesion during soldering of parts other than soldered parts and through holes. 5 is a conductor (copper foil, etc.) that is attached to the outer surface of the board after the board is completed, and serves as a power supply wire and a ground wire, and serves as the electric wire 3. Ground wire 3
connected to. Therefore, the electric wire 3. The grounding wire 3 has a function of lowering the characteristic impedance, as will be described later, but it does not need to have a function as an external shielding layer, so it can be provided in the inner layer portion as shown. The surface of the prepreg 1 also serves as a component mounting surface and a soldering surface.

このような構成によれば、第1にはプリプレグ1の内層
や外層に信号線2を配し、さらに、後述するように、プ
リプレグ1の表面を銅箔等で覆うことで信号線の特性イ
ンピーダンスを小さくすることができる。これを第2図
、第3図に基づいて説明すると次のようになる。
According to such a configuration, firstly, the signal line 2 is arranged on the inner layer or outer layer of the prepreg 1, and furthermore, as described later, the characteristic impedance of the signal line is reduced by covering the surface of the prepreg 1 with copper foil or the like. can be made smaller. This will be explained as follows based on FIGS. 2 and 3.

第2図および第3図は、本実施例の信号線2をストリッ
プラインとしてモデル化したもので、第2図は不平衡形
ストリップラインとしてのモデル、第3図は平衡形スト
リップラインとしてのモデルを表す。一般に、第2図の
モデルではストリップラインの特性インピーダンスZ0
は(1)式で表される。
2 and 3 model the signal line 2 of this embodiment as a stripline. FIG. 2 is a model as an unbalanced stripline, and FIG. 3 is a model as a balanced stripline. represents. Generally, in the model shown in Figure 2, the characteristic impedance of the stripline Z0
is expressed by equation (1).

ここでHrはプリプレグ1の実効誘電率、Wは信号線等
をストリップラインとみなした時の導体幅。
Here, Hr is the effective dielectric constant of the prepreg 1, and W is the conductor width when a signal line etc. is regarded as a strip line.

Tは信号線等をストリップラインとみなした時の導体厚
、Hは不平衡形ストリップラインのプリプレグ1の厚さ
である。
T is the conductor thickness when a signal line or the like is regarded as a strip line, and H is the thickness of the prepreg 1 of the unbalanced strip line.

一方、第3図の平衡形ストリップラインのモデルでは、
特性インピーダンスZ0は(2)式で表される。
On the other hand, in the balanced strip line model shown in Figure 3,
Characteristic impedance Z0 is expressed by equation (2).

ここで、Lは平衡形ストリップラインのプリプレグ1の
厚さである。(1)式、(2)式から信号線を含む回路
パターン2をプリプレグ1の内・外層に形成し、電源線
3.接地線3を配置し、さらに、面状銅箔5で覆うこと
により特性インピーダンスを小さくできる。その結果、
誘導される電圧が小さくなり信号間の電磁干渉を防止す
ることができる。
Here, L is the thickness of the prepreg 1 of the balanced stripline. From formulas (1) and (2), a circuit pattern 2 including signal lines is formed on the inner and outer layers of the prepreg 1, and a power supply line 3. By arranging the grounding wire 3 and further covering it with the planar copper foil 5, the characteristic impedance can be reduced. the result,
The induced voltage is reduced, and electromagnetic interference between signals can be prevented.

前述したように、プリプレグlの表面を電源線や接地線
等の銅箔面5で覆うために、この面が静電遮蔽の役割を
なし、外来ノイズに対する遮蔽や内部から発するノイズ
の遮蔽効果が改善される。
As mentioned above, since the surface of the prepreg l is covered with the copper foil surface 5 for the power supply line, grounding line, etc., this surface plays the role of electrostatic shielding, and has the effect of shielding against external noise and the noise emitted from inside. Improved.

また、銅箔面5は外部に貼り付けられるために、希望す
る遮蔽効果に応じて銅箔面5の厚さ(電気抵抗)等を変
えることができる。従って、本実施例によれば、高信頼
性のプリント配線基板の製作が可能である。
Further, since the copper foil surface 5 is attached to the outside, the thickness (electrical resistance) etc. of the copper foil surface 5 can be changed depending on the desired shielding effect. Therefore, according to this embodiment, it is possible to manufacture a highly reliable printed wiring board.

第4図は本発明の第2の実施例を示すもので、本実施例
はプリプレグ1の内層に信号線等の銅箔パターン層2を
複数層形成する他に、各銅箔パターン層2の上下に電源
線あるいは接地線の面パターン銅箔層3を配したもので
、さらに、基板完成後、電源線や接地線等の銅箔面5で
覆ったものである。この実施例は第1の実施例より更に
インピーダンスを低くすることが可能でより高信頼性を
有する多層プリント配線基板を提供することができる。
FIG. 4 shows a second embodiment of the present invention. In this embodiment, in addition to forming a plurality of copper foil pattern layers 2 such as signal lines on the inner layer of the prepreg 1, each copper foil pattern layer 2 is A surface pattern copper foil layer 3 of a power supply line or a ground line is disposed on the top and bottom, and after the board is completed, it is covered with a copper foil surface 5 of a power supply line or a ground line. This embodiment can lower impedance even further than the first embodiment, and can provide a multilayer printed wiring board with higher reliability.

第5図は本発明の第3の実施例を示すもので第1の実施
例に対し、電源線や接地超等の銅箔面5をプラスチック
シートに導電箔をラミネートしたラミネートテープ6に
置き換えたもので信号線とのショートを防止することが
できる。この構成によれば、ラミネートされる導電箔は
面状になっているが、回路パターン2に応じたパターン
にすることもできる。
FIG. 5 shows a third embodiment of the present invention, in which the copper foil surface 5 of the power supply line, grounding conductor, etc. is replaced with a laminate tape 6 made by laminating a conductive foil onto a plastic sheet, in contrast to the first embodiment. This can prevent short circuits with signal lines. According to this configuration, the conductive foil to be laminated has a planar shape, but it can also be patterned in accordance with the circuit pattern 2.

第6図は第5図に対し、部品(デバイス)7の取付完了
後に部品等を覆うようにラミネートテープ6を取付けた
ものであり、部品の外来ノイズの影響を軽減できる。以
上の実施例において、ラミネートテープを用いるものは
、ラミネートテープをスパイラル巻、縦沿え巻きし、そ
の重合面をヒートシールするだけで良いので簡単に製造
することができる。
In FIG. 6, in contrast to FIG. 5, a laminate tape 6 is attached to cover the components (devices) 7 after the attachment of the components (devices) 7 is completed, so that the influence of external noise on the components can be reduced. In the above embodiments, those using a laminate tape can be easily manufactured by simply spirally winding the laminate tape, vertically winding the tape, and heat-sealing the overlapping surfaces.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明のプリント配線基板によれ
ば、プリント配線基板完成後に、プリント配線基板の外
層に、接地電位あるいは電源電位に落とした銅箔等の導
電体を貼り合わせるようにしたため、プリント配線基板
の信号線間の干渉や外部からの静電誘導や電磁誘導ノイ
ズを大幅に減少させ、かつ、布線の配設・修正等を容易
に行えるようにできた。
As explained above, according to the printed wiring board of the present invention, after the printed wiring board is completed, a conductive material such as copper foil, which has been lowered to the ground potential or power supply potential, is attached to the outer layer of the printed wiring board. Interference between signal lines on printed wiring boards and external electrostatic induction and electromagnetic induction noise have been significantly reduced, and wiring can be easily installed and modified.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の第1の実施例を示す要部断面図。第2
図は本発明の詳細な説明するために多層プリント配線基
板を不平衡形ストリップラインとしてモデル化した説明
図。第3図は本発明の詳細な説明するために多層プリン
ト配線基板を平衡形ストリップラインとしてモデル化し
た説明図。第4図は本発明の第2の実施例を示す要部断
面図。第5図は本発明の第3の実施例を示す要部断面図
。第6図は本発明の第4の実施例を示す要部断面図。第
7図は従来のプリント配線基板の一例を示す要部断面図
である。 符号の説明
FIG. 1 is a sectional view of essential parts showing a first embodiment of the present invention. Second
The figure is an explanatory diagram in which a multilayer printed wiring board is modeled as an unbalanced strip line in order to explain the present invention in detail. FIG. 3 is an explanatory diagram in which a multilayer printed wiring board is modeled as a balanced strip line for detailed explanation of the present invention. FIG. 4 is a sectional view of a main part showing a second embodiment of the present invention. FIG. 5 is a sectional view of main parts showing a third embodiment of the present invention. FIG. 6 is a sectional view of a main part showing a fourth embodiment of the present invention. FIG. 7 is a sectional view of a main part of an example of a conventional printed wiring board. Explanation of symbols

Claims (1)

【特許請求の範囲】[Claims] (1)プリント配線基板完成後に、プリント配線基板の
外層に、接地電位あるいは電源電位に落とした銅箔等の
導電体を貼り合わせたことを特徴とするプリント配線基
板。
(1) A printed wiring board characterized in that, after the printed wiring board is completed, a conductor such as copper foil, which is at ground potential or power supply potential, is bonded to the outer layer of the printed wiring board.
JP1071282A 1989-03-23 1989-03-23 Printed wiring board Pending JPH02249290A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1071282A JPH02249290A (en) 1989-03-23 1989-03-23 Printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1071282A JPH02249290A (en) 1989-03-23 1989-03-23 Printed wiring board

Publications (1)

Publication Number Publication Date
JPH02249290A true JPH02249290A (en) 1990-10-05

Family

ID=13456195

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1071282A Pending JPH02249290A (en) 1989-03-23 1989-03-23 Printed wiring board

Country Status (1)

Country Link
JP (1) JPH02249290A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5563773A (en) * 1991-11-15 1996-10-08 Kabushiki Kaisha Toshiba Semiconductor module having multiple insulation and wiring layers

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5563773A (en) * 1991-11-15 1996-10-08 Kabushiki Kaisha Toshiba Semiconductor module having multiple insulation and wiring layers

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