JPH0786754A - Laminated hybrid integrated circuit component - Google Patents

Laminated hybrid integrated circuit component

Info

Publication number
JPH0786754A
JPH0786754A JP5253810A JP25381093A JPH0786754A JP H0786754 A JPH0786754 A JP H0786754A JP 5253810 A JP5253810 A JP 5253810A JP 25381093 A JP25381093 A JP 25381093A JP H0786754 A JPH0786754 A JP H0786754A
Authority
JP
Japan
Prior art keywords
laminated
component
land
semiconductor component
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP5253810A
Other languages
Japanese (ja)
Inventor
Nobunori Mochizuki
宣典 望月
Chisato Manome
千里 馬目
Masashi Orihara
正志 折原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Corp
Original Assignee
TDK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TDK Corp filed Critical TDK Corp
Priority to JP5253810A priority Critical patent/JPH0786754A/en
Publication of JPH0786754A publication Critical patent/JPH0786754A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

PURPOSE:To provide a multilayered hybrid integrated circuit component having a means for protecting malfunction of a mounted semiconductor component, by reducing the noise generated by the action of a laminated inductor or a laminated capacitor and a land. CONSTITUTION:A laminated inductor 1A wherein a transformer is formed by alternately laminating insulator layers 2 and conductive layers 3 is constituted. A laminated capacitor is laminated on the laminated inductor 1A, or individually consituted as a capacitor formed by alternately laminating dielectric layers and electrode layers. A semiconductor component 8 is mounted on the above laminated component. A shield layer 15 is formed interposing an insulator layer 16 under a land 7 with which the lead 9 of the semiconductor component 8 and/or a land with which other constituent components relative to the semiconductor components are connected. Further a shield layer 15 may be formed under a resistance layer connected directly or indirectly with the semiconductor component 8.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、積層型インダクタ(本
明細書では内部にインダクタを積層構造により形成した
もののみならず、トランスのみまたはトランスとインダ
クタの双方を積層構造により形成したものも積層型イン
ダクタと称することとする)と積層型コンデンサの少な
くともいずれか一方でなる積層部品を基板とし、該基板
上に半導体部品を搭載してなる積層型混成集積回路部品
に係り、特に例えばDC−DCコンバータに用いられる
もののように、積層部品内部からの漏洩磁束等により半
導体部品のリードに載る微弱ノイズにより半導体部品が
誤動作するおそれがある場合におけるノイズ防止構造に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated inductor (in this specification, not only one having an inductor internally formed by a laminated structure, but also one having only a transformer or both a transformer and an inductor formed by a laminated structure are laminated. Type inductor) and a multilayer capacitor as a substrate, and a multilayer hybrid integrated circuit component in which a semiconductor component is mounted on the substrate, and particularly, for example, DC-DC The present invention relates to a noise prevention structure in a case where a semiconductor component may malfunction due to a weak noise placed on a lead of the semiconductor component due to a leakage magnetic flux from the inside of the laminated component, such as that used in a converter.

【0002】[0002]

【従来の技術】図4(A)は従来の積層型混成集積回路
の一例を示す斜視図であり、DC−DCコンバータに使
用されるものである。1Aはインダクタあるいはトラン
スを内部に構成した積層部品であり、該積層部品1Aは
例えば図4(B)に示すように、磁性フェライトのよう
な磁性体層2とコイルとなる導体層3とが印刷法やシー
ト法により例えば特開昭60−244097号公報にお
いて開示した方法により積層、焼成して内部に1以上の
インダクタ4(またはトランス)を構成し、側面に外部
電極5を焼き付けやメッキにより形成して積層型インダ
クタからなる積層部品1Aを構成する。該積層部品1A
を基板としても利用するため、絶縁層6を表面または表
裏面に形成し、その上に一部が前記外部電極5に接続さ
れるランド7等を含む配線パターンを必要に応じて設け
られる抵抗層と共に形成し、その上にDC−DCコンバ
ータの場合にはスイッチング素子や増幅回路等を構成す
る樹脂モールドした半導体部品8等の電子部品を、その
リード9を前記ランド7に半田付けや導電性樹脂による
接着等によって固定することにより搭載し、混成集積回
路部品を構成する。
2. Description of the Related Art FIG. 4A is a perspective view showing an example of a conventional laminated hybrid integrated circuit, which is used in a DC-DC converter. Reference numeral 1A denotes a laminated component in which an inductor or a transformer is formed, and the laminated component 1A is printed with a magnetic layer 2 such as magnetic ferrite and a conductor layer 3 serving as a coil as shown in FIG. 4B. Method or sheet method, for example, the method disclosed in Japanese Patent Laid-Open No. 60-244097 is laminated and fired to form one or more inductors 4 (or transformers) inside, and external electrodes 5 are formed on the side surfaces by baking or plating. Then, the laminated component 1A including the laminated inductor is configured. The laminated component 1A
In order to utilize as a substrate, a resistance layer in which an insulating layer 6 is formed on the front surface or the front and back surfaces, and a wiring pattern including a land 7 or the like partially connected to the external electrode 5 is provided on the resistance layer 6 as necessary. And a resin-molded electronic component such as a semiconductor component 8 which forms a switching element, an amplifier circuit or the like in the case of a DC-DC converter, and its lead 9 is soldered to the land 7 or a conductive resin. It is mounted by being fixed by adhesion or the like to form a hybrid integrated circuit component.

【0003】図5は他の例の積層部品1Bに半導体部品
8を搭載したもので、誘電体層10と内部電極11とを
前記と同様の方法で積層して1以上のコンデンサ12を
構成するものである。
FIG. 5 shows another example of a laminated component 1B on which a semiconductor component 8 is mounted. A dielectric layer 10 and internal electrodes 11 are laminated in the same manner as described above to form one or more capacitors 12. It is a thing.

【0004】[0004]

【発明が解決しようとする課題】図4に示した従来の積
層型混成集積回路部品においては、特にトランスを構成
するものの場合、トランスで発生した磁束Φの一部が漏
れてランド7と鎖交し、電磁誘導作用によってランド7
にノイズとして信号が載り、半導体部品8の誤動作を引
き起こすことがあるという問題点があった。また、図5
に示す場合においても、コンデンサ12の最上層の電極
11とランド7との間の静電誘導により信号のランド7
への漏れを生じて半導体部品8の誤動作を生じるおそれ
があるという問題点があった。
In the conventional laminated type hybrid integrated circuit component shown in FIG. 4, particularly in the case where a transformer is formed, a part of the magnetic flux Φ generated in the transformer leaks and is interlinked with the land 7. The land 7 by the electromagnetic induction action.
However, there is a problem in that a signal may be added as noise to cause malfunction of the semiconductor component 8. Also, FIG.
Also in the case shown in (1), signal land 7 is generated by electrostatic induction between uppermost electrode 11 of capacitor 12 and land 7.
There is a problem in that the semiconductor component 8 may malfunction due to the leakage to the semiconductor component 8.

【0005】本発明は、上述のような積層型混成集積回
路部品において、積層インダクタまたは積層コンデンサ
とランドとの作用により発生するノイズを低減すること
により、搭載半導体部品の誤動作を防止する手段を有す
る積層型混成集積回路部品を提供することを目的とす
る。
The present invention has means for preventing malfunction of the mounted semiconductor component by reducing noise generated by the action of the laminated inductor or laminated capacitor and the land in the laminated hybrid integrated circuit component as described above. An object is to provide a laminated hybrid integrated circuit component.

【0006】[0006]

【課題を解決するための手段】本発明は、上記目的を達
成するため、絶縁体層と導体層との交互積層により1以
上のインダクタまたはトランスの少なくともいずれかが
形成された積層型インダクタおよび/または誘電体層と
導体層との交互積層により1以上のコンデンサが形成さ
れた積層型コンデンサからなる積層部品上に、半導体部
品を搭載した積層型混成集積回路部品において、前記半
導体部品のリードが接続されるランドおよび/または該
半導体部品に関連した他の構成部品が接続されるランド
の下部に、あるいはさらに該半導体部品に直接的または
間接的に接続される抵抗層の下部に絶縁層を挟んでシー
ルド層を設けたことを特徴とする。
In order to achieve the above-mentioned object, the present invention provides a laminated inductor and / or one or more inductors or transformers formed by alternately laminating an insulator layer and a conductor layer. Alternatively, in a laminated hybrid integrated circuit component in which a semiconductor component is mounted on a laminated component composed of a laminated capacitor in which one or more capacitors are formed by alternately laminating dielectric layers and conductor layers, the leads of the semiconductor component are connected. An insulating layer under a land to which the semiconductor component and / or other components related to the semiconductor component are connected, or further below a resistance layer directly or indirectly connected to the semiconductor component. It is characterized in that a shield layer is provided.

【0007】[0007]

【作用】本発明によれば、積層インダクタの漏洩磁束は
ランド等の下部に形成したシールド層によりランドへの
到達分が減少するかあるいは無くなり、これによりノイ
ズを低減し、半導体部品等の誤動作を防止できる。ま
た、積層コンデンサ上に半導体部品を搭載したものにお
いては、内部電極とランド等との間にシールド層が介在
することになり、同様に内部電極とランドとの間に静電
誘導により発生するノイズが低減される。
According to the present invention, the leakage magnetic flux of the laminated inductor is reduced or eliminated by reaching the land by the shield layer formed under the land, thereby reducing noise and preventing malfunction of semiconductor parts and the like. It can be prevented. Also, in the case where a semiconductor component is mounted on the multilayer capacitor, a shield layer is interposed between the internal electrode and the land, and similarly noise generated by electrostatic induction is generated between the internal electrode and the land. Is reduced.

【0008】[0008]

【実施例】図1(A)は本発明による積層型混成集積回
路部品の一実施例を示す断面図であり、図4(B)に対
応させて描いた図である。14は前記積層インダクタ1
Aの上に形成されたガラス等からなる絶縁層、15は該
絶縁層14上の、前記ランド7の下部に相当する箇所に
形成された銀、銀−パラジウム、銅、金等からなるシー
ルド層、16は該シールド層15および前記絶縁層14
上に重ねて形成した絶縁層、7は同様のシールド層15
と同様または異なる材質でなるランドであり、これらは
印刷法やシールド法によりインダクタ1A上に積層して
形成する。このように、これらの層を積層し焼成した
後、外部電極5を焼き付けやメッキにより形成する。該
絶縁層16上には前記ランド7の基層となる銀、銀−パ
ラジウム、銅、金を印刷、シート法等により形成した
後、その上にニッケル層、Sn等の半田付け層を順次積
層して形成する。なお、実施例においては、製品として
の絶縁層14、16の厚みは約20μm程度とし、シー
ルド層15やランド7の基層の厚みは約5μm程度とし
た。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1A is a sectional view showing an embodiment of a laminated hybrid integrated circuit component according to the present invention and is a drawing corresponding to FIG. 4B. 14 is the laminated inductor 1
An insulating layer made of glass or the like formed on A, and a shield layer 15 made of silver, silver-palladium, copper, gold or the like formed on the insulating layer 14 at a position corresponding to the lower portion of the land 7. , 16 are the shield layer 15 and the insulating layer 14
Insulating layer formed overlying, 7 is a similar shield layer 15
And lands made of the same material as or different from the above, and these are formed by laminating on the inductor 1A by a printing method or a shield method. In this way, after these layers are laminated and fired, the external electrode 5 is formed by baking or plating. After forming silver, silver-palladium, copper, and gold, which will be the base layer of the land 7, by a printing method, a sheet method or the like on the insulating layer 16, a nickel layer and a soldering layer such as Sn are sequentially laminated thereon. To form. In the embodiment, the thickness of the insulating layers 14 and 16 as products is about 20 μm, and the thickness of the shield layer 15 and the base layer of the land 7 is about 5 μm.

【0009】このような構造とすれば、インダクタ4ま
たはトランスにおいて発生した磁束Φの一部の漏洩磁束
がランド7に到達する前にシールド層15と鎖交して渦
電流として消費されるので、ランド7にほとんど到達し
なくなり、漏洩磁束の作用によるノイズがリード9に載
ることが防止され、半導体部品8の誤動作が防止され
る。
With this structure, a part of the leakage flux of the magnetic flux Φ generated in the inductor 4 or the transformer is linked with the shield layer 15 before reaching the land 7, and is consumed as an eddy current. The land 7 is hardly reached, noise due to the action of the leakage magnetic flux is prevented from being placed on the lead 9, and malfunction of the semiconductor component 8 is prevented.

【0010】図1(B)は本発明の他の実施例であり、
前記絶縁層16上に半導体部品8に接続される抵抗層1
7を形成した回路を有する場合、ランド7から抵抗層1
7ないしは抵抗層17が接続されたランド18にわたっ
てこれらの下部にシールド層15を形成したものであ
り、このような構成とすれば、抵抗層17において漏洩
磁束による電磁誘導によって発生したノイズが半導体部
品8に達して半導体部品8が誤動作することが防止され
る。なお、図示のように、抵抗層17がリード9に直接
的に接続される場合のみならず、他の部品を介して接続
され、信号の伝播があって半導体部品8が誤動作するお
それがある場合には必要に応じて抵抗層17の下部にシ
ールド層15を設ける。
FIG. 1B shows another embodiment of the present invention.
A resistance layer 1 connected to the semiconductor component 8 on the insulating layer 16
7 has a circuit in which the resistor 7 is formed from the land 7 to the resistance layer 1.
7 or the land 18 to which the resistance layer 17 is connected, the shield layer 15 is formed under these, and with this structure, noise generated in the resistance layer 17 by electromagnetic induction due to leakage magnetic flux is a semiconductor component. 8 to prevent the semiconductor component 8 from malfunctioning. In addition, as shown in the drawing, not only when the resistance layer 17 is directly connected to the lead 9, but also when the resistance layer 17 is connected through another component and there is a possibility that the semiconductor component 8 malfunctions due to signal propagation. In this case, the shield layer 15 is provided below the resistance layer 17 as necessary.

【0011】図2(A)は半導体部品8に関連するダイ
オード、トタンジスタ等の他の構成部品20を備えたも
のにおいて、ランド7から他の構成部品20のリード2
1を固定するランド22にわたり、これらの下部にシー
ルド層15を設けた本発明の他の実施例であり、この実
施例によれば、他の構成部品20搭載用ランド22に漏
洩磁束による電磁誘導によってノイズが載ることが防止
され、半導体部品8の誤動作が防止される。なお、内部
のインダクタ4またはトランスとリード9、21の配置
によっては、漏洩磁束による影響が大きいランド7の下
部のみあるいはランド22の下部のみにシールド層15
を設けてもよい。また、図1(B)に示したように、抵
抗層17がさらに形成される場合には、抵抗層17の下
部にもシールド層15をさらに設けてもよい。
FIG. 2A shows a semiconductor component 8 including another component 20 such as a diode and a transistor, which is related to the semiconductor component 8. In FIG.
1 is another embodiment of the present invention in which a shield layer 15 is provided below the lands 22 for fixing 1 and, according to this embodiment, electromagnetic induction due to a leakage magnetic flux is applied to another component 20 mounting land 22. This prevents noise from being carried and prevents malfunction of the semiconductor component 8. Depending on the arrangement of the internal inductor 4 or transformer and the leads 9 and 21, only the lower part of the land 7 or the lower part of the land 22 where the influence of the leakage magnetic flux is large is provided.
May be provided. Further, as shown in FIG. 1B, when the resistance layer 17 is further formed, the shield layer 15 may be further provided below the resistance layer 17.

【0012】図2(B)は積層型コンデンサからなる積
層部品1B上に半導体部品8が搭載されたものに本発明
を適用した実施例であり、図1(A)の実施例と同様に
ランド7の下部にシールド層15を設けたものであっ
て、コンデンサ12の電極11とランド7との静電誘導
によってランド7にノイズが載ることが防止され、半導
体部品8の誤動作が防止される。
FIG. 2 (B) shows an embodiment in which the present invention is applied to a semiconductor component 8 mounted on a laminated component 1B composed of a multilayer capacitor. As in the embodiment shown in FIG. 7, a shield layer 15 is provided below the electrode 7, noise is prevented from being placed on the land 7 due to electrostatic induction between the electrode 11 of the capacitor 12 and the land 7, and malfunction of the semiconductor component 8 is prevented.

【0013】図3は内部にインダクタ4あるいはトラン
スを形成した積層型インダクタと内部にコンデンサ12
を形成した積層型コンデンサとを一体化した積層部品1
Cに半導体部品8を搭載したものに本発明を適用した実
施例である。図示のように積層型インダクタが上(半導
体部品8の搭載面)、積層型コンデンサが下となるもの
においても、その反対に積層型コンデンサが上、積層型
インダクタが下になるものにおいても、前記実施例の説
明から明らかなように半導体部品8の誤動作が防止され
る。
FIG. 3 shows a laminated inductor having an inductor 4 or a transformer formed therein and a capacitor 12 inside.
Multilayered component 1 integrated with multilayer capacitor
This is an example in which the present invention is applied to a semiconductor component 8 mounted on C. In the case where the multilayer inductor is on the top (mounting surface of the semiconductor component 8) and the multilayer capacitor is on the bottom as shown in the figure, on the contrary, the multilayer capacitor is on the top and the multilayer inductor is on the bottom, As is clear from the description of the embodiment, the malfunction of the semiconductor component 8 is prevented.

【0014】上記実施例においては、ランド7等の下部
のみに浮島状にシールド層15を設けたが、積層部品1
A〜1Cの周囲を除いてほぼ全面にシールド層15を形
成してもよく、また、シールド層15をグランドパター
ンに接続してもよい。また、インダクタ4としては磁性
体2ではなく、用途によっては非磁性体を用いる場合も
ある。
In the above embodiment, the shield layer 15 is provided in the form of a floating island only under the land 7 etc.
The shield layer 15 may be formed on almost the entire surface except the periphery of A to 1C, and the shield layer 15 may be connected to the ground pattern. The inductor 4 may be a non-magnetic material instead of the magnetic material 2 depending on the application.

【0015】[0015]

【発明の効果】請求項1によれば、前記半導体部品およ
び/または他の構成部品搭載用ランドの下部に絶縁層を
挟んでシールド層を設けたので、漏洩磁束による電磁誘
導あるいは静電誘導によってランドにノイズが載ること
が防止され、半導体部品の誤動作が防止される。
According to the first aspect of the present invention, the shield layer is provided below the semiconductor component and / or other component mounting land with the insulating layer interposed therebetween. It is possible to prevent noise from landing on the land, and prevent malfunction of semiconductor components.

【0016】請求項2によれば、抵抗層の下部にもシー
ルド層を設けたことにより、抵抗層にノイズが載ること
による半導体部品の誤動作も防止できる。
According to the second aspect, since the shield layer is also provided under the resistance layer, it is possible to prevent malfunction of the semiconductor component due to noise on the resistance layer.

【図面の簡単な説明】[Brief description of drawings]

【図1】(A)は本発明による積層型混成集積回路部品
の一実施例を示す断面図、(B)は本発明の他の実施例
を示す断面図である。
1A is a sectional view showing an embodiment of a laminated hybrid integrated circuit component according to the present invention, and FIG. 1B is a sectional view showing another embodiment of the present invention.

【図2】(A)、(B)はそれぞれ本発明の他の実施例
をさらに示す断面図である。
2A and 2B are cross-sectional views each showing another embodiment of the present invention.

【図3】本発明の他の実施例をさらに示す断面図であ
る。
FIG. 3 is a sectional view further showing another embodiment of the present invention.

【図4】(A)は従来の積層型混成集積回路部品の一実
施例を示す斜視図、(B)はその断面図である。
4A is a perspective view showing an embodiment of a conventional laminated hybrid integrated circuit component, and FIG. 4B is a sectional view thereof.

【図5】従来の積層型混成集積回路部品の他の例を示す
断面図である。
FIG. 5 is a cross-sectional view showing another example of a conventional laminated hybrid integrated circuit component.

【符号の説明】[Explanation of symbols]

1A 積層型インダクタ 1B 積層型コンデンサ 1C インダクタとコンデンサを重ねた積層部品 2 磁性体層 3 導体層 4 インダクタ 5 外部電極 7、18、22 ランド 8 半導体部品 9、21 リード 10 誘電体層 11 内部電極 12 コンデンサ 14、16 絶縁層 15 シールド層 17 抵抗層 20 他の構成部品 1A Multilayer Inductor 1B Multilayer Capacitor 1C Multilayer Component Including Inductor and Capacitor 2 Magnetic Layer 3 Conductor Layer 4 Inductor 5 External Electrode 7, 18, 22 Land 8 Semiconductor Component 9, 21 Lead 10 Dielectric Layer 11 Internal Electrode 12 Capacitors 14 and 16 Insulating layer 15 Shield layer 17 Resistive layer 20 Other components

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】絶縁体層と導体層との交互積層により1以
上のインダクタまたはトランスの少なくともいずれかが
形成された積層型インダクタおよび/または誘電体層と
導体層との交互積層により1以上のコンデンサが形成さ
れた積層型コンデンサからなる積層部品上に、半導体部
品を搭載した積層型混成集積回路部品において、 前記半導体部品のリードが接続されるランドおよび/ま
たは該半導体部品に関連した他の構成部品が接続される
ランドの下部に、絶縁層を挟んでシールド層を設けたこ
とを特徴とする積層型混成集積回路部品。
1. A laminated inductor in which at least one inductor or transformer is formed by alternately laminating an insulating layer and a conductor layer, and / or one or more layers by alternately laminating a dielectric layer and a conductor layer. In a laminated hybrid integrated circuit component in which a semiconductor component is mounted on a laminated component formed of a laminated capacitor in which a capacitor is formed, a land to which a lead of the semiconductor component is connected and / or another configuration related to the semiconductor component A laminated hybrid integrated circuit component, characterized in that a shield layer is provided below the land to which the component is connected, with an insulating layer interposed therebetween.
【請求項2】請求項1において、前記半導体部品に接続
される抵抗層の下部にも絶縁層を挟んでシールド層を設
けたことを特徴とする積層型混成集積回路部品。
2. The laminated hybrid integrated circuit component according to claim 1, further comprising a shield layer provided below the resistance layer connected to the semiconductor component with an insulating layer interposed therebetween.
JP5253810A 1993-09-16 1993-09-16 Laminated hybrid integrated circuit component Withdrawn JPH0786754A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5253810A JPH0786754A (en) 1993-09-16 1993-09-16 Laminated hybrid integrated circuit component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5253810A JPH0786754A (en) 1993-09-16 1993-09-16 Laminated hybrid integrated circuit component

Publications (1)

Publication Number Publication Date
JPH0786754A true JPH0786754A (en) 1995-03-31

Family

ID=17256465

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5253810A Withdrawn JPH0786754A (en) 1993-09-16 1993-09-16 Laminated hybrid integrated circuit component

Country Status (1)

Country Link
JP (1) JPH0786754A (en)

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JP2006216769A (en) * 2005-02-03 2006-08-17 Sony Corp Semiconductor device and its fabrication process
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JP2007173713A (en) * 2005-12-26 2007-07-05 Hitachi Metals Ltd Component with built-in inductor, and dc-dc converter using same
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WO2011148678A1 (en) * 2010-05-26 2011-12-01 株式会社 村田製作所 Lc co-sintered substrate and method for producing same
WO2012137386A1 (en) * 2011-04-06 2012-10-11 株式会社村田製作所 Laminated-type inductor element and method of manufacturing thereof
WO2012140805A1 (en) * 2011-04-11 2012-10-18 株式会社村田製作所 Laminated inductor element and method for manufacturing same
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Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006216769A (en) * 2005-02-03 2006-08-17 Sony Corp Semiconductor device and its fabrication process
EP1761118A1 (en) * 2005-09-01 2007-03-07 Ngk Spark Plug Co., Ltd Wiring board and capacitor
US7742314B2 (en) 2005-09-01 2010-06-22 Ngk Spark Plug Co., Ltd. Wiring board and capacitor
JP2007173713A (en) * 2005-12-26 2007-07-05 Hitachi Metals Ltd Component with built-in inductor, and dc-dc converter using same
JP2008084921A (en) * 2006-09-26 2008-04-10 Kyocera Corp Substrate with built-in coil
WO2011148678A1 (en) * 2010-05-26 2011-12-01 株式会社 村田製作所 Lc co-sintered substrate and method for producing same
JPWO2012137386A1 (en) * 2011-04-06 2014-07-28 株式会社村田製作所 Multilayer inductor element and manufacturing method thereof
WO2012137386A1 (en) * 2011-04-06 2012-10-11 株式会社村田製作所 Laminated-type inductor element and method of manufacturing thereof
US9129733B2 (en) 2011-04-06 2015-09-08 Murata Manufacturing Co., Ltd. Laminated inductor element and manufacturing method thereof
JP5510554B2 (en) * 2011-04-06 2014-06-04 株式会社村田製作所 Multilayer inductor element and manufacturing method thereof
EP2698798A1 (en) * 2011-04-11 2014-02-19 Murata Manufacturing Co., Ltd. Laminated inductor element and method for manufacturing same
US8810352B2 (en) 2011-04-11 2014-08-19 Murata Manufacturing Co., Ltd. Laminated inductor element and manufacturing method thereof
EP2698798A4 (en) * 2011-04-11 2014-09-03 Murata Manufacturing Co Laminated inductor element and method for manufacturing same
WO2012140805A1 (en) * 2011-04-11 2012-10-18 株式会社村田製作所 Laminated inductor element and method for manufacturing same
JP2014155265A (en) * 2013-02-06 2014-08-25 Fujitsu Telecom Networks Ltd Transformer wiring structure of dc-dc converter
WO2017018134A1 (en) * 2015-07-30 2017-02-02 株式会社村田製作所 Multilayer substrate and electronic device
US10374305B2 (en) 2015-07-30 2019-08-06 Murata Manufacturing Co., Ltd. Multilayer substrate and electronic device

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