JP2514430Y2 - Hybrid IC - Google Patents
Hybrid ICInfo
- Publication number
- JP2514430Y2 JP2514430Y2 JP1988020926U JP2092688U JP2514430Y2 JP 2514430 Y2 JP2514430 Y2 JP 2514430Y2 JP 1988020926 U JP1988020926 U JP 1988020926U JP 2092688 U JP2092688 U JP 2092688U JP 2514430 Y2 JP2514430 Y2 JP 2514430Y2
- Authority
- JP
- Japan
- Prior art keywords
- hybrid
- insulating sheet
- terminals
- base ribbon
- ribbon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Description
【考案の詳細な説明】 〔産業上の利用分野〕 本考案は小型で高密度、高信頼性のハイブリッドICに
関するものであり、特に搭載部品エリアの改善に関する
ものである。[Detailed Description of the Invention] [Industrial field of application] The present invention relates to a small, high-density, and highly reliable hybrid IC, and more particularly to improvement of a mounting component area.
近年、ハイブリッドICは、IC、トランジスタ、コンデ
ンサ、抵抗器、及びコイルを高密度に実装したものが増
加している。第２図は従来のハイブリッドICの樹脂封止
前の平面図である。第２図において11はベースリボン、
12はベースリボンの端子、13は表面を搭載部品エリアと
する絶縁シート、４は絶縁シート13上に形成されている
配線導体、５はICチップ、６はチップコンデンサ、７は
抵抗器であり、端子12と絶縁シート上の接続電極の間は
ボンディングワイヤ８によって接続されている。In recent years, the number of hybrid ICs in which an IC, a transistor, a capacitor, a resistor, and a coil are mounted at high density is increasing. FIG. 2 is a plan view of a conventional hybrid IC before resin sealing. In FIG. 2, 11 is a base ribbon,
12 is a terminal of the base ribbon, 13 is an insulating sheet whose surface is a mounting component area, 4 is a wiring conductor formed on the insulating sheet 13, 5 is an IC chip, 6 is a chip capacitor, 7 is a resistor, The terminals 12 and the connection electrodes on the insulating sheet are connected by the bonding wires 8.
上述した従来のハイブリッドICの搭載部品エリアは端
子部の内側であったために、搭載部品エリアは狭く、搭
載部品点数は非常に限られてしまうといった欠点があ
る。Since the mounted component area of the conventional hybrid IC described above is inside the terminal portion, the mounted component area is narrow and the number of mounted components is extremely limited.
上記問題点に対し本考案のハイブリッドICは、配線導
体が形成されかつ、能動および受動素子が搭載された絶
縁シートのほぼ全面がベースリボンに貼り付けられ、樹
脂封止されたハイブリッドICにおいて、前記ベースリボ
ンの端子は前記絶縁シート上の接続電極に直接接続され
ていると共に、接続相手のない端子は予め切り落とされ
ている。To solve the above problems, the hybrid IC of the present invention is a hybrid IC in which a wiring conductor is formed, and almost all the surface of an insulating sheet on which active and passive elements are mounted is attached to a base ribbon and the resin is sealed. The terminals of the base ribbon are directly connected to the connection electrodes on the insulating sheet, and the terminals without connection partners are cut off in advance.
次に、本考案を実施例により説明する。 Next, the present invention will be described with reference to examples.
第１図は本考案の一実施例の樹脂封止前のハイブリッ
ドICの平面図である。第１図において、１はベースリボ
ンで、ベースリボン平面よりディンプル加工で一段くぼ
ませてあるベースリボンの絶縁シート搭載部には、表面
に配線導体４が形成され、さらにICチップ５、チップコ
ンデンサ６、抵抗器７などが搭載された絶縁シート３の
裏面のほぼ全面が貼り付けられている。また、絶縁シー
ト３の縁辺にある接続電極には、ベースリボンの端子２
が直接接続されている。なお、ベースリボンの多数の端
子のうち、接続相手の接続電極が絶縁シート２上にない
ものは予め切落とされて、その分絶縁シートの搭載部品
エリアが広げられている。この場合、絶縁シート３にお
いては、切落とされるベースリボンの端子が絶縁シート
３のなるべく角の部分に一括して集まるように絶縁シー
ト上の接続電極の配線を考慮することにより、部品搭載
エリアが効率的に広げられるのはいうまでもない。な
お、ベースリボンの端子を絶縁シート３に接続後樹脂封
止され、さらに一体の端子は個々に切り離されて樹脂封
止のハイブリッドICが完成する。FIG. 1 is a plan view of a hybrid IC before resin encapsulation according to an embodiment of the present invention. In FIG. 1, reference numeral 1 is a base ribbon, and a wiring conductor 4 is formed on the surface of an insulating sheet mounting portion of the base ribbon, which is recessed by one step from the plane of the base ribbon by dimple processing. Almost the entire back surface of the insulating sheet 3 on which the resistors 7 and the like are mounted is attached. In addition, the connecting electrodes on the edge of the insulating sheet 3 are connected to the terminals 2 of the base ribbon.
Are directly connected. In addition, among the many terminals of the base ribbon, those in which the connection electrode of the connection partner is not on the insulating sheet 2 are cut off in advance, and the mounting component area of the insulating sheet is widened accordingly. In this case, in the insulating sheet 3, by considering the wiring of the connecting electrodes on the insulating sheet so that the terminals of the base ribbon to be cut off are collectively gathered at the corners of the insulating sheet 3, the component mounting area can be reduced. It goes without saying that it can be spread efficiently. The terminals of the base ribbon are connected to the insulating sheet 3 and then sealed with resin, and the integrated terminals are individually cut off to complete a resin-sealed hybrid IC.
以上説明したように本考案は、搭載部品エリアを大き
くし、直接端子部に接続することによって、搭載部品エ
リアが広くなり、また、端子部を一部切断することによ
り、さらに搭載部品エリアが広くなり搭載部品点数を増
やしている。よって、外形寸法を大きくせず搭載部品点
数を増やすことができ、さらに、従来の絶縁シートとベ
ースリボンの端子との間のボンディングワイヤををなく
したことにより、信頼性を一段と向上させることが出来
る効果がある。As described above, according to the present invention, the mounting component area is increased by directly connecting to the terminal portion, and the mounting component area is further enlarged by cutting a part of the terminal portion. The number of mounted parts is increasing. Therefore, it is possible to increase the number of mounted components without increasing the external dimensions, and further to improve reliability by eliminating the conventional bonding wire between the insulating sheet and the terminal of the base ribbon. effective.
第１図は本考案の一実施例の樹脂封止前の平面図、第２
図は従来のハイブリッドICの樹脂封止前の平面図であ
る。 １、11……ベースリボン、２、12……ベースリボンの端
子、３、13……絶縁シート、４……配線導体、５……IC
チップ、６……チップコンデンサ、７……抵抗器、８…
…ボンディングワイヤFIG. 1 is a plan view of an embodiment of the present invention before resin sealing, and FIG.
The figure is a plan view of a conventional hybrid IC before resin sealing. 1, 11 ... Base ribbon, 2, 12 ... Base ribbon terminals, 3, 13 ... Insulation sheet, 4 ... Wiring conductor, 5 ... IC
Chip, 6 ... Chip capacitor, 7 ... Resistor, 8 ...
… Bonding wire
Claims (1)
素子が搭載された絶縁シートのほぼ全面がベースリボン
に貼り付けられ、樹脂封止されたハイブリッドICにおい
て、前記ベースリボンの端子は前記絶縁シート上の接続
電極に直接接続されていると共に、接続相手のない端子
は予め切り落とされていることを特徴とするハイブリッ
ドIC。1. A hybrid IC in which a wiring conductor is formed, and substantially the entire surface of an insulating sheet on which active and passive elements are mounted is adhered to a base ribbon, and a resin-sealed hybrid IC has terminals of the base ribbon which are insulated from each other. A hybrid IC characterized in that it is directly connected to the connection electrodes on the sheet, and the terminals that have no connection partner are cut off in advance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988020926U JP2514430Y2 (en) | 1988-02-19 | 1988-02-19 | Hybrid IC |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988020926U JP2514430Y2 (en) | 1988-02-19 | 1988-02-19 | Hybrid IC |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01125573U JPH01125573U (en) | 1989-08-28 |
| JP2514430Y2 true JP2514430Y2 (en) | 1996-10-16 |
Family
ID=31237706
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988020926U Expired - Lifetime JP2514430Y2 (en) | 1988-02-19 | 1988-02-19 | Hybrid IC |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2514430Y2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01120856A (en) * | 1987-11-04 | 1989-05-12 | Sony Corp | Lead frame |
-
1988
- 1988-02-19 JP JP1988020926U patent/JP2514430Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01125573U (en) | 1989-08-28 |
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