JPH11330371A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having input-output buffer cells, in which cell widths can be made smaller than those of existing input-output buffer cells, and layout and wiring can be done with cells of the same kind and the same performance. SOLUTION: The semiconductor device has plural input-output buffer cells mutually adjacent to each other in peripherals of inner logic circuit area. Bonding pads 1a and 1b are located in input-output buffer cells, and are wire bonded in staggered arrangement with input and output buffer cells.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device.

[0002]

2. Description of the Related Art In recent years, with the miniaturization of transistor sizes, the number of pins in semiconductor devices has been increasing. Accordingly, the conditions for limiting the chip size of the semiconductor device include not only the total number of transistors in the internal logic circuit area of the semiconductor device but also the distance between wire bonding pads at the time of assembly between two input / output buffer cells adjacent to each other. .

A conventional input / output buffer will be described below with reference to the drawings. FIG. 4 is a plan view showing the configuration of the conventional input / output buffer cell 10. As shown in FIG. In FIG. 4, reference numeral 1 denotes a bonding pad. Power supply wiring (hereinafter referred to as “Vdd wiring”) 2a indicated by hatching
b is a ground wiring (hereinafter, referred to as “Vss wiring”). The portion surrounded by the broken line is the logic circuit region 3 in the input / output buffer cell. 4 is a bonding pad 1
And the Vdd wiring 2 and the Vss wiring 3. Reference numeral 5 denotes wiring for connecting the logic circuit area 3 in the input / output buffer cell and the internal logic circuit area on the semiconductor device (hereinafter, referred to as "signal terminal on the input / output buffer cell")
It is.

Next, an example in which the arrangement and wiring are performed using the conventional input / output buffer cell 10 having the above configuration and the internal logic circuit area on the semiconductor device will be described with reference to FIG.
In FIG. 5, reference numeral 6 denotes a semiconductor device. On this semiconductor device 6, an internal logic circuit area 7 is arranged. Further, the same input / output buffer cell 10 as shown in FIG.
However, input / output buffer cells 10 are arranged side by side around the internal logic circuit area 7 on the semiconductor device 6 so as to be adjacent to each other. The connection between the internal logic circuit area 7 on the semiconductor device 6 and the input / output buffer column is performed by connecting the signal terminal 5 on the input / output buffer cell shown in FIG.
And it is done by.

The Vdd wiring 2a and the Vss wiring 2b
Are connected at positions equivalent to the input / output buffer cells 10 arranged adjacent to each other, as shown in FIG. Further, the horizontal input / output buffer cell column and the vertical input / output buffer cell column are also connected to the wiring 9a shown in FIG.
And 9b are connected to each other at equivalent positions.

[0006]

Problems with the conventional input / output buffer cell will be described with reference to FIG. FIG. 6 shows FIG.
It is the top view which extracted and expanded two adjacent input / output buffer cells 10 in the input / output buffer cell row | line in the middle.

In FIG. 6, reference numerals 12a and 13a represent a vertical dimension and a horizontal dimension of the bonding pad 1, respectively. Reference numeral 14a denotes a dimension from the center of each of the bonding pads 1, 1 on the two input / output buffer cells 10, 10 adjacent to each other. The dimension 14a is limited by the distance between the bonding pads 1 and 1 on the two input / output buffer cells 10 and 10 adjacent to each other at the time of wire bonding at the time of assembly. Is set to Reference numeral 15a denotes a distance from one end of the bonding pad 1 of one input / output buffer cell 10 to one end of the other input / output buffer cell 10 adjacent thereto. 16a is the width of the input / output buffer cells 10, 10, and 16A is the total width of two input / output buffer cells 10, 10 adjacent to each other.

The input / output buffer cells 10, 1 shown in FIG.
When the layout wiring is performed using 0, the chip size of the semiconductor device is determined not by the total number of transistors in the internal logic circuit region on the semiconductor device but by the total width 16A of two input / output buffer cells 10 and 10 adjacent to each other. There was a problem that it was decided.

In order to solve this problem, as shown in FIG. 7, two types of input / output buffer cells 10A and 10B having different positions of the bonding pads 1 along the length of the input / output buffer cells can be considered. Was.

That is, FIG. 7 shows two types of input / output buffer cells 10 having different positions of the bonding pads 1.
A and 10B are arranged side by side so as to be adjacent to each other.

In FIG. 7, reference numerals 12b and 13b represent a vertical dimension and a horizontal dimension of the bonding pad 1, respectively. Reference numeral 14b denotes a dimension in the width direction of the input / output buffer cells 10A and 10B from the center of each of the bonding pads 1 and 1 on the two input / output buffer cells 10A and 10B adjacent to each other. 16b is the width of the input / output buffer cell. 17b
Are input / output buffer cells 10A, 10A adjacent to each other.
This is the actual distance between B bonding pads 1 and 1.
Since the distance 17b is restricted by wire bonding at the time of assembly, the distance 17b is set to a minimum dimension that enables wire bonding. That is, in the example of FIG. 7, wire bonding is performed in a staggered manner.

As described above, the bonding pads 1, 1
The input / output buffer cells 10A and 10B of FIG. 7 are arranged side by side so as to be alternately adjacent to each other and wire-bonded in a staggered manner.
Of the bonding pad 1 in the lateral direction 13
b is not directly affected by this constraint, and this width 16b is
It can be smaller than the width 16a of the input / output buffer cell in FIG.

However, in order to arrange and wire using the input / output buffer cells as shown in FIG. 7, two types of input / output buffer cells 10A and 10B having the same performance and different positions of the bonding pads 1 and 1 are designed. There was a problem that had to be done.

Further, as a method for reducing the width of the input / output buffer cell, as shown in FIG. 8, a method in which two bonding pads 1 and 1 are arranged diagonally to each other on one input / output buffer cell 10C is known. it was thought. FIG. 8 shows such input / output buffer cells 10C and 10C.
Are arranged side by side so as to be adjacent to each other.

In FIG. 8, reference numerals 12c and 13c denote vertical and horizontal dimensions of the bonding pad 1, respectively. 16c is the width of the input / output buffer cell 10C. 17c is one input / output buffer cell 10C
Is the distance between the pair of bonding pads 1 and 1 in FIG. Since the distance 17c is restricted by wire bonding at the time of assembly, the distance 17c is set to a minimum dimension that enables wire bonding.

By arranging two bonding pads 1 and 1 diagonally on the input / output buffer cell 10C in this manner, it is not necessary to set the distance 15a shown in FIG.

Therefore, with the configuration of FIG. 8, it is possible to make the width 16c of the input / output buffer cell 10C smaller than the total width 16A of the two adjacent input / output buffer cells 10, 10 in FIG. Become.

However, if the bonding pads 1 and 1 are arranged diagonally to each other at both ends of the input / output buffer cell 10C as shown in FIG. 8, the length of the wire for wire bonding inside the chip is limited by assembly. Had the problem of receiving

The present invention has been made in order to solve the above-mentioned problems, and can reduce the cell width as compared with the conventional input / output buffer cell. It is an object of the present invention to provide a semiconductor device provided with an input / output buffer cell in which cells can be arranged and wired.

[0020]

According to the present invention, there is provided a semiconductor device having a plurality of input / output buffer cells arranged adjacent to each other around an internal logic circuit area. A plurality of bonding pads are provided in the buffer cell, and the plurality of input / output buffer cells arranged side by side are wire-bonded in a staggered manner.

With this arrangement, by arranging a plurality of bonding pads in one input / output buffer cell, wire bonding at the time of assembly can be performed in a staggered manner, and two adjacent input / output buffer cells can be connected. The restriction due to wire bonding on the distance between the bonding pads on the buffer cell can be made smaller than in the past. Furthermore, a single type of input / output buffer cell of the same performance is used without preparing two types of input / output buffer cells of the same performance with different bonding pad positions, which were conventionally required to perform wire bonding in a staggered manner. Alone, it is possible to perform arrangement and wiring, and the number of design steps can be significantly reduced.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described. FIG. 1 is a plan view showing a configuration of an input / output buffer cell of a semiconductor device according to an embodiment of the present invention. In FIG. 1, reference numerals 1a and 1b denote bonding pads arranged at two positions on the input / output buffer cell 20 along the length direction. 2a and 2b are Vdd wiring and V
The ss wiring is shown by oblique lines. Reference numeral 3 denotes a logic circuit area in the input / output buffer cell, which is surrounded by a broken line. 4a is a wiring connecting the bonding pad 1a and the bonding pad 1b, and 4b is a wiring connecting the bonding pad 1b.
b is a wiring connecting the logic circuit area 3 with the logic circuit area 3 in the input / output buffer cell. These wirings 4a and 4b are both wired on the same straight line with the same wiring width. Reference numeral 5 denotes a signal terminal on the input / output buffer cell for connecting the logic circuit area 3 in the input / output buffer cell and the internal logic circuit area on the semiconductor device. On one side. The bonding pads 1a and 1b and the signal terminal 5 on the input / output buffer cell transmit an input signal or an output signal via the logic circuit region 3 in the input / output buffer cell. Note that the bonding pads may be arranged at three or more positions along the length direction on the input / output buffer cell 20.

Next, an example in which the input / output buffer cell 20 according to the present invention is used to arrange and wire the internal logic circuit area on the semiconductor device will be described with reference to FIG. In FIG. 2, reference numeral 6 denotes a semiconductor device. The internal logic circuit area 7 is arranged on the semiconductor device 6, and the input / output buffer cells 20 of FIG. They are arranged side by side so that they are adjacent to each other. The connection between the internal logic circuit area 7 on the semiconductor device 6 and the column of the input / output buffer cells 20 is made by the signal terminal 5 on the input / output buffer cell and the wiring 8 shown in FIG. The horizontal input / output buffer cell row and the vertical input / output buffer cell row are connected to each other at equivalent positions by wirings 9a and 9b.

Since the plurality of bonding pads 1a and 1b are arranged on the input / output buffer cell 20 along the length thereof, the width of the input / output buffer cell is reduced to the width of the conventional input / output buffer cell. It can be smaller than the width. That is, as shown in FIG. 3, when wire bonding is performed in a staggered manner on the bonding pads 1a and 1b of the input / output buffer cells 20 and 20 adjacent to each other, the distance from the center of the bonding pads 1a and 1b for performing the wire bonding to each other is increased. Since the actual distance 17 is restricted by wire bonding at the time of assembly, the actual distance 17 is set to the minimum dimension that enables wire bonding.

Now, the center distance 1 between the bonding pads of the input / output buffer cells 20 adjacent to each other is 1
Assuming that 4 is equal to the center distance 18 between the bonding pads 1a and 1b along the length direction of the input / output buffer cell 20, the center distances 14 and 18 are 1 / √2 of the distance 17. Accordingly, correspondingly, the width of the input / output buffer cell 20 can be reduced to 1 / √2 of the width of the conventional input / output buffer cell 10 shown in FIGS. Become.

[0026]

As described above, according to the present invention, a plurality of bonding pads are provided in an input / output buffer cell, and a plurality of input / output buffer cells arranged side by side are wire-bonded in a staggered manner. As a result, the restriction on the distance between the bonding pads on the two input / output buffer cells adjacent to each other due to the wire bonding can be made smaller than before, so that the chip size of the semiconductor device is reduced. When the width is determined not by the total number of transistors in the circuit area but by the width of the input / output buffer cell, the chip size of the semiconductor device can be reduced as compared with the case where the layout is performed using the conventional input / output buffer cell. it can. Furthermore, a single type of input / output buffer cell of the same performance is used without preparing two types of input / output buffer cells of the same performance with different bonding pad positions, which were conventionally required to perform wire bonding in a staggered manner. Alone, it is possible to perform arrangement and wiring, and the number of design steps can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is a plan view of an input / output buffer cell in a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a plan view of a semiconductor chip in a case where the input / output buffer cell of FIG.

FIG. 3 is an enlarged plan view showing a main part in FIG. 2;

FIG. 4 is a plan view of a conventional input / output buffer cell.

5 is a plan view of a semiconductor chip in a case where the internal logic circuit area of the semiconductor device is arranged and wired using the input / output buffer cell of FIG. 4;

FIG. 6 is an enlarged plan view showing a main part in FIG. 5;

FIG. 7 is a plan view when another conventional plurality of input / output buffer cells are arranged adjacent to each other.

FIG. 8 is a plan view showing a case where a plurality of other conventional input / output buffer cells are arranged adjacent to each other.

[Explanation of symbols]

 1a Bonding pad 1b Bonding pad 7 Internal logic circuit area 14 Center-to-center dimension

Claims (1)

[Claims] 1. A semiconductor device having a plurality of input / output buffer cells arranged adjacent to each other around an internal logic circuit area, wherein a plurality of bonding pads are provided in the input / output buffer cells. A semiconductor device, wherein the plurality of input / output buffer cells arranged side by side are wire-bonded in a staggered manner.