JP2555774B2 - Semiconductor integrated circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a semiconductor integrated circuit.

[Conventional technology]

FIG. 5 is a plan view showing the structure of a conventional peripheral cell.
This peripheral cell is a pad (1) arranged in one place on the peripheral cell in the figure, the V _SS wiring and V _DD wiring shown in (2a) and (2b), and the peripheral cell logic circuit area surrounded by a dotted line. (3), pad (1) and peripheral cell logic circuit area (3)
Wiring (4) for connecting with the peripheral cell logic circuit area (3)
Wiring lead-out port (5) for connecting to the internal logic circuit
(Hereinafter referred to as input / output signal terminals on peripheral cells).

Next, a conventional peripheral cell and an example in which the internal logic circuit and the layout and wiring are performed using the peripheral cell will be described with reference to FIGS. 5 and 6.

In FIG. 6, (6) is a semiconductor chip on which an internal logic circuit (7) and a peripheral cell row (8a) in which the peripheral cells of FIG. 5 are arranged adjacent to each other,
(8b) is arranged, and the internal logic circuit (7) and the peripheral cell input / output signal terminal (5) arranged on each peripheral cell on the peripheral cell columns (8a) and (8b) are wired. It is connected at (9).

Further, as shown in FIG. 6, the V _DD wiring and the V _SS wiring of (2a) and (2b) shown in FIG. 5 are connected at positions equivalent to those of the neighboring peripheral cells, and further in the lateral direction. The cell row (8a) and the vertical peripheral cell row (8b) are also connected by the wirings (10a) and (10b).

[Problems to be Solved by the Invention]

 Problems of conventional peripheral cells will be described with reference to FIG.

FIG. 7 shows the peripheral cell rows (8a) and (8b) in FIG. 6 described above.
It is the top view which extracted and expanded two adjacent peripheral cells in the inside. In the figure, (12) and (13) represent the vertical and horizontal dimensions of the pad (1), which are a and b, respectively.
(14) represents the dimension from the center to the center of each pad on the adjacent peripheral cell, and is designated as c. This dimension c is set to a dimension that allows wire bonding, because of constraints imposed on wire bonding of the assembly. (17) is
It is the dimension from one end of the pad (1) provided to satisfy the dimension c to the edge of the peripheral cell, where d is d = (c−b) / 2 (1) above (1) The dimensions shown in the formula are required.

When performing layout and wiring using this peripheral cell, if the chip size is determined by the cell width shown in (16) in FIG. 7, there is a problem that the dimension d is large and the chip size is affected. .

The present invention has been made to solve the above problems, and an object thereof is to reduce the peripheral cell width per pad.

[Means for solving the problem]

A semiconductor integrated circuit according to the present invention includes a first power supply wiring,
Second power supply wiring, peripheral cell logic circuit area located in these power supply inter-wiring areas and power supply wiring areas, and a pair of wires arranged diagonally to each other with respect to the first and second power supply wirings It is characterized by peripheral cells constituted by bonding pads.

[Action]

In the peripheral cell according to the present invention, by arranging two pads in one peripheral cell in a zigzag pattern, it is possible to avoid the restriction of the pad spacing on the adjacent peripheral cells due to the wire bonding at the time of assembly. By using the region between the ends as a wiring and a logic circuit region, the peripheral cell width per pad can be reduced.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view showing the configuration of peripheral cells of a semiconductor integrated circuit according to an embodiment of the present invention. In FIG.
a) and (1b) are a pair of wire bonding pads diagonally arranged on the peripheral cell, which are shown by diagonal lines (2).
a) and (2b) are V _SS wiring and V _DD wiring, and (3) surrounded by a dotted line is a peripheral cell logic circuit area. The V _SS wiring (2a) and the V _DD wiring (2b) are formed in order to form the peripheral cell logic circuit area (3) widely in the peripheral cell.
It has a shape like the diagonal line in the figure. Further, (4a) and (4b) are wirings that connect the pads (1a) and (1b) to the peripheral cell logic circuit (3), and (5a) and (5b) are the peripheral cell logic circuit area (3). Input / output signal terminals on the peripheral cells for connecting to the internal logic circuit, which are arranged on one side of the internal cells on the peripheral cells. The pads (1a) and (1b) and the input / output signal terminals (5a) and (5b) on the peripheral cells are transmitted through the peripheral cell logic circuit area (3), respectively, to input or output signals.

Next, a peripheral cell of the present invention, and an example in which an internal circuit and a layout wiring are performed using the peripheral cell will be described with reference to FIGS. 1 and 2.

In FIG. 2, (6) is a semiconductor chip on which a peripheral cell row (8a) in which the internal logic circuit (7) and the peripheral cells of FIG. 1 are arranged adjacent to each other,
(8b) is arranged, and the connection between the internal logic circuit (7) and the peripheral cells on the peripheral cell columns (8a) and (8b) is arranged at two locations shown in FIG. It is connected to the on-cell input / output terminals (5a) and (5b) by a wiring (9).

Further, as shown in FIG. 2, the V _DD and V _SS wirings (2a) and (2b) shown in FIG. 1 are connected at a position equivalent to an adjacent peripheral cell, and further, a peripheral cell row in the lateral direction. The peripheral cell column (8b) in the vertical direction is also connected to (8a) by wirings (10a) and (10b). Therefore, in the peripheral cell array arranged in this way, pad (1a) and pad (1b) are
_Since it is separated by the _SS wiring (2a), V _DD wiring (2b) and peripheral cell logic circuit area (3), it is not restricted by wire bonding and the length of the cell row is smaller than that of the conventional peripheral cell row. can do.

Although the pair of wire bonding pads diagonally arranged in the peripheral cell of the above-described embodiment are arranged so as not to overlap each other in the peripheral cell height direction, the peripheral cell logic circuit area (3) is When it is possible to reduce the size, if a pair of wire bonding pads (1a) and (1b) diagonally arranged as shown in FIG. The width (16) is smaller than that of two conventional cells, and they are adjacent to each other and the wiring (10a), (1
The degree of overlap may be as large as the wire bonding constraint in the assembly between pads located on the same side with respect to 0b) allows.

Also, as shown in FIG. 4, a plurality of pads (1
The same effect can be obtained by arranging a) to (1d) in a zigzag pattern with respect to the adjacent pads.

〔The invention's effect〕

As described above, according to the present invention, the first power supply wiring, the second power supply wiring, the inter-power-supply-wiring area and the peripheral cell logic circuit area located in the power supply wiring area, and the power supply wiring are mutually opposed. Since the peripheral cell is composed of a pair of wire bonding pads diagonally arranged, the peripheral cell width can be made smaller than the cell width of two conventional peripheral cells, and the semiconductor chip size is equal to the peripheral cell width. If decided, there is an effect that a smaller chip size can be obtained than that using a conventional peripheral cell.

[Brief description of drawings]

FIG. 1 is a plan view of a peripheral cell which is an embodiment of the present invention,
FIG. 2 is a plan view of a semiconductor integrated circuit in the case where a peripheral cell is used to place and wire an internal circuit, and FIGS. 3 and 4 are plan views of a peripheral cell showing another embodiment of the present invention. FIG. 5 is a plan view of a conventional peripheral cell, FIG. 6 is a plan view of a semiconductor integrated circuit when layout and wiring are performed using the peripheral cell of FIG. 5, and FIG. 7 is a conventional peripheral cell. It is various size explanatory drawing of an adjacent peripheral cell. In the figure, (1), (1a) to (1d) are pads on the peripheral cell, (2a) and (2b) are V _SS wiring and V _DD wiring, (3) is a logic circuit area on the peripheral cell, and (4) ), (4a) to (4d) are wirings connecting the pad and the peripheral cell logic circuit, (5,),
(5a) to (5d) are input / output signal terminals on peripheral cells, (6) is a semiconductor chip, (7) is an internal logic circuit, (8a), (8b)
Is a peripheral cell row, (9) is a wiring connecting the peripheral cells and internal circuits, (10a) and (10b) are V of the horizontal and vertical peripheral cell rows.
_{This is the} wiring that connects the _SS and V _DD wiring. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (2)

(57) [Claims] 1. A first power supply wiring, a second power supply wiring, a peripheral cell logic circuit area located in an area between these power supply wirings and a power supply wiring area, and arranged diagonally to each other with respect to the power supply wiring. A semiconductor integrated circuit having a peripheral cell constituted by a pair of wire bonding pads formed as described above. 2. A first power supply wiring, a second power supply wiring, a peripheral cell logic circuit area located in an area between these power supply wirings and a power supply wiring area, and arranged diagonally to each other with respect to the power supply wiring. A semiconductor integrated circuit having a peripheral cell row in which a plurality of peripheral cells configured by a pair of wire bonding pads are arranged adjacent to each other and the pads are arranged in a staggered pattern.