JPH085558Y2 - Planar layout structure of input / output interface area in semiconductor chip - Google Patents

Description

The present invention relates to a planar layout structure of an input / output interface area in a semiconductor chip in an LSI (Large Scale Integrated Circuit) element.

(Prior Art) The plane layout structure of a semiconductor chip in an LSI is
An internal circuit area and an input / output interface area (hereinafter, referred to as an I / O area) formed around the internal circuit area are provided, and an output driver formation area and an output driver (in the I / O area) are provided. It has a structure having an output pad formation region connected to the output portion of the output buffer). A thin metal wire is wire-bonded to the output pad with an external lead of the LSI.

FIG. 2 shows especially I / O in the semiconductor chip according to the conventional example.
It is a figure which shows the plane layout structure of an area | region. In FIG. 2, reference numeral 2 is an I / O region surrounded by the power supply line 4 and the ground line 6 in the semiconductor chip. In this I / O area 2, output drivers 8, 10 and 12 each having a drive capability meeting a certain standard are formed. The first output driver 8 includes a bottom 8a along each of the power supply line 4 and the ground line 6, a pair of vertical sides 8b and 8b perpendicular to the bottom 8a, and an upper side 8c parallel to the bottom 8a. It occupies a pair of flat plane regions 8d, 8d surrounded by. Transistors having a CMOS structure are diffused and formed inside the semiconductor chip corresponding to the respective plane regions 8d, 8d, and both transistors are connected to each other so as to form an input inverting circuit (inverter).

Since the second output driver 10 and the third output driver 12 have the same structure as the first output driver 8,
In order to avoid duplication of the explanation, only the reference numerals are attached and the explanation is omitted. And each of the output drivers
Comparing 8, 10 and 12, the area of the plane area 8d is the smallest so that the drive capacity of the first output driver 8 is the minimum, and the drive capacity of the second output driver 10 is medium. The area of the planar region 10d is moderate, and the area of the planar region 12d is maximized so that the drive capability of the third output driver 12 is maximized.

Then, the output pads 14, 16 and 18 corresponding to the output sections of the output drivers 8, 10 and 12 are formed between the pair of rectangular flat regions 8d, 10d and 12d, respectively.
4, 16 and 18 are respectively connected to the corresponding output drivers 8, 10 and 12 by connection wirings 20, 22 and 24. This output pad 14,1
A thin metal wire (not shown) is bonded to external leads 6 and 18.

(Problems to be solved by the invention) However, in the case of the above conventional configuration, since the heights of the vertical sides of the plane region 8d and the plane region 10d which form the output driver are different from each other, There is a problem in that the wiring structure becomes complicated and it takes time to design and the masks used for etching need to have different shapes, which requires much time to manufacture.

The present invention has been made in view of the above circumstances, and an object of the present invention is to simplify the layout configuration of the output driver and to facilitate manufacturing.

(Means for Solving the Problems) In order to achieve the above-mentioned object, in the layout structure of the present invention, in the input / output interface region surface surrounded by the power supply line and the ground line in the semiconductor chip, each is constant. With a plurality of output drivers occupying a pair of quadrilateral planar regions whose bases are along each of the lines so as to have a drive capability that conforms to the standard, a plurality of output drivers are formed in the forming direction of the lines, A planar layout structure of an input / output interface region in a semiconductor chip in which an output pad corresponding to an output section of each output driver is formed between the pair of rectangular planar regions, wherein each output driver has a fixed While maintaining the standard drive capability, the heights of the vertical sides from each line are equal to each other. Is laid out in a position occupying a planar area of a rectangular shape, and the arbitrary output pad is laid out in a region between a pair of output drivers located next to a pair of output drivers to which the output pad corresponds. It has a structure.

(Operation) According to the present invention, the heights of the vertical sides of the output driver are equalized, so that the output driver can be designed only in its width dimension.

Also, if the heights of the output drivers are set equal to each other as described above, the width of the output driver having a large driving capability becomes wider, but the output pad is placed next to the pair of output drivers to which the output pad corresponds. By laying out in the region between the pair of output drivers located, the space between adjacent output drivers can be reduced.

Embodiment An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a diagram showing a planar layout structure of a semiconductor chip according to an embodiment of the present invention. In the planar layout structure of the present embodiment shown in FIG. 1, the portions corresponding to those of FIG. 2 according to the conventional example are designated by the same reference numerals, and the description of the portions having the same reference numerals is omitted.

The feature of the planar layout structure of the present embodiment is that the output drivers 8, 10 and 12 hold the drive capability of a certain standard, while the vertical sides 8b and 10b from the respective lines 4 and 6 are mutually maintained. , 12b so that the height is the same
8d, 10d, 12d are laid out.

Further, the output pad 14 is laid out in a region between the regions 10d of the pair of output drivers 10 located next to the regions 8d of the pair of output drivers 8 to which the output pad 14 corresponds in part. is there.

As mentioned above, the heights of 8b, 10b and 12b are made equal, so that the output drivers 8, 10 and 12 can be designed only in the width dimension, the layout configuration is simple, and the etching mask shape is Also easy to do.

Further, even in the configuration in which the vertical sides of the output drivers 8, 10, 12 are made equal, a part of the output pad 14 is located next to each of the regions 8d of the pair of output drivers 8 to which the output pad 14 corresponds. By laying out in a region between the regions 10d of the pair of output drivers 10, the region 8d
The distance between the area and the area 10d can be minimized.

(Effect of Device) As is apparent from the above description, according to the present invention, the heights of the vertical sides of the output drivers are equalized,
The output driver only needs to be designed for its width,
The arrangement configuration is simple and the etching mask shape is also simple, which facilitates manufacturing.

Also, if the heights of the output drivers are set equal to each other as described above, the width of the output driver having a large driving capability becomes wider, but the output pad is placed next to the pair of output drivers to which the output pad corresponds. By laying out in a region between a pair of output drivers located, the distance between adjacent output drivers can be made small, and thus the degree of integration can be made as high as possible.

[Brief description of drawings]

FIG. 1 is a plan view of an input / output interface area of a semiconductor chip according to an embodiment of the present invention. FIG. 2 is a plan view corresponding to FIG. 1 according to the conventional example. 2 ... I / O interface area, 4 ... Power supply line,
6 ... Ground line, 8, 10, 12 ... Output driver, 8d, 10d,
12d …… Output driver area, 14,16,18 …… Output pad.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 27/04 A

Claims (1)

[Scope of utility model registration request] 1. A bottom side of each of the two lines so that each of them has a drive capability meeting a certain standard in a plane of an input / output interface region surrounded by a power line and a ground line in a semiconductor chip. A plurality of output drivers that occupy a pair of quadrangular plane areas are formed in a plurality of directions in which the lines are formed, and the output drivers correspond to the output parts of the respective output drivers between the pair of quadrangular plane areas. An output pad is formed, and each of the output drivers has a quadrangular planar area having a shape in which the heights of the vertical sides from the respective lines are equal to each other while maintaining the drive capability of each constant standard. Occupying the position where the output pad is located adjacent to the pair of output drivers to which the output pad corresponds. A planar layout structure of an input / output interface area in a semiconductor chip, characterized in that the layout is arranged in an area between a pair of output drivers.