JPH07130972A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce an unconnected interconnection in an automatic 'arrangement and wiring operation because a wiring grid which connects and wires functional blocks lacks when a circuit whose cell utilization rate is high is realized. CONSTITUTION:In a semiconductor chip 15, P-type diffused layers 12 and N-type diffused layers 13 for fundamental cells 14 are adjacent at a definite interval in the Y-direction, and they are arranged in the semiconductor chip 15 so as to be deviated by one grid in the X-direction. VDDs and GNDs for power supply lines 11 are arranged alternately between the individual fundamental cells 14 in the Y-direction. When the semiconductor chip is formed in this manner, the fundamental cells in the Y-direction can use the power-supply lines 11 in common, and the number of the power-supply lines 11 in an internal cell region can be reduced by about 50% as compared with that in conventional cases. When a reduced portion is used as connection and interconnection grids, the efficieincy of interconnections connecting Fs and B becomes good, and a layout between the Fs and the Bs becomes easy.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a gate array type semiconductor integrated circuit device.

[0002]

2. Description of the Related Art A conventional gate array type semiconductor integrated circuit device, as shown in the basic cell of FIG.
D) line 41 and power supply (GND) line are provided on the P-type diffusion layer 42 and the N-type diffusion layer 43, respectively, and as shown in FIG. A semiconductor chip 54 is configured by arranging the basic cells 44 of FIG. 4 in a spread form over the entire surface of the cell region 53.

By the way, a function block (hereinafter referred to as FB) having a function such as an inverter or a flip-flop.
Is designed by using the basic cell 44. When a desired circuit is realized, the blocks F and B are arranged and the connection wiring between the blocks F and B is performed by the wiring grid defined by the design standard. , The semiconductor chip 54 is configured.

[0004]

In this conventional gate array type semiconductor integrated circuit device, the VDD line 41 and the GN are provided on the semiconductor chip 54 when a desired circuit is realized.
The basic cell 44 having two D lines 41 is arranged in the Y direction, but the block F in the Y direction of the semiconductor chip 54
Since the connection wiring grid between B is used as the power supply line 41 by twice as many as the number of the basic cells 44 arranged in the Y direction, when a circuit with a high cell usage rate is realized, the block F is used.
There is a problem in that the wiring grid for connecting and connecting between B is insufficient and unconnected wiring occurs in the automatic placement and wiring, the cell usage rate decreases, and the integration degree decreases. Further, since the unconnected wiring is manually connected and wired, there is a problem that the design period becomes long.

[0005]

A gate array type semiconductor integrated circuit device of the present invention is a basic cell having a P-type diffusion layer in the upper part and an N-type diffusion layer in the lower part, and an N-type diffusion layer in the upper part and a lower part in the lower part. In a gate array type semiconductor integrated circuit device in which basic cells having a P-type diffusion layer are alternately arranged at regular intervals in the Y direction, a power supply line is provided at a boundary portion of each basic cell arranged in the Y direction. In particular, a part of the diffusion layer connected to the GND of the N-type transistor in the basic cell and the diffusion layer connected to the VDD of the P-type transistor in the basic cell is projected, and this diffusion layer is used for the power supply. It is characterized by having a structure covered with lines.

[0006]

1 is a plan view showing a chip of a semiconductor integrated circuit device according to a first embodiment of the present invention.

In FIG. 1, the first embodiment has a P
A basic cell having a type diffusion layer 12 and an N-type diffusion layer 13 in the lower portion, and a basic cell having an N-type diffusion layer 13 in the upper portion and a P-type diffusion layer 12 in the lower portion are alternately arranged at regular intervals in the Y direction. In the gate array type semiconductor integrated circuit device,
The power supply line 11 is provided between each basic cell 14 arranged in the Y direction.

Each of the P-type diffusion layer 12 and the N-type diffusion layer 13 of the basic cell 14 of FIG. 3, which shows the basic cell 14 of FIG. 1 in detail, are adjacent to each other at a certain interval in the Y direction and in the X direction. When they are arranged on the semiconductor chip 15 by shifting one grid, the VDD line and the GND line of the power supply line 11 are alternately arranged between the respective basic cells 14 in the Y direction.

With such a structure, the basic cells 14 in the Y direction can share the power supply lines 11, and the number of the power supply lines 11 in the internal cell area can be reduced by about 50% as compared with the conventional one. By using that portion as a connection wiring grid, the wiring efficiency when connecting between the blocks F and B is improved.

The P-type diffusion layer 12 and the N-type diffusion layer 13 are also provided.
Since a part of the power supply line 11 is covered with the power supply line 11, it is easy to connect the source to the power supply line 11 when power is supplied to the source side of the MOS transistor.
Layout becomes easy.

FIG. 2 is a plan view of a semiconductor chip according to the second embodiment of the present invention.

In FIG. 2, each of the P type diffusion layer 22 and the memory cell N type diffusion layer 26 in the basic cell 24 having the P type MOS transistor, the N type MOS transistor, and the memory cell N type MOS transistor. Are adjacent to each other at a certain interval in the Y direction, and the P-type diffusion layers 22 of the respective basic cells 24 face each other in the Y direction.
Are arranged on the semiconductor chip 25 by shifting one grid in the X direction, and are arranged so as to cover the VDD line 21 between the respective basic cells in the Y direction to which the P-type diffusion layers 22 face each other.
The GND line 21 is arranged on the mold diffusion layer 23.

With this structure, P in the Y direction
When the type diffusion layers 22 face each other, the VDD line 21 can be shared, and the number of the power supply lines 21 in the internal cell region can be reduced by about 25% as compared with the conventional one, and the portion can be used as a connection wiring grid. By doing so, the wiring efficiency when connecting the blocks F and B is improved.

A part of the P-type diffusion layer 22 is a power line 21.
When the power is supplied to the source side of the MOS transistor, the structure covered with the source makes it easy to connect the source to the power supply line 21 and facilitate the layout of the blocks FB.

[0015]

As described above, according to the present invention, the power supply line VDD or GN is provided between the basic cells arranged in the Y direction.
Since it has D, the ratio of the number of wiring grids used as power supply lines to the wiring grid of the entire semiconductor chip can be reduced, so that even circuits with a high cell usage rate can easily connect blocks F and B by automatic placement and routing. Since wiring is possible, unconnected wiring can be prevented and the degree of integration can be increased, and since connection wiring by hand is not required, there is also an effect that the design period can be shortened.

Further, according to the present invention, in particular, a part of the diffusion layer connected to the GND of the N-type transistor in the basic cell and the diffusion layer connected to the VDD of the P-type transistor in the basic cell is projected, and this diffusion is performed. When the structure is such that the layer is covered with the power supply line, it is easy to connect the power supply line to the diffusion layer, and the block F
-Has the effect of facilitating the layout of B.

[Brief description of drawings]

FIG. 1 is a plan view of a semiconductor chip showing a first embodiment of the present invention.

FIG. 2 is a plan view of a semiconductor chip showing a second embodiment of the present invention.

FIG. 3 is a plan view of a basic cell according to the first embodiment.

FIG. 4 is a plan view of a conventional basic cell.

FIG. 5 is a plan view of a semiconductor chip including a conventional basic cell.

[Explanation of symbols]

 11, 21, 41, 51 Power line 12, 22, 32, 42 P-type diffusion layer 13, 23, 33, 43 N-type diffusion layer 14, 24, 31, 44, 52 Basic cell 15, 25, 54 Semiconductor chip 26 N-type diffusion layer for memory cell 53 Internal cell area 16, 27, 34, 45 Polysilicon gate

Claims (2)

[Claims] 1. A basic cell having a P-type diffusion layer in the upper part and an N-type diffusion layer in the lower part, and a basic cell having an N-type diffusion layer in the upper part and a P-type diffusion layer in the lower part, which are arranged at regular intervals in the Y direction. 2. A semiconductor integrated circuit device in which a gate array is arranged alternately with each other, wherein a power supply line is provided at a boundary portion of each basic cell arranged in the Y direction. 2. The G of the N-type transistor in the basic cell
2. A part of a diffusion layer connected to ND and a diffusion layer connected to VDD of a P-type transistor in the basic cell are made to project, and these diffusion layers are covered with the power supply line.
The semiconductor integrated circuit device described.