JPH0563165A - Semiconductor device - Google Patents

Abstract

PURPOSE:To set a scribe line almost at an arbitrary position and to facilitate the construction of an input-output protection circuit with regard to a borderless master slice semiconductor device. CONSTITUTION:A wafer is overspread with many patterns congruent with third patterns each consisting of the combination of a first pattern which is a lateral layout of logical circuit MOS transistors 20, 24 adjacent right and left and a second pattern which is a layout of input-output protection circuit elements 44, 46.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a master slice type semiconductor device.

[0002]

2. Description of the Related Art In recent years, in order to promptly respond to requests from customers, even diffusion processing, which occupies a large weight in LSI design and manufacturing, has been uniformly processed, and only the subsequent circuit wiring has been performed. The master slice method, which is used for each product type, has been adopted. This master slice method is useful for shortening the development period and reducing the development cost, and has the advantages that standardization can promote automation and that the characteristics of the developed product can be accurately predicted.

FIG. 3 is a schematic view showing a wafer on which a large number of basic master slice chips are formed, and FIG. 4 is an enlarged schematic view showing one basic master slice chip. Here, FIG. 4A shows a state before circuit wiring, and FIG. 4B shows a state after circuit wiring and further scribing. As shown in FIG. 3, one basic master slice chip 6 is formed on the wafer 2 in each square surrounded by a large number of vertical and horizontal planned scribe lines 4a and 4b indicated by broken lines in the figure. Each of these basic master slice chips 6 has a first area 6 in which a large number of basic cells for logical operation are formed as shown in FIG.
1 and a second region 62 in which a large number of input cells and / or output cells (hereinafter simply referred to as “input / output cells”) are formed so as to surround the first region 61. There is. Here, between the basic master slice chips 6 adjacent to each other, a gap 8 is provided for arranging a conductor pad connected to an input / output cell in circuit wiring and for scribing thereafter.

By carrying out circuit wiring on this wafer 2, arranging pads for connection to an external circuit, and further performing scribing, a semiconductor chip as shown in FIG. 4B is completed (region 61 and region). The illustration of the circuit wiring 62 is omitted). In this master slice method, the number of logic operation basic cells, the number of input / output basic cells, etc. are preliminarily manufactured up to the step prior to the circuit wiring regardless of the individual product type. Assuming a product type that is fixed and therefore requires a small number of basic cells for logic operation, a product type that requires complicated logic operation, etc.
For 00 gate, 800 gate, 2000 gate, ...
It is necessary to prepare many types of basic master slice chips. For this reason, some of the advantages of the master slice method for the purpose of versatility are lost.

In order to solve this problem, it has been proposed to dispose logic operation basic cells on the entire surface of the wafer (see Japanese Patent Laid-Open No. 2-58871). FIG. 5 is a plan view of a wafer according to this proposal, and FIG. 6 is an enlarged schematic view of the fine area A of FIG. Wafer 12 according to this proposal
Shows that the basic cell group 14 having a structure as shown in FIG. 6 is arranged over the entire surface. This basic cell group 14
Is an independent well region 16 and this well region 16
And an intermediate region 18 adjacent in the vertical direction. For example, when the wafer 12 is an n-type semiconductor wafer, the well region 16 is formed by doping the wafer with P-type impurities. Two n-channel MOS transistor groups 20 are formed in this P-type well region. This n
The channel MOS transistor group 20 is arranged in the order of first n ⁺ type region-first silicon gate terminal-second n ⁺ type region-second silicon gate terminal-third n ⁺ type region and connected in series 2 It is composed of a pair of n-channel MOS transistors each having one current path and two gate terminals arranged in parallel in the lateral direction. The second n ⁺ type region serves as one drain region of the pair of n-channel MOS transistors, and at the same time serves as the other source region. Further, three P ⁺ type diffusion regions 22 are formed in the P type well region 16. This P ⁺
The type diffusion regions 22 are arranged in the middle and both sides of the two n-channel MOS transistor groups 20.

In the intermediate region 18, two n-channel MOS transistor groups 2 in the well region 16 are formed.
Two P-channel MOs in the horizontal direction that correspond to 0
An S transistor group 34 is formed. The P-channel MOS transistor group 24 is arranged in the order of first P ⁺ type region-first silicon gate terminal-second P ⁺ type region-second silicon gate terminal-third P ⁺ type region and connected in series. It is composed of a pair of P-channel MOS transistors each having two current paths and two gate terminals arranged laterally with respect to each other. The second P ⁺ type region serves as one drain region of the pair of P-channel MOS transistors, and at the same time serves as the other source region. Further, in the intermediate region 18, three n ⁺ type diffusion regions 26 are formed. The n ⁺ type diffusion regions 26 are arranged in the middle and both sides of the two p channel MOS transistor groups 24.

Here, the P ⁺ type diffusion region 22 in the well region 16 and the n ⁺ type diffusion region 2 in the intermediate region 18 are formed.
6 is used to stabilize the substrate potentials of the well region 16 and the intermediate region 18, respectively. Here, a circuit element such as a MOS transistor arranged in a well formed on the wafer can be used as long as the well is not damaged by the scribe, so that the extremely small basic cell 14 as described above is used for the wafer. By arranging on the entire surface of 12, it is possible to scribe an arbitrary position, and by configuring the input / output circuit also using this basic cell 14, a semiconductor chip of an arbitrary size and a small amount of wasted space is constructed.

[0008]

Normally, the input / output circuit of the semiconductor chip is constructed so that it will not be destroyed by noise or excessive voltage intruding from the outside. On the other hand, the logic circuit in the operation area is formed. Is configured so that noise and the like is prevented by the input / output circuit. Therefore, the input / output circuit area is a structure and element suitable for forming a protection circuit, and the basic cell in the operation area is related to the degree of integration. Each is composed of a structure and an element optimized for logical operation.

However, when both the input / output circuit and the logic circuit are composed of one type of basic cell as in the above-mentioned Japanese Patent Laid-Open No. 2-58871, (1) a structure in which the basic cell is optimized for logical operation Then, it is very difficult to realize the same input / output protection performance as the conventional one. (2) If the element of the basic cell has an optimized structure for input / output protection, the degree of integration of the logic operation circuit is greatly reduced. The problem arises.

In view of this point, an object of the present invention is to facilitate the structure of an input / output protection circuit in a borderless master slice type semiconductor device in which basic cells are arranged on the entire surface of a wafer.

[0011]

According to another aspect of the present invention, there is provided a semiconductor device according to the present invention, which is a semiconductor device of a master slice type, which is adjacent to each other in the left and right directions for logic circuit M.
A pattern congruent with the third pattern, which is a combination of the first pattern in which the OS transistors are arranged in the lateral direction and the second pattern in which the input / output protection circuit elements are arranged,
It is characterized in that a large number are formed on the entire surface of the wafer.

Here, the "congruent pattern with the third pattern" refers to both the third pattern and the pattern obtained by turning the third pattern over, and therefore, the entire surface of the wafer. The pattern formed in large numbers may be the third pattern described above, a pattern obtained by turning the third pattern over, or a mixture of both patterns.

Further, as an aspect of the semiconductor device of the present invention, the first pattern may be formed by a plurality of sub-patterns arranged in the vertical direction. Further, in the semiconductor device of the present invention, the second pattern formed on the wafer may be congruent with the second pattern, or the plurality of second patterns formed on the wafer may be laterally adjacent to each other. It is preferable that the fourth pattern, which is a combination of patterns, is formed so as to be bilaterally symmetric, and a pattern that is congruent with the second pattern,
Alternatively, it is preferable that the fourth pattern is vertically symmetrical.

The above "congruent pattern with the second pattern" also refers to both the second pattern and the pattern obtained by turning the second pattern inside out.

[0015]

In the semiconductor device of the present invention, a large number of patterns which are congruent with the third pattern and which include both logic circuit basic cells and input / output circuit basic cells are formed over the entire surface of the wafer. As a result, the position of the scribe line is hardly limited, and the configuration of the input / output protection circuit becomes easy. In addition, in the part other than the input / output protection circuit of the input / output circuit, the basic cell for the input / output protection circuit may be used when the basic cell for the input / output protection circuit remains, or the basic cell for the logic circuit You may comprise.

Here, the size of the logic circuit transistor may be very small, while at least the input / output protection circuit transistor among the input / output circuit transistors is required to have a relatively large size in order to withstand noise and the like. Becomes Therefore, the first pattern is composed of a plurality of sub-patterns aligned in the vertical direction, and one second pattern is adjacent to the plurality of sub-patterns. A precise arrangement is possible.

Further, it is preferable that pads for connecting to an external circuit can be arranged on both the left and right sides of the input / output circuit, so that the same input / output circuit can be configured for both the rightward and leftward directions. When a pattern congruent with the second pattern or a pattern congruent with the second pattern is formed adjacent to each other on the left and right, a first pattern consisting of a combination of these plural second patterns and congruent patterns is formed. It is preferable that the pattern 4 is formed symmetrically.

Further, it is preferable that pads for connecting to an external circuit can be arranged above and below the input / output circuit,
Therefore, in order to be able to configure the same input / output circuit both upward and downward,
It is preferable that a pattern congruent with the pattern is formed vertically symmetrically.

[0019]

EXAMPLES Examples of the present invention will be described below. FIG. 1 is a schematic diagram showing a unit of a basic cell group arranged on a wafer of a semiconductor device according to an embodiment of the present invention. The basic cell group constituting this one unit and / or the basic cell group of the pattern in which the basic cell group is turned upside down are arranged such that the longitudinal direction (left and right direction in the drawing) is aligned in the lateral direction (constant direction) of the wafer. It is arranged over the entire surface of the wafer. In this figure, constituent elements corresponding to the constituent elements of the basic cell shown in FIG. 6 are denoted by the same reference numerals as those given in FIG. 6, and detailed description of common points is omitted.

The basic cell group 30 is composed of a logic circuit basic cell group 32 and an input / output protection circuit basic cell 34 which are formed laterally adjacent to each other. Here, in this embodiment, the logic circuit basic cell group 32 and the input / output circuit basic cell 34 are considered to be the first pattern and the second pattern, respectively, according to the present invention. The logic circuit basic cell group 32 is similar to the unit cell 14 (see FIG. 6) in the conventional example in that it includes an independent well region 36 and an intermediate region 38 vertically adjacent to the well region 36. For example, 20 to 30 MOS transistor groups 20 are arranged in the well region 36. The same applies to the intermediate region 38.

In this way, this logic circuit basic cell group 32 is provided.
A large number of logic circuit MOS transistor groups 20 and 24 are laterally arranged in two columns. The input / output protection circuit basic cell 34 includes an independent well region 40 and an intermediate region 42 vertically adjacent to the well region 40. The well region 40 and the intermediate region 42 have a logic circuit MOS in the well region 40 and the intermediate region 42. Input / output protection circuit MOS transistor groups 44, 46 having a size larger than the transistor groups 20, 24
Diffusion regions 48 and 50 for stabilizing the potentials of the well region 40 and the intermediate region 42 are formed.

Further, the basic cell group 30 'adjacent to the basic cell group 30 is a basic cell group having a pattern in which the basic cell group 30 is turned upside down, and therefore is adjacent to the input / output protection circuit basic cell 34. Is formed with an input / output circuit basic cell 34 ′ having a pattern in which the input / output circuit basic cell 34 is turned upside down so as to have a bilaterally symmetrical pattern with respect to the one-dot chain line L shown in the drawing.

In the present embodiment, as described above, a large number of alternating reverse patterns are arranged in the horizontal direction, and basic cell groups are formed on the entire surface of the wafer so that the same pattern is repeated in the vertical direction. In this embodiment, since such a pattern is formed on the wafer, the scribe line can be set at almost any position and the input / output circuit can be easily constructed. Further, in the present embodiment, since the combination of the two input / output protection circuit basic cells 34, 34 'is configured to be bilaterally symmetric, the pad for connection with the external circuit is provided with the combined input / output protection circuit basic cell. The same input / output circuit is formed regardless of whether the cells 34 and 34 'are arranged on the left or right.

FIG. 2 is an enlarged schematic view showing the vicinity of a scribe line after circuit wiring is applied to a wafer of a semiconductor device according to another embodiment of the present invention. In this figure, the elements corresponding to the respective constituent elements such as the basic cells shown in the previous figures are given the same numbers as the numbers given in the previous figures, and explanations other than the differences are omitted. .. In each square area (hereinafter referred to as “each block”) surrounded by a large number of vertical and horizontal scribe lines 4a and 4b and having a side length of d, the same group as the logic circuit basic cell group 32 of FIG. The logic cell basic cell group 321 is arranged in six columns in the vertical direction, and the input / output protection circuit basic cells 34 corresponding to the input / output protection circuit basic cell 34 of FIG. A cell group 341 is arranged. The output protection circuit basic cell groups 341 are bilaterally symmetric, and are also vertically symmetrical. Therefore, in the present embodiment, each logic circuit basic cell group 321 corresponds to the sub-pattern according to the present invention, and a pattern obtained by combining six sub-patterns (logic circuit basic cell group 321) arranged in the vertical direction is the present invention. The input / output protection circuit basic cell group 341 corresponds to the so-called first pattern, and further corresponds to the second pattern of the present invention. Here, with respect to the six basic cell groups 321 for logic circuits,
One input / output protection circuit basic cell group 341 corresponds to each input / output protection circuit constituting the input / output protection circuit basic cell group 341 depending on the element performance and the required input / output protection performance. The basic cell is a logic circuit basic cell group 32.
1 for each logic circuit that composes 1 (logic circuit MOS
This is because a large area is required as compared with the transistor group 24 (see FIG. 6)).

The length d of one side of each block corresponds to the minimum pitch between the pads due to restrictions such as bonding between the pads on the chip and the lead frame of the semiconductor package. Basic cell group 341
Is the vertical length, and the vertical length of the logic circuit basic cell group 32 is the sum of six sub-patterns arranged so as to form the first pattern. In the horizontal direction, the sum of the horizontal length of the input / output protection circuit basic cell group 341 and the horizontal length of the logic circuit basic cell group 321 is configured to be d.

Before the circuit wiring, many planned scribe lines 4
Although it is not defined which of the planned scribe lines 4a, 4b of a and 4b is the line to be actually scribed, here, as a result of actually designing the circuit, the planned scribe lines 41a, 41b are It is scheduled to be scribed. Scheduled scribe lines 41a and 41b
On each block constituting the strip-shaped region 400 having the width d adjacent to the pad 6 at the same interval d as the pitch d of each block.
3 are arranged. Also, adjacent to the area 400, 2
An input / output buffer circuit is composed of a basic cell group 321 for logical operation and a basic cell group 341 for input / output protection circuit which form each of the two blocks, and the strip-shaped region 401 in which two blocks are arranged side by side corresponds to each other. Aluminum wiring 63 is provided between each input / output buffer circuit and each pad 63.
Connected by 1. A logic circuit is formed in a region 402 inside the strip-shaped region 401 in which the input / output buffer circuit is formed.

Thus, in this embodiment, all pads 6 are
3, the input / output buffer circuits can be efficiently arranged one to one, and the pads 63 are arranged at the minimum pitch d, that is, the maximum number of pads 63 in the same chip size.
Can be placed. Further, the first, second, and third patterns referred to in the present invention can be made into various shapes on the user side by appropriately configuring them in consideration of the element performance and the like as in the present embodiment. It is possible to configure a gate array that meets requirements.

In the above embodiment, the shape of the third pattern (each block) is schematically shown as a square, but the shape is not necessarily square. The shapes of the respective logic circuit basic cell groups 321 forming the first pattern do not necessarily have to be the same. Furthermore, the shape of the input / output protection circuit basic cell group 341 and the shape of each logic circuit basic cell group 321 do not necessarily have to be rectangular.

[0029]

As described above, according to the semiconductor device of the present invention, the first pattern in which the logic circuit MOS transistors are laterally arranged and the input / output protection circuit element which are adjacent to each other are arranged. Since a large number of patterns that are congruent with the third pattern, which is a combination with the second pattern, are formed on the entire surface of the wafer, the scribe line can be set at almost any position and the input / output protection circuit can be set. Is also easily configured.

When one or more basic input / output protection circuit basic cells are formed symmetrically and vertically symmetrically, the same input / output protection circuit is formed and pads are provided on both the left and right sides. It will be possible to arrange.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a unit of a basic cell group arranged on a wafer of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is an enlarged schematic view of the vicinity of a scribe line after circuit wiring is applied to a wafer of a semiconductor device according to another embodiment of the present invention.

FIG. 3 is a schematic view showing a wafer on which a large number of basic master slice chips are formed.

FIG. 4 is an enlarged view showing one basic master slice chip.

FIG. 5 is a plan view of a conventionally proposed wafer.

FIG. 6 is an enlarged schematic view showing a fine area A in FIG.

[Explanation of symbols]

 2, 12 Wafers 4a, 4b Scheduled scribe line 6 Basic master slice chip 8 Gap 14 Basic cell 16 Well 18 Intermediate region 20, 24 Logic circuit MOS transistor group 30, 30 'Basic cell group 36, 40 Well 38, 42 Intermediate region 44, 46 Input / output supply circuit MOS transistor group 321 Logic circuit basic cell group 341 Input / output protection circuit basic cell group

Claims (4)

[Claims] 1. In a master slice type semiconductor device, a first pattern in which logic circuit MOS transistors are laterally adjacent to each other and a second pattern in which input / output protection circuit elements are arranged. A semiconductor device, wherein a large number of patterns, which are congruent with the third pattern formed by the combination of, are formed on the entire surface of the wafer. 2. The semiconductor device according to claim 1, wherein the first pattern is formed of a plurality of sub-patterns that are vertically aligned with each other. 3. A pattern that is congruent with the second pattern formed on the wafer, or a combination of a plurality of second patterns and congruent patterns that are formed on the wafer adjacent to each other on the left and right sides. The fourth pattern is
3. The semiconductor device according to claim 1, wherein the semiconductor device is formed symmetrically. 4. The congruent pattern with the second pattern,
The semiconductor device according to claim 1, wherein the semiconductor device is vertically symmetrical.