JPS63182837A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the wiring capacities for assuring high speed actuation by a method wherein the part used as a wiring region out of an insulating film provided on a semiconductor element is selectively thickened. CONSTITUTION:In addition to a thin insulating film 15 provided on semiconductor elements FETQp1-Qp4 and Qn1-Qn4 to be a wiring region further to provide the first layer wiring 17 on the insulating film 16. Through these procedures, the gaps between the wiring 17 above a basic cell 7 and a gate electrode G, a source region and a drain regions 12, 14 are enlarged so that the parasitic capacity between the wiring 17 and the latter may be reduced.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device.

The present invention relates to a technique that is effective when applied to a master slice type semiconductor integrated circuit device.

[Prior art]

A master slice type semiconductor integrated circuit device.

Many logic functions, memory functions, etc. can be realized by changing the wiring pattern (mask pattern in the wiring formation process) applied to the master wafer. In this master wafer, one or more semiconductor elements (MISFET etc.)
A plurality of basic cells formed by the above are arranged in the first direction to form a basic cell column. This basic cell row is composed of complementary MISFETs, for example, a p-channel MISFET and an n-channel MISFET. Also.

This basic cell row is arranged in the second direction (
A plurality of them are formed at predetermined intervals in a direction perpendicular to the first direction. Semiconductor integrated circuit devices that employ this type of master slicing method are characterized by being able to complete products in a short time in response to requests from users.

Semiconductor integrated circuit devices employing this master slicing method tend to adopt a so-called sea of gate method in which basic cells are spread over the entire surface in advance. This gate-padding method uses a predetermined basic cell or a basic cell column as a logic circuit or a memory circuit, and can also use it as a wiring area if necessary. This laying method has the advantage of achieving high area usage efficiency. In particular, R.A.M.
(Rando Access Memory), RO
In semiconductor integrated circuit devices having M (Read 0nly Memory) etc.,
Circuits (memory cells) can be connected only by wiring within the basic cell column. Namely.

According to the all-in-one method, the wiring length is shortened to create RAM.

It is possible to condense the ROM and the like into blocks, reduce the area of the wiring area, and obtain extremely high area usage efficiency.

The technology regarding gate arrays as master slice type semiconductor integrated circuit devices is described, for example, in Nikkei Microdevice J, September 1986 issue, pages 65 to 80, published by Nikkei McGraw-Hill.

[Problem that the invention seeks to solve]

However, as a result of intensive study on the above technology, the inventor found the following problem.

That is, in the semiconductor integrated circuit device described above, the area above the semiconductor element is used as a wiring area;
For example, an insulating film provided between a complementary MISFET and a wiring layer passing above it is considerably thinner than a field insulating film formed by selective oxidation, which is generally used as a wiring region.

As a result, a large parasitic capacitance is generated between the wiring layer and the semiconductor element, which poses a major obstacle to high-speed operation of semiconductor integrated circuit devices.For example, 1986, CICG (1986, CICG) P, 281-P , 284.

If the laying method is adopted, the average wiring capacity will be 47゜4.
% increase has been reported. Moreover, the area above the semiconductor element becomes the wiring area, and the connection between the first layer wiring and the second layer wiring is made above the thin insulating film on the semiconductor element. Defects such as short-circuiting with the wiring are likely to occur, which may adversely affect reliability and yield.

An object of the present invention is to provide a technique that can realize high-speed operation by reducing wiring capacitance in a semiconductor integrated circuit device that employs a master slice method.

Another object of the present invention is to prevent defects due to short circuits between the second layer wiring and the semiconductor element serving as the wiring area when connecting the first layer wiring and the second layer wiring, and to The objective is to improve the reliability and yield of integrated circuit devices.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of one typical invention disclosed in this application is as follows.

That is, the portion of the insulating film provided on the semiconductor element used as the wiring region is selectively made thicker.

[Effect]

According to the above-mentioned means, since there is a thick insulating film on the semiconductor element used as a wiring region, the parasitic capacitance between this semiconductor element and the wiring passing above it is small, and therefore high-speed operation can be achieved. Can be done. In addition, because of this thick insulating film, the first layer wiring and the second layer wiring are placed above the semiconductor element.
Even if the wiring is connected to the wiring in the second layer, a short circuit between the semiconductor element and the wiring in the second layer can be prevented, and therefore the reliability and yield of the semiconductor integrated circuit device can be improved.

〔Example〕

Hereinafter, one embodiment of the present invention will be specifically described using the drawings.

Note that throughout the description of the embodiments, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

FIG. 1 is a plan view showing a master slice type semiconductor integrated circuit device according to an embodiment of the present invention.

As shown in FIG. 1, external terminals (ponding pads) 2 are provided at the periphery of the semiconductor integrated circuit device 1 according to the present embodiment.
and a plurality of turnout cover sofa circuits 3 are arranged. Further, above the human output buffer circuit 3 in the peripheral portion of the semiconductor integrated circuit device 1, a power supply voltage (Vcc) wiring 4 and a reference voltage (Vss) wiring 5 extend respectively. For example, a circuit operating voltage Vcc=5V is applied to this power supply voltage wiring 4. Further, the reference voltage wiring 5 is set to 1, for example, the circuit ground potential Vss=OV.

In the center of the semiconductor integrated circuit device 1, a power main line 6 is provided extending in a mesh shape in the column direction (first direction) or row direction (second direction). This power supply main line 6 is configured as a set of a power supply voltage (Vcc) main line 1i6A and a base 1 voltage (Vss) main line 6B.

A plurality of basic cells are arranged on the entire surface of the central portion of the semiconductor integrated circuit device 1. A plurality of these basic cells are arranged in the column direction to form a basic cell column 8. Furthermore, a plurality of basic cell columns 8 are arranged in the row direction.

In the so-called spread type semiconductor integrated circuit device 1 in which the basic cells are spread out in the column and row directions, the basic cells or the basic cell columns 8 are used as wiring areas as necessary. This wiring area is configured to pass wiring connecting between logic circuits and memory circuits. In this laid-out type semiconductor integrated circuit device 1, basic cells or basic cell rows 8 are used to conduct logic circuits Logic,
The memory circuits ROM, RAM, etc. can be configured in blocks. Further, since these memory circuits ROM, RAM, etc. can be sufficiently connected by wiring provided within the basic cell, the wiring length can be shortened and extremely high area usage efficiency can be obtained. In addition, the logic circuit Logi
Also in c, the basic cell column 8 is used as a wiring area as much as necessary.

No wasted area.

The basic self is constructed as shown, for example, in FIG. 2 (a plan view of main parts). That is, the basic self is 1, for example, 4 p-channel MISFETs Q Px ~Q P
4 and four n-channel MISFETs Qn1 to Qn4. These MISFETs Qp are connected to an n-type well region 10 provided on the surface of a semiconductor substrate 9 such as a silicon substrate.
A gate insulating film, a gate electrode G, a p' type source region and a drain region 12 are formed in an active region surrounded by a field insulating film 11 which is located within the semiconductor substrate 9 and is selectively provided on the surface of the semiconductor substrate 9. It is made up of. Each MISF
The source or drain region 12 of the ETQp is configured integrally with the source or drain region 12 of another adjacent MISFETQP. On the other hand, the MISFET
Qn is located in the p-type well region 13 provided on the surface of the semiconductor substrate 9 and is formed in an active region surrounded by the field insulating film 11, and is connected to the gate insulating film, the gate electrode G, r
It is composed of a 1'' type source region and drain region 14.The source region or drain region 14 of each MISFETQn is constructed integrally with the source region or drain region 14 of other adjacent MISFETQn.In other words, the basic Self is designed to be able to construct a four-person NAND gate circuit.

A wiring made of a first aluminum layer is extended in a direction perpendicular to each gate G. First wiring 17 (Vcc
) is formed on the p-channel MI 5FETs QPt to Qp4 so as to pass through the center thereof. Second wiring 17 (V
ss) are similarly formed on MISFETQn, ~Qn4. This makes it possible to supply the power supply potential Vcc or the ground potential to the MISFET of the distributed cell.

The d-type and p-type semiconductor regions 24 and 25 are regions for supplying the power supply potential Vcc and the ground potential Vs+s to the n-type and p-type well regions 10 and IOA, respectively.

FIG. 3 shows a schematic cross-sectional view of the basic self.

In the conventional semiconductor integrated circuit device using the gate-padding method,
As mentioned above, since the first layer wiring passes over the thin insulating film on the semiconductor element which becomes the wiring area, there is a gap between this first layer wiring and the gate electrode, and between this wiring and the p° type source region. A large parasitic capacitance occurs between the wiring and the drain region or between this wiring and the Go type source region and drain region. On the other hand, according to this embodiment, while using a spreading method with high area efficiency, it is possible to realize a small parasitic capacitance like the fixed channel method, and realize high-speed operation of the semiconductor integrated circuit device. That is, as shown in FIG. 3, a thin insulating film 1 such as a Sin film provided on the entire surface
In addition to 5, a thick insulating layer such as a Sin film or the like is placed on the semiconductor elements (p-channel MISFET Qpz~QP4 and n-channel MISFET Qn-~Qn*) that serve as wiring regions. selectively providing the membrane 1B;
On this insulating film 16, a first layer wiring 17 made of, for example, an aluminum film is provided. Since the wiring 17 above the basic cell serving as the wiring region is provided on the thick insulating film 16, the distance between this wiring 17 and the gate electrode G, source region, and drain region 12, 14 is large. Because of the cloudiness, the parasitic capacitance between these and the wiring 17 can be reduced. Note that the wiring 17 connects the second
In addition to the fixed potentials (Vcc, Vss) shown in the figure, wiring within and between the basic self is formed.

FIG. 4 shows a cross-sectional view of a portion where the first layer wiring 17 and the second layer wiring 18 are connected. If a mask misalignment occurs in one photolithography step for forming a contact hole (through hole) in the insulating film 19 between the second layer wiring 18, the thin insulating film 15 on the basic self during etching may be removed. A hole is easily formed in the wiring, causing a short circuit between the second layer wiring and, for example, the p° type source and drain regions, which causes a big reliability problem and lowers the yield. In the gate array of the invention, even if misalignment occurs, as shown in FIG. 4, since there is a thick insulating film 16 on the semiconductor element in the wiring area, there will be no hole reaching the semiconductor substrate 9, etc. Therefore, short circuits between the wiring 17.18 and the source and drain regions 12.14 and the like can be prevented.

This allows the arrangement 8 to be
17 and the area 12 or 14 can be connected. That is, the connection hole for the connection can be formed at any position of the insulating film 16.16. Similarly.

The wiring 18 can be connected to any position in the regions 12 and 14. Furthermore, it is possible to connect the wirings 17 and 18 at any position within the basic self. In addition, the wiring 17 and/or 18 can be connected to the gate electrode G at both ends GP of each gate electrode G.

Note that the wiring is actually done using CAD.

The positions where each connection hole to be formed in the insulating film 15, 16, 17 can be formed at predetermined intervals are defined in advance, and are formed as necessary.

Next, a thick insulating film 1 on the basic self, which will be the wiring area.
The method for forming No. 6 will be explained.

As shown in Figure 5, first, a thin insulating film 1 on the basic self.
5, an insulating film 16A such as a thin plasma nitride film (p-5iN) and a thick plasma oxide film (p-S
An insulating film 16B such as in) is formed.

Next, as shown in FIG. 6, a photoresist 20 is coated on this insulating film 16B, and then this photoresist 20 is exposed using a predetermined mask. On this occasion.

The insulating film 16B is dry-etched together with the photoresist 20. Then, the insulating film 16B is dry-etched together with the photoresist 20. As a result, as shown in FIG. 7, a thick insulating film 16 is formed only above the wiring area, and an ideal cross-sectional structure is obtained. Here, the insulating film 16A, such as a plasma nitride film, serves as a stopper during the dry etching.

Next, a second method for forming the insulating film 16 will be described.

As shown in FIG. 8, a spin-on-glass (Spin-on-glass, S
○G) After applying the insulating film 16 like a film, this insulating fi1
A photoresist 20 having a predetermined shape is formed on the photoresist 6 by one step of photolithography. Next, the insulating film 16 is etched using the photoresist 20 as a mask, and then the photoresist 20 is removed to obtain the state shown in FIG. 9.Next, the insulating film 16 is reflowed by high-temperature treatment. As shown in FIG. 10, an insulating film 16 having a predetermined shape is formed.

In this embodiment, as shown in FIG. 11, among the basic cells, there is a basic cell row 8 (hatched area) in which gates or units of a certain logic function are lined up, and a basic cell row 8 (hatched area) that is a wiring area. (non-hatched portions) may be arranged alternately in the row direction to form a block of a logic circuit Logic.

Here, the insulating film on the basic cell row 8, which becomes the wiring region, is selectively formed thick.

In addition, as shown in FIG. 12, a cell 21 is composed of a plurality of basic cells in which gates or parts that are elements for realizing a logic function of a higher hierarchy are adjacent to each other. It is also possible to arrange the basic cells periodically, leaving a mesh-like basic cell group that forms a certain wiring area.
The insulating film on the basic cell group serving as the wiring region is selectively formed thick.

Furthermore, as shown in FIG. 13, in memories such as RAM and ROM, circuits (between memory cells) can be connected only by wiring within the basic self, so no basic self serving as a wiring area is generated. In particular, when high-speed memory operation is required, we focus only on a specific wiring 22 that endlessly crosses the basic self in the row or column direction, such as a word line or bit line, and only the part 23 in the area directly below it.
That is, it is possible to selectively thicken the insulating film only in a certain part of the basic self.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

For example, the basic self may be configured to be able to configure a two-man power NAND gate circuit, a three-man power NAND gate circuit, etc. Also, in the present invention, the basic self is constructed of complementary MISFETs and bipolar transistors. It can also be applied. Furthermore, the present invention can be applied even if the basic self is composed of a bipolar transistor.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, it is possible to reduce the wiring capacitance to increase the speed of operation of the semiconductor integrated circuit device, and to prevent short circuits between the second layer wiring and the semiconductor element, the reliability and yield of the semiconductor integrated circuit device can be improved. You can improve your performance.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing the overall configuration of a master slice type semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a plan view showing essential parts of a basic cell in the semiconductor integrated circuit device shown in FIG. Figure 3 is a cross-sectional view of main parts schematically showing the cross-sectional structure of the basic cell shown in Figure 2. Figure 4 shows the connection between the first layer wiring and the second layer wiring. 5 to 7 are cross-sectional views for explaining step-by-step the first method for forming the thick insulating film shown in FIG. 3, and FIGS. 8 to 10 are FIG. 4 is a cross-sectional view for explaining step-by-step the second method for forming the thick insulating film shown in FIG. 3; 11 is a plan view of a main part showing an example of the wiring area in the semiconductor integrated circuit device shown in FIG. 1, and FIG. 12 is a main part plan view showing another example of the wiring area in the semiconductor integrated circuit device shown in FIG. FIG. 13 is a plan view of a main part showing another example of the wiring area in the semiconductor integrated circuit bag shown in FIG. 1. In the figure, 1... Semiconductor integrated circuit device, 3... Input/output sofa circuit, 4... Wiring for power supply voltage, 5... Wiring for grounding power, F... Basic cell, 8... Basic cell row, 9...
・Conductor substrate, 10... n-type well region, 12.14.
... Saw region and drain region, 13 ... P-type well region, 16.19 ... Insulating film, 17.18 ... Wiring, Qpi to QP4 ... Char M I S F E
T, Qn, ~Qn4 = n-channel MISFET.

Claims (1)

[Scope of Claims] 1. A master slice type semiconductor integrated circuit device in which a desired circuit is obtained by arranging a plurality of semiconductor elements on a semiconductor substrate and wiring between these semiconductor elements, A semiconductor integrated circuit device characterized in that a portion of the insulating film provided on the semiconductor element used as a wiring region is selectively thickened. 2. The semiconductor element is composed of complementary MISFETs, a plurality of basic cells formed by the complementary MISFETs are arranged in a first direction to form a basic cell row, and the basic cells are arranged in a second direction different from the first direction. A plurality of basic cell rows are formed, and the basic cell row adjacent in the first direction or the second direction of one or more stages of the basic cell rows in which gates or logic units are arranged is used as the wiring area. A semiconductor integrated circuit device according to claim 1, characterized in that: 3. The semiconductor integrated circuit device according to claim 2, wherein a part of the basic cell column constituting the gate or logic unit is used as the wiring region. 4. The semiconductor integrated circuit device according to claim 2 or 3, wherein the basic cell is composed of a complementary MISFET and a bipolar transistor. 5. Claim 2 or 3, characterized in that the basic cell is constituted by a bipolar transistor.
The semiconductor integrated circuit device described in .