JP2541537B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effectively applied to a master slice type semiconductor integrated circuit device.

[Prior art]

The master slice type semiconductor integrated circuit device can realize many logical functions, storage functions, and the like by changing the wiring pattern (mask pattern in the wiring forming process) applied to the master wafer. In this master wafer, a plurality of basic cells formed by one or a plurality of semiconductor elements (MISFET, etc.) are arranged in the first direction to form a basic cell row. The basic cell array is composed of, for example, a complementary MISFET including a p-channel MISFET and an n-channel MISFET. In addition, a plurality of the basic cell rows are formed at predetermined intervals in the second direction (direction perpendicular to the first direction) with the wiring region interposed. The semiconductor integrated circuit device adopting this type of master slice method has a feature that a product can be completed in a short time in response to a request from a user.

In the semiconductor integrated circuit device adopting the master slice method, there is a tendency to adopt a so-called gate spread method (Sea of Gate) in which basic cells are spread over the entire surface in advance. This gate spreading method uses a predetermined basic cell or basic cell row as a logic circuit or a memory circuit,
It can be used as a wiring area if necessary. This spreading method has an advantage that a high area usage efficiency can be obtained. In particular, RAM (Random Acce
In a semiconductor integrated circuit device having an ss memory), a ROM (Read Only Memory), and the like, circuits can be connected (between memory cells) only by wiring in a basic cell row by a spreading method. That is, according to the spread method, the wiring length can be shortened to condense RAM, ROM and the like in a block manner, the area of the wiring region can be reduced, and extremely high use efficiency of the area can be obtained.

A technique relating to a gate array as a master slice type semiconductor integrated circuit device is described in, for example, "Nikkei Microdevice", published by Nikkei McGraw-Hill, September 1986, p.65-p.80.

[Problems to be solved by the invention]

However, as a result of diligent studies on the above technique, the present inventor found the following problem.

That is, in the above-mentioned semiconductor integrated circuit device, the upper side of the semiconductor element is used as the wiring region. However, the insulating film provided between this semiconductor element, for example, the complementary MISFET and the wiring layer passing thereover is generally the wiring region. It is considerably thinner than the field insulating film formed by selective oxidation used as. As a result, a large parasitic capacitance is generated between the wiring layer and the semiconductor element, which is a major obstacle to high-speed operation of the semiconductor integrated circuit device. For example, in 1986, CIC (1986, CICC) p.281 to p.284, it was reported that the wiring capacity increased by 47.4% on average when the spread method was adopted. Moreover, since the wiring region is above the semiconductor element and the wiring of the first layer and the wiring of the second layer is connected above the thin insulating film on the semiconductor element, the semiconductor element and the second layer are connected. A defect such as a short circuit with the wiring is likely to occur, which may adversely affect reliability and yield.

An object of the present invention is to provide a technique capable of realizing a high speed operation by reducing a wiring capacitance in a semiconductor integrated circuit device adopting a master slice method.

Another object of the present invention is to prevent a defect due to a short circuit between the wiring of the second layer and the semiconductor element in the wiring region when connecting the wiring of the first layer and the wiring of the second layer, It is to improve the reliability and yield of an integrated circuit device.

The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

The outline of a typical invention disclosed in the present application is briefly described as follows.

That is, a portion used as a wiring region in the insulating film provided on the semiconductor element is selectively thickened.

[Action]

According to the above-mentioned means, since the semiconductor element used as the wiring region has the thick insulating film, the parasitic capacitance between this semiconductor element and the wiring passing above the semiconductor element is small, and therefore high-speed operation can be achieved. You can Further, because of this thick insulating film, even if the wiring of the first layer and the wiring of the second layer are connected above the semiconductor element, a short circuit between the semiconductor element and the wiring of the second layer can be prevented. Therefore, the reliability and the yield of the semiconductor integrated circuit device can be improved.

〔Example〕

An embodiment of the present invention will be specifically described below with reference to the drawings.

In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and repeated description thereof will be omitted.

FIG. 1 is a plan view showing a master slice type semiconductor integrated circuit device according to an embodiment of the present invention.

As shown in FIG. 1, external terminals (bonding pads) are provided on the periphery of the semiconductor integrated circuit device 1 according to the present embodiment.
2 and a plurality of input / output buffer circuits 3 are arranged respectively. Further, a power supply voltage (V _cc ) wiring 4 and a reference voltage (V _ss ) wiring 5 extend on the input / output buffer circuit 3 in the peripheral portion of the semiconductor integrated circuit device 1. For example, the circuit operating voltage V
_cc = 5V is applied. Further, the reference voltage wiring 5 is
For example, the circuit ground potential V _ss = 0V is set.

At the center of the semiconductor integrated circuit device 1, a power supply main line 6
Are provided so as to extend like a mesh in the column direction (first direction) or the row direction (second direction). The power supply trunk line 6 includes a power supply voltage (V _cc ) trunk line 6A and a reference voltage (V _ss ) trunk line 6B as a set.

A plurality of basic cells 7 are installed on the entire surface of the central portion of the semiconductor integrated circuit device 1. A plurality of basic cells 7 are arranged in the column direction to form a basic cell row 8. Further, the plurality of basic cell columns 8 are arranged in the row direction.

In the semiconductor integrated circuit device 1 of the so-called spread type in which the basic cells 7 are spread in the column direction and the row direction in this way, the basic cell 7 or the basic cell column 8 is used as a wiring region as needed. This wiring region is configured to pass the wiring that connects the logic circuits and the storage circuits. In the spread-type semiconductor integrated circuit device 1, the logic circuit Logic, the storage circuit ROM, the RAM, and the like can be configured in blocks by using the basic cells 7 or the basic cell rows 8. Further, since these memory circuits ROM, RAM, etc. can be sufficiently connected between circuits only by the wiring provided in the basic cell 7, the wiring length can be shortened and the use efficiency of an extremely large area can be obtained. Further, in the logic circuit Logic as well, the basic cell row 8 is used as a wiring region by a necessary amount, so that no area is wasted.

The basic cell 7 is configured, for example, as shown in FIG. 2 (plan view of relevant parts). That is, the basic cell 7 is composed of, for example, a complementary MISFET including four p-channel MISFETs Q _{p1 to} Q _p4 and four n-channel MISFETs Q _{n1 to} Q _n4 . These MISFETs Q _p are located in an n-type well region 10 provided on the surface of a semiconductor substrate 9 such as an n ⁻ type silicon substrate, and a field insulating film selectively provided on the surface of the semiconductor substrate 9. It is formed in an active region surrounded by 11, and is composed of a gate insulating film, a gate electrode G, a p ⁺ type source region and a drain region 12. The source region or the drain region 12 of each MISFET Q _p is adjacent to another MISFET.
It is formed integrally with the source region or the drain region 12 of Q _p . On the other hand, the MISFETQ _n is formed in the p-type well region 13 provided on the surface of the semiconductor substrate 9 and in the active region surrounded by the field insulating film 11, and the gate insulating film,
The gate electrode G is composed of an n ₊ type source region and a drain region 14. The source region or drain region 14 of each MISFET Q _n is integrally formed with the source region or drain region 14 of another adjacent MISFET Q _n . That is, the basic cell 7 can configure a 4-input NAND gate circuit.

A wiring made of a first aluminum layer extends in a direction orthogonal to each gate G. First wiring 17 (V _cc )
Are formed on the p-channel MISFETs Q _{p1 to} Q _p4 so as to pass through the central portion thereof. The second wiring 17 (V _ss ) has MISFETQ _{n1 to} Q
Similarly formed on _n4 . By this, the MISF of the book cell
It is possible to supply the power supply potential V _cc or the ground potential to ET.

The n ⁺ type and p ⁺ semiconductor regions 24 and 25 are n type and p type, respectively.
Power source potential V _cc and ground potential V _{ss in the} well regions 10 and 10A
Is an area for supplying.

FIG. 3 shows a schematic diagram of a cross section of the basic cell 7. In the conventional gate-laying-type semiconductor integrated circuit device, as described above, the first-layer wiring passes over the thin insulating film on the semiconductor element to be the wiring region. Between the wiring and the p ⁺ type source region and the drain region, or between the wiring and the n ⁺ type source region and the drain region. On the other hand, according to the present embodiment, it is possible to realize a small parasitic capacitance as in the fixed channel method and realize a high speed operation of the semiconductor integrated circuit device while using the spread method having high area efficiency. That is, as shown in FIG. 3, in addition to a thin insulating film 15 such as a SiO ₂ film provided on the entire surface,
The semiconductor element that became the wiring area (p-channel MISFETQ _{p1 to} Q
A thick insulating film 16 such as a SiO ₂ film is selectively provided on the _p4 and n-channel MISFETs Q _{n1 to} Q _n4 ), and a first wiring 17 made of, for example, an aluminum film is provided on the insulating film 16. ing. Since the wiring 17 above the basic cell 7 to be the wiring region is provided on the thick insulating film 16, the wiring 17, the gate electrode G, the source region and the drain region 12,
The distance between 14 and 14 is large, which makes them 17
The parasitic capacitance between and can be reduced. In addition to the fixed potential (V _cc , V _ss ) shown in FIG.
Wirings within the basic cells 7 and between the basic cells 7 are formed.

FIG. 4 shows a cross-sectional view of a portion where the wiring 17 of the first layer and the wiring 18 of the second layer are connected. In the conventional spread gate array, mask misalignment occurs in a photolithography process for forming a contact hole (through hole) in the insulating film 19 between the first-layer wiring 17 and the second-layer wiring 18. When the etching occurs, a hole is immediately formed in the thin insulating film 15 on the basic cell 7 at the time of etching, and a short circuit occurs between the wiring of the second layer and, for example, the p ⁺ type source region and the drain region, resulting in reliability. This causes a big problem and lowers the yield. On the other hand, in the spread gate array of the present invention, even if there is a misalignment, as shown in FIG. Since no reaching hole is formed, it is possible to prevent a short circuit between the wirings 17, 18 and the source and drain regions 12, 14, etc.

This allows wiring 17 to be placed at any position on regions 12 and 14.
Can be connected to the area 12 or 14.
That is, a connection hole for the connection can be formed at any position of the insulating films 16 and 16. Similarly, the wiring 18 can be connected to these regions at arbitrary positions in the regions 12 and 14. Furthermore, at any position in the basic cell 7, wirings 17 and 18
It becomes possible to connect between and. Further, at both ends GP of each gate electrode G, the wiring 17 and / or 18 and the gate electrode G can be connected.

Actually, since the wiring is performed by CAD, the positions where the respective connection holes formed in the insulating films 15, 16 and 17 can be formed are defined in advance at predetermined intervals and are formed as needed.

Next, a thick insulating film on the basic cell 7 which becomes the wiring region
A method of forming 16 will be described.

As shown in FIG. 5, first, a thin insulating film on the basic cell 7 is formed.
An insulating film (stopper insulating film) 16A, such as a thin plasma nitride film (p-SiN), and an insulating film (first insulating film) 16B, such as a thick plasma oxide film (p-SiO), are formed on 15
To form. Next, as shown in FIG.
After applying the photoresist 20 on B, the photoresist 20 is exposed using a predetermined mask. At this time, overexposure is performed to form an inversely tapered photoresist 20. Next, the insulating film 16B is dry-etched together with the photoresist 20. As a result, as shown in FIG. 7, the thick insulating film 16 is formed only above the wiring region, and an ideal sectional structure is obtained. Here, the insulating film 16A such as a plasma nitride film is used.
Serves as a stopper during the dry etching.

Next, the second method for forming the insulating film 16 will be described.

As shown in FIG. 8, after an insulating film (second insulating film) 16 such as a spin-on-glass (SOG) film is applied on the thin insulating film 15, the insulating film 16 is coated. Photoresist with a predetermined shape is formed by photolithography process.
Forming 20. Next, after the insulating film 16 is etched using the photoresist 20 as a mask, the photoresist is
20 is removed to obtain the state shown in FIG. Next, the insulating film 16 is reflowed by high temperature treatment to form an insulating film 16 having a predetermined shape as shown in FIG.

In this embodiment, as shown in FIG. 11, among the basic cells 7, basic cell rows 8 (hatched portions) in which gates or units of a certain logic function are arranged, and basic cell rows 8 serving as wiring areas. (Parts not hatched) may be arranged alternately in the row direction to form a block of the logic circuit Logic. Here, the insulating film on the basic cell row 8 which becomes the wiring region is selectively formed thick.

In addition, as shown in FIG. 12, a cell 21 composed of a plurality of basic cells 7 in which parts that are elements for realizing a higher-level logical function in units of gates or certain logical functions are adjacent to each other is formed. Alternatively, the mesh-shaped basic cell group which becomes a certain wiring region may be left and arranged periodically. Here, the insulating film on the basic cell group to be the wiring region is selectively formed thick.

Further, as shown in FIG. 13, in a memory such as a RAM or a ROM, since the circuits (memory cells) can be connected only by the wiring in the basic cell 7, the basic cell 7 serving as a wiring area
Does not occur, but especially when high-speed memory operation is required,
Attention is paid only to a specific wiring that crosses the basic cell 7 in the row direction or the column direction endlessly, for example, a wiring 22 such as a word line or a bit line, and only a portion 23 of a region immediately below that, that is, a portion of the basic cell 7 exists. The insulating film can be selectively thickened only in a specific portion.

As mentioned above, although the present invention was explained concretely based on an example, the present invention is not limited to the above-mentioned example.
It goes without saying that various modifications can be made without departing from the spirit of the invention.

For example, the basic cell 7 is a 2-input NAND gate circuit, 3-input
It may be configured so that a NAND gate circuit or the like can be configured. Further, in the present invention, the basic cell 7 is a complementary MISFET.
Also, it can be applied even if it is composed of a bipolar transistor. Further, the present invention can be applied even if the basic cell 7 is composed of a bipolar transistor.

〔The invention's effect〕

The following is a brief description of an effect obtained by the representative one of the inventions disclosed in the present application.

That is, it is possible to reduce the wiring capacitance to achieve high-speed operation of the semiconductor integrated circuit device, and to prevent the short circuit between the second layer wiring and the semiconductor element, thereby improving the reliability and yield of the semiconductor integrated circuit device. It is possible to improve.

[Brief description of drawings]

FIG. 1 is a plan view showing an overall configuration of a master slice type semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a main part plan view showing a basic cell in the semiconductor integrated circuit device shown in FIG. 3 and FIG. 3 are cross-sectional views of a main part schematically showing the cross-sectional structure of the basic cell shown in FIG. 2, and FIG. 4 shows a connecting portion between the first layer wiring and the second layer wiring. 5 to 7 are cross-sectional views for explaining the first method for forming the thick insulating film shown in FIG. 3 in order of steps, and FIGS. 8 to 10 are 3 is a cross-sectional view for explaining the second method for forming a thick insulating film shown in FIG. 3 in the order of steps, and FIG. 11 is a cross-sectional view showing an example of a wiring region in the semiconductor integrated circuit device shown in FIG. 12 is a plan view of a main part showing another example of the wiring region in the semiconductor integrated circuit device shown in FIG. FIG. 6 is a plan view of a principal portion showing another example of the wiring region in the semiconductor integrated circuit device shown in FIG. In the figure, 1 ... Semiconductor integrated circuit device, 3 ... Input / output buffer circuit, 4 ... Power voltage wiring, 5 ... Ground voltage wiring, 7 ... Basic cell, 8 ... Basic cell row, 9 ... ... Semiconductor substrate, 10 ... n-type well region, 12, 14 ... Source region and drain region, 13 ... P-type well region, 15, 16, 19 ...
… Insulating film, 17, 18 …… Wiring, Q _{p1 to} Q _p4 … p channel MI
SFET, is a Q _n1 ~Q _n4 ...... n-channel MISFET.

Claims (1)

(57) [Claims] 1. A method of manufacturing a master slice type semiconductor integrated circuit device in which a predetermined circuit is configured by using a plurality of basic cells spread in a matrix direction on a main surface of a semiconductor substrate. Depositing a thin insulating film covering the plurality of basic cells on a substrate, depositing an insulating film for a stopper functioning as an etching stopper on the thin insulating film, and insulating film for the stopper A step of depositing a first insulating film on the first insulating film, and a photoresist is deposited on the first insulating film, and an overexposure process is performed on the photoresist to form a wiring region in the plurality of basic cells A step of forming a photoresist pattern in which the side surface has an inverse tapered shape on the area of the basic cell to be used, and the photoresist pattern is etched by an etching mass. By patterning the first insulating film using the stopper insulating film as an etching stopper, a thick insulating film is formed only on the area of the basic cell used as the wiring area of the plurality of basic cells. And a step of selectively forming the semiconductor integrated circuit device.