JP3085472B2 - Semiconductor integrated circuit device and method of forming the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to relates to a semiconductor integrated circuit device, in particular, a mask of a lateral structure ROM (R ead O nly M
The present invention relates to a technology that is effective when applied to a semiconductor integrated circuit device having emory).

[0002]

2. Description of the Related Art A mask ROM having a horizontal structure stores one bit ([bit]) of information at the intersection of a data line extending in a row direction and a word line extending in a column direction. Is arranged. This memory cell is composed of a MOSFET, a word line is connected to a gate electrode of the MOSFET, a source line is connected to a source region, and a data line is connected to a drain region.

The word line is integrally formed and electrically connected to an end of the gate electrode of the MOSFET in the gate width direction. That is, the word line is formed of the same gate material as the gate electrode of the MOSFET or formed in the same manufacturing process. The source line is formed integrally with and electrically connected to the source region of the MOSFET, and is formed of a semiconductor region (diffusion layer). The data line is formed of an aluminum alloy wiring formed in a wiring layer above the word line, and is connected to the memory cell through a connection hole formed in an interlayer insulating film which is a base insulating film of the aluminum alloy wiring. . The aluminum alloy wiring has a smaller resistance value than each of the above-described word line and source line, and can speed up the operation of reading information stored in the memory cell.

Recently, the mask ROM of the horizontal structure, in addition to those used only in the semiconductor memory device, PLA (P rogr
amable L ogic A rray), etc., as a logic circuit, or a microprocessor or the like, is used as a memory circuit mounted on the logic circuit. In the mask ROM having the horizontal structure used in this manner, two wiring layers (for example, aluminum alloy wiring) are formed in the peripheral circuit.

The peripheral circuit controls a read operation of information stored in a memory cell, such as a decoder circuit, a sense amplifier circuit, and a buffer circuit arranged around a memory cell array in which the plurality of memory cells are arranged. Circuit. The two wiring layers reduce unnecessary wiring and detouring of elements constituting peripheral circuits, for example, wiring connecting between MOSFETs or between circuits, and can reduce the wiring length. Therefore, the signal transmission speed is increased, and the horizontal structure is improved. The operation speed for reading information from the mask ROM can be increased. In addition, since the two wiring layers can reduce extra wiring and detouring of wiring and reduce the area occupied by wiring as described above, the mask ROM having a horizontal structure can be used.
Can be improved.

The mask ROM having the horizontal structure, which is used as a logic circuit for increasing the capacity, has a memory cell in which information is written out of a plurality of memory cells, that is, a MOSFET during a manufacturing process. The mainstream is to change the threshold voltage and write information. The threshold voltage is changed after the gate electrode of the MOSFET is formed and before the interlayer insulating film between the MOSFET and the data line is formed.
This is performed by introducing an impurity into the channel region through the gate electrode using an ion implantation technique.

In this information writing method, it is not necessary to separate a diffusion layer between adjacent bits on the drain side, and one contact is required for every two bits. Therefore, the cell size is small, and a mask having a horizontal structure is used. High integration, that is, large capacity of the ROM can be achieved.

Further, as for a mask ROM having a horizontal structure, which is used as a storage circuit mounted on a logic circuit for reducing the capacity, a drain region of a MOSFET as a memory cell, a data line, The mainstream is to write information depending on the presence or absence of the connection. The data line is formed in the first wiring layer on the lower side even when two wiring layers are formed in the peripheral circuit, and writing of information is performed by connecting holes (not shown) in an interlayer insulating film serving as a base insulating film of the data line. (Contact hole) is formed.

In the method of writing information, a data line, an interlayer insulating film,
A step of sequentially forming each of the second wiring layer and the protective film is performed. Since the information writing step is at the final stage of the manufacturing process, the manufacturing process ends after the information writing step (the product is To complete) can be shortened. Further, this information writing method only changes the pattern of the mask for forming the connection hole in the interlayer insulating film, and does not increase the number of masks used in the manufacturing process.

In addition, in this information writing method, it is necessary to separate a diffusion layer between adjacent bits on the drain side.
Since it is necessary to form a contact for each bit, the cell size becomes larger than that of a horizontal mask ROM in which writing is performed by changing the threshold voltage.

A horizontal type mask ROM in which information is written depending on whether or not a memory cell is connected to a data line is described in, for example, IED, 1983.
Year, p. 577 (IEDM, 1983, p. 577).

[0012]

In the above-described mask ROM having the horizontal structure, although the peripheral circuit has two wiring layers, the memory cell array has the data line as the data line among the two wiring layers. Only the first wiring layer is used. Therefore, in the mask ROM having the horizontal structure, in any of the above-described information writing methods, the manufacturing process is not completed unless the second wiring layer is formed, and the second wiring layer is formed. The time required until the end of the manufacturing process is increased by the amount corresponding to the step.

The above-mentioned mask ROM having the horizontal structure has the following structure.
Despite having two wiring layers in the peripheral circuit, one wiring layer is used in the memory cell array. Therefore, the mask ROM having the horizontal structure does not effectively use the wiring layer.

An object of the present invention is to provide a mask ROM having a horizontal structure.
In the semiconductor integrated circuit device provided with the above, there is provided a technique capable of shortening the time required from the information writing step to the end of the manufacturing process (to shorten the work completion) and effectively utilizing the wiring layer. Is to do.

Another object of the present invention is to achieve the above object,
It is an object of the present invention to provide a technique capable of increasing the operating speed of a mask ROM having a horizontal structure.

Another object of the present invention is to achieve the above object,
It is an object of the present invention to provide a technique capable of improving the integration degree of a mask ROM having a horizontal structure.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0018]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, typical ones will be briefly described as follows.

(1) A semiconductor integrated circuit having a mask ROM of a horizontal structure using a MISFET as a memory cell in which a drain region is connected to a data line, a word line is connected to a gate electrode, and a source line is connected to a source region. In the device, a plurality of wiring layers formed in a wiring layer above a gate electrode of a MISFET as a memory cell and formed with a smaller resistance value than the gate electrode in a memory cell array of the mask ROM having the horizontal structure. And a data line connected to a memory cell is formed on the uppermost layer of the plurality of wiring layers, and information is written based on the presence or absence of a connection between the drain region of the memory cell and the data line.

(2) A semiconductor integrated circuit having a laterally structured mask ROM using a MISFET as a memory cell in which a drain region is connected to a data line, a word line is connected to a gate electrode, and a source line is connected to a source region. In the device, a plurality of wiring layers formed in a wiring layer above a gate electrode of a MISFET as a memory cell and formed with a smaller resistance value than the gate electrode in a memory cell array of the mask ROM having the horizontal structure. And a data line connected to a memory cell is formed on the uppermost layer of the plurality of wiring layers, and a word line or a source line connected to the memory cell is formed below the uppermost layer of the plurality of wiring layers. And writing information based on the presence or absence of connection between the drain region of the memory cell and the data line.

(3) A memory cell array is formed by arranging a plurality of memory cells connected to data lines, word lines, and source lines. The operation of the memory cells is controlled around the memory cell array, and a MISFET is mainly used. In a semiconductor integrated circuit device having a mask ROM having a horizontal structure which constitutes a peripheral circuit arranged in a semiconductor device, the mask RO having a horizontal structure is provided.
In the peripheral circuit of M, a plurality of wiring layers are formed in a wiring layer above the gate electrode of the MISFET and formed with a smaller resistance value than the gate electrode, and in the memory cell array, A data line is formed on the same wiring layer as the uppermost layer of the plurality of wiring layers, and a word line or a source line is formed on the same wiring layer as the lower wiring layer than the uppermost layer of the plurality of wiring layers. Then, information is written depending on whether there is a connection between the memory cell and the data line.

(4) Logic is realized by combining an AND type cell arranged at the intersection of the input signal line and the product term line and an OR type cell arranged at the intersection of the product term line and the output signal line. In a method of forming a semiconductor integrated circuit device having a PLA in which a function is formed, an output signal line of the PLA is formed, and first information is written based on whether or not the output signal line is connected to an OR cell. Forming a backing wire of the input signal line connected to the AND type cell on the same wiring layer as the output signal line; forming a product term line of the PLA; Writing second information based on the presence or absence of connection, and forming a backing wiring of the product term line connected to the OR type cell in the same wiring layer as the product term line.

[0023]

According to the above means (1), the writing of information in the memory cell can be performed by the presence or absence of connection between the data line formed in the uppermost wiring layer and the memory cell, and the writing of this information can be performed in the manufacturing process. Since it can be performed at the final stage before forming the uppermost wiring layer (ie, the step of forming the connection holes), the time required from the information writing step of the mask ROM having the horizontal structure to the end of the manufacturing process can be shortened ( Construction completion).

According to the means (2) described above, in addition to the operation and effect of the means (1), the signal transmission speed of the word line or the source line is increased, and the reading operation speed of the information stored in the memory cell is increased. Since the operation speed can be increased, the operation speed of the mask ROM having the horizontal structure can be increased.

According to the above means (3), in addition to the operation and effect of the means (2), in the peripheral circuit of the mask ROM having the horizontal structure, a plurality of wiring layers can be formed and cross wiring can be performed. And the length of wiring can be shortened, so that the signal transmission speed can be increased, the operating speed can be increased, or the area occupied by the wiring can be reduced, and high integration can be achieved. By using the wiring layer, at least any two of the data line, the source line, and the word line of the memory cell array can be reduced in resistance, so that the information reading operation speed can be increased.

According to the above-mentioned means (4), writing of the first information of the PLA (for example, writing of information on the maker side)
Is a fixed information write, and a predetermined logical function can be formed only by writing the second information (for example, writing information on the user side) (PLA information is written in two stages), and this second information is written. Can be performed before the step of forming the uppermost wiring layer in the manufacturing process (the step of forming the connection hole), that is, at the final stage, so that the work can be shortened, and the step of forming the output signal line can be used. A line for backing a product line (a product term line of an OR type cell array) can be formed by using a process of forming a backing wire of a line and forming a product term line.
Wiring can be used effectively. Further, by forming a backing wiring on each of the input signal line and the product term line (the product term line of the OR type cell array), the signal transmission speed can be increased, and the operating speed of the PLA can be increased.

Hereinafter, the configuration of the present invention will be described together with embodiments.

In all the drawings for explaining the embodiments, parts having the same functions are given the same reference numerals, and their repeated explanation is omitted.

[0029]

(Embodiment 1) This embodiment 1 is applicable to a case where a semiconductor memory device is constituted only by a mask ROM having a horizontal structure, or a mask ROM having a horizontal structure is used as a storage device mounted on a logic circuit. 1 is a first embodiment of the present invention to which the present invention is applied.

The configuration of a mask ROM having a horizontal structure according to a first embodiment of the present invention is shown in FIG.

As shown in FIG. 1, a mask RO having a horizontal structure
M is mainly composed of a p- type semiconductor substrate 1 made of single crystal silicon. Memory cell array, n-channel M of peripheral circuit
In each formation region of the ISFET, a p-type well region 2 is formed on the main surface of the p- type semiconductor substrate 1.
In the formation region of the p-channel MISFET of the peripheral circuit, an n-type well region (not shown) is formed on the main surface of the p − type semiconductor substrate 1.

The mask ROM having the horizontal structure stores 1-bit information at the intersection of a data line (DL) extending in a row direction and a word line (WL) extending in a column direction. A cell is placed. This memory cell is a data line,
A plurality of word lines are arranged in the respective extending directions to form a memory cell array. Around this memory cell array, peripheral circuits, such as a decoder circuit, a sense amplifier circuit, and a buffer circuit, for controlling the operation of reading information from the memory cells are arranged.

The memory cell is located on the right side of FIG.
As shown in (main part plan view), an n-channel MISFET
Qn1 (for example, an element to which no information is written) or Qn1
n2 (for example, an element in which information is written).
This n-channel MISFET Qn1 or Qn2 is
In the region defined and surrounded by the element isolation insulating film (field insulating film) 3 and the p-type channel stopper region 4, it is formed on the main surface of the p-type well region 2. That is,
The n-channel MISFET Qn1 or Qn2 is mainly composed of a p-type well region (channel formation region) 2, a gate insulating film 5, a gate electrode 6, and a pair of n + -type semiconductor regions 7 used as a source region and a drain region.

The gate electrode 6 of the n-channel MISFET Qn1 or Qn2 is formed of a gate material, for example, a polycrystalline silicon film, and an impurity for reducing the resistance value is introduced into the polycrystalline silicon film. The gate electrode 6 is formed of a single layer (gate material) of a high melting point metal film or a high melting point metal silicide film, or a polycrystalline silicon film and a high melting point metal film or a high melting point metal silicide film laminated thereon. Laminated film (gate material)
May be formed.

The gate electrode 6 is integrally formed with a word line (WL) 6 at the end in the gate width direction and is electrically connected thereto. That is, the word line 6 is formed of the same conductive layer as the gate electrode 6 or formed in the same manufacturing process.

The n + -type semiconductor region 7 has a gate electrode 6
Are formed on the main surface of the p-type well region 2 at both ends in the gate length direction. The n + type semiconductor region 7 is formed by introducing an n type impurity by, for example, an ion implantation method. The n + type semiconductor region 7 is formed integrally with the source line and is electrically connected. That is, the source line is constituted by the n + type semiconductor region 7.

An n-channel MISFET Qn1, which is a memory cell into which no information is written, has n corresponding to a drain region.
The data line (DL) 13 is connected to the + type semiconductor region 7. The data line 13 is formed on the second wiring layer, which is the uppermost layer, of the two wiring layers formed on the gate electrode 6 with a lower resistance value than the gate electrode 6. The data line 13 is formed of, for example, an aluminum alloy film. This aluminum alloy film is made of Cu for improving electromigration resistance and Si for improving alloy spike resistance.
Is aluminum to which at least one of the above is added.

The data line 13 extends on the surface of the interlayer insulating film 11 and is once connected to one end of the intermediate conductive layer 10 through a connection hole (through hole) 12 formed in the interlayer insulating film 11. This intermediate conductive layer 10 is formed in the first wiring layer on the lower layer side of the two wiring layers, and is similarly formed of an aluminum alloy film. This intermediate conductive layer 1
Numeral 0 extends on the surface of the interlayer insulating film 8, and the other end of the intermediate conductive layer 10 is connected to the n + -type semiconductor region 7 through a connection hole (contact hole) 9 formed in the interlayer insulating film 8.

An n-channel MISFET Qn2, which is a memory cell in which information is written, has n +
Data line 13 is not connected to type semiconductor region 7. More specifically, the other end of the intermediate conductive layer 10 is connected to the drain region of the n-channel MISFET Qn2.
The connection hole 12 is not formed (information is written),
One end of intermediate conductive layer 10 and data line 13 are not electrically connected. In other words, when writing information in the memory cell, the data line 13 is constituted by the uppermost layer of the wiring layer.
And the memory cells are connected.

Although not shown, the first wiring layer of the two wiring layers extends in the same direction as the word line 6 and is short-circuited to the word line 6. A backing wiring (shunt word line 10) or extends in the same direction as the source line (7), and a backing wiring (10) short-circuited with this source line is formed.

N-channel MIS constituting the peripheral circuit
The FET Qn has a structure basically similar to that of the memory cell, as shown on the left side of FIG. That is, the n-channel MISFET Qn is formed on the main surface of the p-type well region 2 whose periphery is defined by the element isolation insulating film 3 and the p-type channel stopper region 4, and the p-type well region 2, the gate insulating film 5, the gate electrode 6, a pair of n + -type semiconductor regions 7 serving as a source region and a drain region. The first-layer wiring 10 and the second-layer wiring 13 formed in two wiring layers are connected between the n-channel MISFETs Qn of the peripheral circuit or between circuits constituted by the n-channel MISFETs Qn.

The p-channel MI constituting the peripheral circuit
Although not shown, the SFET is formed on the main surface of the n-type well region, and includes a gate insulating film 5, a gate electrode 6, and a pair of p + -type semiconductor regions serving as a source region and a drain region.

Next, a method of forming the above-described mask ROM having the horizontal structure will be briefly described with reference to FIGS. 3 to 6 (cross-sectional views showing main parts in respective manufacturing steps). In this description, the description of the p-channel MISFET is omitted.

First, a p-type well region 2 is formed on the main surface of a p- type semiconductor substrate 1 made of single crystal silicon.
An element isolation insulating film 3 and a p-type channel stopper region 4 are formed on the main surface of the non-active region of the mold well region 2.

Next, a p-type impurity is introduced into the main surface of the active region of the p-type well region 2 to set the threshold voltage of the n-channel MISFET to the enhancement type.

Next, a gate insulating film 5 is formed on the main surface of the active region of the p-type well region 2, and as shown in FIG.
A gate electrode 6 and a word line 6 (not shown) are formed on the gate insulating film 5.

Next, as shown in FIG. 4, an n + type semiconductor region 7 is formed on the main surface of the active region of the p type well region 2. Through the step of forming the n + -type semiconductor region 7, n-channel MISFETs Qn1 and Qn2, which are memory cells, are formed in the memory cell array, and n-channel MISFETs Qn are formed in peripheral circuits.

Next, the n-channel MISFET Qn
1, an interlayer insulating film 8 covering each of Qn2 and Qn is formed, and thereafter, a connection hole 9 is formed in the interlayer insulating film 8.

Next, as shown in FIG. 5, in the memory cell array, an intermediate conductive layer 10 and a not-shown backing wiring (10) are formed on the surface of the interlayer insulating film 8, and
In the peripheral circuit, the wiring 10 is formed. Intermediate conductive layer 1
0, the backing wiring, and the wiring 10 are formed in the first wiring layer on the lower layer side of the two wiring layers.

Next, an interlayer insulating film 11 covering the first wiring layer is formed. Thereafter, as shown in FIG.
In the memory cell array, the connection hole 12 is formed only in the memory cell region of the interlayer insulating film 11 where information is not written, and the connection hole 12 is formed in the memory cell region where information is written.
Does not form. That is, information is written in the memory cell array. In the peripheral circuit, a connection hole 12 is formed in the interlayer insulating film 11.

Next, a data line 13 is formed on the surface of the memory cell array of the interlayer insulating film 11, and a wiring 13 is formed on the surface of the peripheral circuit. Each of the data line 13 and the wiring 13 is formed on the uppermost second wiring layer of the two wiring layers. In the memory cell array, a memory cell to which information is not written is connected to the data line 13, and a memory cell to which information is written is not connected to the data line 13.

Thereafter, by forming a final protective film covering each of the data line 13 and the wiring 13, the mask ROM having the horizontal structure shown in FIGS. 1 and 2 is completed.

As described above, the drain region (n + type semiconductor region 7) is connected to the data line (DL), and the gate electrode 6
A word line (WL) 6 is connected to the source region and a source line (7) is connected to the source region. In the horizontal type mask ROM using the n-channel MISFET Qn as a memory cell, the memory cell array of the horizontal type mask ROM is A plurality of wiring layers (10 and 13) formed in a wiring layer above the gate electrode 6 of the MISFET Qn as a cell and having a smaller resistance value than the gate electrode 6;
And a data line 13 connected to the memory cell is formed on the uppermost layer of the plurality of wiring layers, and the connection between the drain region of the memory cell and the data line 13 is determined by the presence or absence of the connection hole 12. Write information (with or without). With this configuration, the writing of information in the memory cell can be performed by the presence or absence of the connection between the data line 13 formed in the uppermost wiring layer and the memory cell, and the writing of this information is performed by the uppermost wiring layer in the manufacturing process. Since the process can be performed at the final stage before the formation (the process of forming the connection holes 12), the time required from the information writing process of the mask ROM having the horizontal structure to the end of the manufacturing process can be reduced (the work can be shortened).

A drain region (n + type semiconductor region 7) is connected to the data line (DL), a word line (WL) 6 is connected to the gate electrode 6, and a source line (7) is connected to the source region. In a mask ROM having a lateral structure using n-channel MISFETs Qn as memory cells, a memory cell array of the mask ROM having the lateral structure is formed in a wiring layer above a gate electrode 6 of the MISFET Qn as a memory cell, and A plurality of wiring layers (10 and 13) formed with a resistance value smaller than 6, and a data line 13 connected to a memory cell on the uppermost layer of the plurality of wiring layers; Below the uppermost layer of the wiring layer, the backing wiring (10) of the word line connected to the memory cell or the backing wiring (1) of the source line.
0) and write information based on the presence or absence of connection between the drain region of the memory cell and the data line 13 (with or without the connection hole 12). With this configuration, in addition to the above-described effects, the signal transmission speed of the word line 6 or the source line (7) can be increased by the backing wiring, and the operation speed of reading information stored in the memory cell can be increased.
The operation speed of the mask ROM having the horizontal structure can be increased.

The data line (DL) and the word line (W
L) A plurality of memory cells connected to 6 and the source line (7) are arranged to form a memory cell array, and the operation of the memory cells is controlled around the memory cell array and n
In a mask ROM having a lateral structure which mainly constitutes a peripheral circuit mainly including the channel MISFET Qn, the peripheral circuit of the mask ROM having the lateral structure is formed in a wiring layer above the gate electrode 6 of the MISFET, and A plurality of wiring layers formed with a resistance value smaller than 6, a data line 13 formed in the same wiring layer as an uppermost layer of the plurality of wiring layers in the memory cell array, and The backing wiring (10) of the word line 6 or the backing wiring (1) of the source line (7) is in the same wiring layer as the wiring layer below the uppermost layer of the plurality of wiring layers.
0), and information is written according to the presence or absence of connection between the memory cell and the data line 13. With this configuration, in addition to the above-described effects, in the peripheral circuit of the mask ROM having the horizontal structure, the wiring layers can be formed in a plurality of layers, cross wiring can be performed, wiring can be routed or bypassed, and the wiring length can be shortened. The transmission speed can be increased, the operation speed can be increased, or the area occupied by the wiring can be reduced, the integration can be increased, and the data lines 13 and the source of the memory cell array can be obtained by using a plurality of wiring layers of the peripheral circuit. Since the resistance of at least any two of the line (7) and the word line (6) can be reduced, the operation speed of reading information can be increased.

The above-described mask ROM having the horizontal structure has the following structure.
Although the case of two wiring layers has been described, information is written in the same manner in the case where three or more wiring layers are formed, depending on whether or not the uppermost wiring layer is connected to the memory cell. .

(Embodiment 2) Embodiment 2 is a second embodiment of the present invention in which the integration degree of a mask ROM having a horizontal structure is further increased.
This is an example.

A configuration of a mask ROM having a horizontal structure according to a second embodiment of the present invention is shown in FIG.

As shown in FIG. 7, the mask ROM having the horizontal structure according to the second embodiment has an n-channel MIS memory cell.
An intermediate conductive layer (pad polysilicon) 15 is further interposed between the n + -type semiconductor region 7 corresponding to the respective drain regions of the FETs Qn1 and Qn2 and the intermediate conductive layer 10. This intermediate conductive layer 15 is composed of n-channel MISFETs Qn1, Qn
n2 are disposed on the side surfaces of the respective gate electrodes 6 in the gate length direction with a side wall spacer interposed therebetween.
Is connected to n @ + -type semiconductor region 7 in a self-aligned manner.
The region of the intermediate conductive layer 15 other than the connection portion with the n + -type semiconductor region 7 is drawn out onto the gate electrode 6 to allow the connection portion with the upper intermediate conductive layer 10 to overlap with the gate electrode 6.

That is, the intermediate conductive layer 15 eliminates the distance between the respective gate electrodes 6 of the n-channel MISFETs Qn1 and Qn2, which are memory cells, and the inner wall (intermediate conductive layer 10) of the connection hole 9, and overlaps the two. Therefore, the area occupied by the memory cells can be reduced, and the integration degree of the mask ROM having the horizontal structure can be improved. Similarly, in the peripheral circuit, an intermediate conductive layer 15 is interposed between the wiring 10 and the n + -type semiconductor region 7 of the n-channel MISFET Qn.

The mask ROM having the horizontal structure has a connection hole 12 connecting the data line 13 and the intermediate conductive layer 10 in the memory cell array, and a connection hole 12 connecting the wiring 13 to the wiring 10 in the peripheral circuit. The buried conductive layer 16 is formed in each of the insides. The buried conductive layer 16 is formed of, for example, a W film deposited only in the connection hole 12 by a selective CVD method.

The buried conductive layer 16 can reduce the level difference in the connection hole 12 and flatten the surface of the interlayer insulating film 11 which becomes the underlying insulating film of the data line 13 and the wiring 13. In addition, the processing accuracy of each of the wirings 13 can be improved, and as a result, the integration degree of the mask ROM having the horizontal structure can be improved.

(Embodiment 3) Embodiment 3 is a third embodiment of the present invention in which the present invention is applied to a semiconductor integrated circuit device provided with a PLA constituting a logic circuit with a mask ROM having a horizontal structure. .

FIG. 8 (block circuit diagram) shows a basic configuration of a PLA according to the third embodiment of the present invention.

As shown in FIG. 8, the PLA has an AND cell array 20 and an OR cell array 21.

In AND cell array 20, AND type cell MA is arranged at an arbitrary position at the intersection of complementary input signal line L1 and product term line L2 extending in the row direction. AND type cell M
A is basically composed of an n-channel MISFET. The gate electrode of the n-channel MISFET is connected to the input signal line L
1, the source region is connected to the ground potential, and the drain region is connected to the product term line L2. The input signal line L
1 receives an input signal Sin via an input driver circuit. The product term line L2 is a load n-channel MISFET
Are connected to the power supply potential V _DD via the power supply potential V _DD .

The OR cell array 21 is located at an arbitrary position at the intersection of the output signal line L3 extending in the row direction and the product term line L2.
An R-type cell MO is arranged. The OR type cell MO is similarly constituted by an n-channel MISFET. This n-channel MI
The gate electrode of the SFET is connected to the product term line L2, the source region is connected to the ground potential, and the drain region is connected to the output signal line L3. The output signal line L3 has one end connected to the power supply potential V _DD via a load n-channel MISFET, and the other end connected to an output driver circuit.
The output driver circuit outputs an output signal Sout.

FIG. 9 (plan view of a main part) shows a specific configuration of this PLA. As shown in FIG. 9, the AND cell MA arranged in the AND cell array 20 of the PLA has a p-type well region in a region defined by the element isolation insulating film 3 and the p-type channel stopper region (4). It is configured on the main surface of (2). That is, the AND-type cell MA includes a p-type well region, a gate insulating film (5), a gate electrode 6, and a pair of n + -type semiconductor regions 7 serving as a source region and a drain region.

The wiring layer (the number of aluminum alloy films) is composed of two layers as in the first embodiment.
The drain region of A has the second uppermost layer of the two wiring layers.
The product term line (L2) 13 formed in the first wiring layer is connected. In the AND cell array 20, information is written depending on whether the AND cell MA is connected to the product term line 13 (the presence or absence of the connection hole 12). The writing of this information is performed, for example, when creating a program on the user side. AND
The gate electrode 6 of the pattern cell MA is connected to an input signal line (L1) 6 integrally formed in the gate width direction, and the input signal line 6 is connected to a lower first side of two wiring layers.
The backing wiring 10 formed in the wiring layer of the layer is connected.

Similarly, the OR type cell MO arranged in the OR cell array 21 of the PLA is provided on the main surface of the p-type well region in the region defined by the element isolation insulating film 3 and the p-type channel stopper region. Be composed. That is, OR
The type cell MO includes a p-type well region, a gate insulating film, a gate electrode 6, and a pair of n + -type semiconductor regions 7 serving as a source region and a drain region.

The output signal line (L3) 10 formed in the first wiring layer of the two wiring layers is connected to the drain region of the OR type cell MO. In the OR cell array 21, writing of information is performed by the presence or absence of connection between the OR type cell MO and the output signal line 10 (the presence or absence of the connection hole 9). The writing of this information is performed, for example, when a fixed program is created on the manufacturer side. The product term line 13 extends on the gate electrode 6 of the OR type cell MO in the same direction as the gate electrode 6 and is electrically connected thereto, and forms a backing wiring 13 in the OR cell array 21.

Since the method of forming the PLA is almost the same as that of the mask ROM having the horizontal structure of the first embodiment, the description is omitted here.

As described above, the input signal line L1 and the product term line L2
And a PLA in which a logical function is formed by combining an AND type cell MA arranged at the intersection with the OR and an OR type cell MO arranged at the intersection of the product term line L2 and the output signal line L3. In the method for forming a semiconductor integrated circuit device,
An output signal line (L3) 10 of LA is formed, and first information is written according to the presence or absence of connection between the output signal line 10 and the OR type cell MO, and the AND signal is connected to the same wiring layer as the output signal line 10. Signal line L1 connected to pattern cell MA
Forming the backing wiring 10 of the above, forming the product term line (L2) 13 of the PLA, writing the second information based on the presence or absence of connection between the product term line 13 and the AND type cell MA; The OR-type cell M
Forming a backing wiring 13 of the product term line (6) connected to O. With this configuration, the writing of the first information of the PLA (for example, the writing of information on the maker side) is regarded as the writing of fixed information, and the writing of the second information (for example, writing of information on the user side) is used to execute a predetermined logical function. Can be formed (PLA information is written in two stages), and this second information is written in the uppermost wiring layer (13) in the manufacturing process.
Can be performed before the step of forming the contact holes (the step of forming the connection holes 12), that is, at the final stage, so that the work can be shortened, and the input signal lines (L
1) The step of forming 6 backing wirings 10 and forming the product term line 13 is used to form the product term line (the product term line L of the OR type cell array).
2) Since six backing wirings 13 can be formed, the wirings can be used effectively. Further, by forming the backing wirings 10 and 13 on the input signal line 6 and the product term line (product term line of the OR type cell array) 6, respectively, the signal transmission speed is increased, and
The operation speed of A can be increased, or the area occupied by the wiring of the input signal line 6 and the product term line 6 can be reduced, so that the integration of the PLA can be increased.

Note that the above-mentioned PLA is obtained by combining the product term line with AN
First information is written according to the presence or absence of connection with the D-type cell, and a backing wire of the product term line connected to the OR-type cell is formed on the same wiring layer as the product term line, and the output signal line is connected to the output signal line. The second information may be written depending on the presence or absence of the connection with the OR type cell, and the backing wiring of the input signal line connected to the AND type cell may be formed in the same wiring layer as the output signal line.

As described above, the invention made by the present inventor is:
Although the present invention has been described in detail with reference to the embodiment, the present invention is not limited to the embodiment, and it is needless to say that various changes can be made without departing from the scope of the invention.

[0076]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

In a semiconductor integrated circuit device provided with a mask ROM having a horizontal structure, the time required from the information writing step to the end of the manufacturing process can be reduced (the work can be shortened) and the effective use of the wiring layer can be achieved. I can do it.

Further, in a semiconductor integrated circuit device provided with a mask ROM having a horizontal structure, the operation speed can be increased.

Further, in a semiconductor integrated circuit device provided with a mask ROM having a horizontal structure, the degree of integration can be improved.

[Brief description of the drawings]

FIG. 1 shows a mask RO having a horizontal structure according to a first embodiment of the present invention.
Sectional drawing of the principal part of M.

FIG. 2 is a plan view of a main part of the mask ROM having the horizontal structure.

FIG. 3 is an essential part cross sectional view in a first step for explaining a method of forming the mask ROM having the horizontal structure.

FIG. 4 is an essential part cross-sectional view in a second step.

FIG. 5 is a sectional view of a main part in a third step.

FIG. 6 is an essential part cross-sectional view in a fourth step.

FIG. 7 is a mask RO having a horizontal structure according to a second embodiment of the present invention;
Sectional drawing of the principal part of M.

FIG. 8 is a block circuit diagram of a PLA according to a third embodiment of the present invention.

FIG. 9 is an essential part plan view showing a specific configuration of the PLA.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Well area, 5 ... Gate insulating film,
6 gate electrode, word line, input signal line or product term line, 7
... Semiconductor region, 9,12 ... Connection hole, 10 ... Wiring, lining wiring, intermediate conductive layer or output signal line, 13 ... Wiring, data line, lining wiring or product term line, Qn ... MISFET, DL
... data line, WL ... word line, L1 ... input signal line, L2
... product term line, L3 ... output signal line, MA ... AND type cell, M
O ... OR type cells.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8246 H01L 21/82 H01L 27/112

Claims (5)

(57) [Claims] 1. A connection to a data line, a word line and a source line.
Memory cell array by arranging multiple memory cells
A memory cell array around the memory cell array.
Around the control of the operation of the MISFET and the MISFET
Semiconductor with horizontal mask ROM that constitutes a circuit
In the integrated circuit device, the peripheral circuit of the mask ROM having the horizontal structure has the MIS
In the wiring layer above the gate electrode of the FET, the gate
Multiple wiring layers formed with lower resistance than the electrodes
And the memory cell array includes an upper layer of the plurality of wiring layers.
A data line formed on the same wiring layer;
Word lines are placed on the same wiring layer as the lower wiring layer of several wiring layers.
Or a source line, wherein information is written depending on whether or not there is a connection between the memory cell and the data line. Wherein it is arranged at the intersection between the input signal line and the product term lines
AND type cell, intersection of the product term line and output signal line
A logical function is formed by combining each of the OR type cells
Forming method of semiconductor integrated circuit device provided with PLA formed
In the above, an output signal line of the PLA is formed, and this output signal line and O
The first information is written according to the presence or absence of connection with the R-type cell.
And the AND type cell in the same wiring layer as the output signal line.
Forming backing wiring of input signal line connected to
And a product term line of the PLA, and this product term line and the AND type cell are formed.
The second information is written depending on the connection with the
Connected to the OR type cell in the same wiring layer as the storage term line
Forming a backing wiring for the product term line.
A method for forming a semiconductor integrated circuit device. 3. A memory cell array is formed by arranging a plurality of memory cells connected to a data line, a word line, and a source line. The operation of the memory cells is controlled around the memory cell array, and a MISFET is mainly used. In a semiconductor integrated circuit device provided with a mask ROM having a horizontal structure constituting a peripheral circuit disposed therein, a peripheral circuit of the mask ROM having a horizontal structure is provided with a MIS
A plurality of wiring layers formed with a smaller resistance value than the gate electrode are formed in a wiring layer above the gate electrode of the FET, and the same as the uppermost layer of the plurality of wiring layers in the memory cell array. configure the data lines formed on the wiring layer, before Symbol semiconductor integrated circuit device characterized by writing information on the presence or absence of a connection is made between the memory cell and the data line. 4. A connection to a data line, a word line and a source line.
Memory cell array by arranging multiple memory cells
A memory cell array around the memory cell array.
Around the control of the operation of the MISFET and the MISFET
Semiconductor integrated circuit device provided with mask ROM constituting circuit
The peripheral circuit is more than the gate electrode of the MISFET.
An N layer having a lower resistance value than the gate electrode
Layers (N ≧ 2) are formed, and the memory cell array is formed in the same layer as the N-th wiring layer.
The formed data line and the same layer as the (N-1) th wiring layer
Conductive layer formed on the substrate and electrically connected to the memory cell
Between the (N-1) th wiring layer and the Nth wiring layer.
Of information depends on whether or not a connection hole is formed in the interlayer insulating film.
Semiconductor integrated circuit device characterized in that writing is performed
Place . 5. A buried conductive layer is formed in said connection hole.
Wherein the data line and the intermediate conductive layer are
Claims: Electrically connected via a layer
5. The semiconductor integrated circuit device according to item 4 .