JPH01218061A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the number of manufacturing processes by forming the following in an identical manufacturing process: a floating gate electrode of a nonvolatile memory element; an upper-part electrode of a capacitive element for information storage use of a dynamic memory element. CONSTITUTION:The following are manufactured in an identical manufacturing process: a floating gate electrode 9 of a non-volatile memory element; an upper- part electrode of a capacitive element (C) for information storage use of a dynamic memory element or gate electrodes of MISFETs Qds, Qfs for memory cell selection use. In addition, the following are formed in an identical manufacturing process: a control gate electrode 13 of the nonvolatile memory element; gate electrodes 13 of the MISFETSs Qds, Qfs for memory cell selection use of the dynamic memory element or the upper-part electrode of the capacitive element (C) for information storage use. Accordingly, the number of manufacturing processes can be reduced.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device.

The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit device having a dynamic random access memory and a nonvolatile memory.

[Conventional technology]

A semiconductor integrated circuit device with a built-in microcomputer uses RAM (Ran) as the storage section of the microcomputer.
dom Access Memory) and ROM (R
(ead ONLY Memory). R.A.
An i;t S (Static) RAM is mounted as M, and its memory cells (storage elements) are composed of six MOSFEs.
T (6MO8 configuration). ROMs include mask ROM and EP (rasable programmer).
ammable) ROM or EEP
Cally Danrasabla Programmab
le) ROM is installed. EEPROM
FLOT OX (Floating Gate Engineering)
A memory cell having a (nnel oxide) structure is used.

In the semiconductor integrated circuit device configured in this manner, the memory cells of the SRAM used as RAM are configured in a 6MO8 structure, so the memory cell area increases and the degree of integration decreases. Therefore, instead of SRAM, D (Dynamic) RA is used as RAM for this type of semiconductor integrated circuit device.
There is a proposal to use M. For example, 1 Published by Nikkei McGraw-Hill, Nikkei Microdevices, July 1987 issue, No. 7.
Pages 1 to 73.

The DRAM of this proposed semiconductor integrated circuit device is as follows.

The memory cell is constituted by a series circuit of an MO8FET for memory cell selection and a capacitive element for information storage.

The information storage capacitive element has a so-called planar structure in which an n-type semiconductor region (lower electrode), a dielectric film, and a plate electrode (upper electrode) formed on the main surface of a semiconductor substrate are sequentially laminated.

This semiconductor integrated circuit device has a feature that since the number of DRAM memory cells is small, the memory cell area can be reduced and the degree of integration can be improved.

Further, the semiconductor integrated circuit device may include an EEPROM FL.
Since a DRAM memory cell is formed using a part of the manufacturing process of a memory cell having an OTOX structure, the manufacturing process can be reduced. As described above, this semiconductor integrated circuit device is equipped with a DRAM, an EEPROM, and a MISFET constituting a peripheral circuit, and the manufacturing method of these elements is as follows.

First, a gate insulating film is formed on the main surface of the semiconductor substrate in the floating gate electrode forming region of the EEPROM+7) FLOTOX structure memory cell.

Next, a portion of the gate insulating film is removed, and a tunnel silicon oxide film having a thickness thinner than the gate insulating film is formed.

Next, a floating gate electrode is formed on the gate insulating film and the tunnel silicon oxide film.

Next, a gate insulating film is formed on the floating gate electrode. Using this process, the dielectric film (silicon oxide film) of the information storage capacitor element of the DRAM memory cell and the MISFE of the peripheral circuit are manufactured using the same manufacturing process as that process.
A gate insulating film of T is formed.

Next, a control gate electrode is formed on the floating gate electrode of the FLOTOX memory cell with a gate insulating film interposed therebetween. Utilize this process and use the same manufacturing process as that process.

The plate electrode (upper electrode) and MISF of the peripheral circuit are placed on the dielectric film of the information storage capacitive element of the DRAM memory cell.
A gate electrode is formed on the gate insulating film of the ET.

[Problem to be solved by the invention]

As described above, the dielectric film of the information storage capacitive element is
It is formed by the same manufacturing process as the gate insulating film between the floating gate electrode and the control gate electrode of the FLOTOX structure memory cell and the gate insulating film of the MI S FET in the peripheral circuit. Since a relatively high voltage necessary for writing, reading, and erasing information is applied to the control gate electrode of a FLOTOX-structured memory cell, the gate insulating film under the control gate electrode is formed with a thin film thickness. I can't. Furthermore, since an operating voltage of about 5 [V] is usually applied to the gate electrode of the MISFET in the peripheral circuit, the gate insulating film under the gate electrode cannot be formed with a thin film thickness. Therefore, the dielectric film of the information storage capacitive element, which is formed in the same manufacturing process as the gate insulating film, is formed to have substantially the same thickness as the gate insulating film. Therefore, the amount of charge stored in the information storage capacitor of the DRAM memory cell decreases, and increasing the amount of charge requires an increase in the area occupied by the information storage capacitor. As a result, the area occupied by the RAM increases, and the degree of integration of the semiconductor integrated circuit device decreases.

In addition, in order to increase the amount of charge of the information storage capacitive element of the memory cell of the DRAM, a dielectric film is formed in a separate manufacturing process from the gate insulating film of the FLOTOX structure and the gate insulating film of the MISFET of the peripheral circuit. There is a need to. Therefore, the number of manufacturing steps for semiconductor integrated circuit devices increases in order to improve the degree of integration.

An object of the present invention is to provide a technique that can improve the degree of integration in a semiconductor integrated circuit device equipped with a dynamic memory (DRAM) and a nonvolatile memory.

Another object of the present invention is to provide a technique that can achieve the above object by reducing the area of a dynamic memory element and optimizing the characteristics of a nonvolatile memory element and peripheral circuit elements. It's about doing.

Another object of the present invention is to provide a technique that can reduce the number of manufacturing steps for the semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the attached drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In a method of manufacturing a semiconductor integrated circuit device including a dynamic memory element and a nonvolatile memory element.

The floating gate electrode of the nonvolatile memory element and the upper electrode of the information storage capacitive element of the dynamic memory element or the gate electrode of the memory cell selection MISFET are formed in the same manufacturing process, and the control gate of the nonvolatile memory element is formed in the same manufacturing process. The electrode and the gate electrode of the memory cell selection MISFET of the dynamic storage element or the upper electrode of the information storage capacitor are formed in the same manufacturing process.

[Function] According to the above-described means, the floating gate electrode and the control gate electrode of the nonvolatile memory element are formed in the step of forming the upper electrode of the information storage capacitive element and the gate electrode of the memory cell selection MISFET. Therefore, the manufacturing process of the semiconductor integrated circuit device can be reduced by the amount corresponding to the process of forming the floating gate electrode and the control gate electrode.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the present invention will be described below along with an embodiment in which the present invention is applied to a semiconductor integrated circuit device incorporating a microcomputer.

In addition, in all the figures for explaining an example.

Components having the same function are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiments of the invention]

(Embodiment) A semiconductor integrated circuit device incorporating a microcomputer, which is Embodiment 2 of the present invention, is shown in FIGS. 1A and 1B (cross-sectional views of essential parts showing each element).

As shown in FIGS. 1A and 1B, five semiconductor integrated circuit devices are composed of one common f-type semiconductor substrate 1 made of single crystal silicon. That is, although the semiconductor substrate 1 is shown separately in FIG. 1A and FIG. 1B for drawing purposes, it is actually constructed as one piece.

On the main surface of the semiconductor substrate 1, as shown in FIG.
A storage element is configured. The RAM is composed of a DRAM, and its memory cell (dynamic memory element) DM is described. ROM is EEPROM, E
PROM and? Consists of X-ROM) J, EEP
ROM (7) FL0TOX structure memory cell (nonvolatile memory element) FM and EPROM memory cell (nonvolatile memory element) EM are each described. Mask ROM
The memory cell shown in FIG. 1B is an n-channel MI
Since it has substantially the same structure as the SFET), it is not shown in the drawings and its explanation will be omitted here. Further, on the main surface of the other region of the semiconductor substrate 1, complementary MISFETs (CMO8) constituting five peripheral circuits are constructed as shown in FIG. 1B. CMOS is an n-channel M I S F E
T Q n x, Qn, p channel MISFETQp
It is configured by combining each of t and Qpz. P-channel MISFETQP□.

Each of QPz is an n provided on the main surface of the semiconductor substrate 1.
- is formed on the main surface of the type well region 2.

A semiconductor element formed on the main surface of a semiconductor substrate 1 is electrically isolated from other regions by a field insulating film 3 and a p-type channel stopper region 4.

The semiconductor element formed on the main surface of the well region 2 is electrically isolated from other regions by a field insulating film 3.

Field insulating film 3 is formed of a silicon oxide film in which the main surfaces of semiconductor substrate 1 and well region 2 are selectively oxidized. Channel stopper region 4 is formed on the main surface of semiconductor substrate 1 and below field insulating film 3 .

As shown on the left side of FIG. 1A, the memory cell DM of the DRAM is constituted by a series circuit of a memory cell selection MISFET Qd5 and an information storage capacitive element C.

The information storage capacitive element C includes an n-type semiconductor region (lower electrode)7. Dielectric film 8. It is constructed by sequentially overlapping plate electrodes (upper electrodes) 9. This information storage capacitive element C has a so-called planar structure (MO8 structure).

The semiconductor region 7 is formed on the main surface of the semiconductor substrate 1.

The dielectric film 8 is formed of a silicon oxide film obtained by oxidizing the main surface of the semiconductor region 7 (semiconductor substrate 1). The dielectric film 8 has a film thickness that is substantially the same as that of the tunnel insulating film (silicon oxide film) 8 of the memory cell FM of the EEPROM, which will be described later.
It is formed with a thin film thickness of about 00 [people]. This dielectric film 8. Each of the tunnel insulating films 8 is connected to the MISFETQd5 for memory cell selection and the peripheral circuit MzSFE
T Q n x, Q n z -Q p z.

It is formed with a thinner film thickness than the respective gate insulating films 6 or 12 of Q10. In other words, since the dielectric film 8 of the information storage capacitive element C is formed with a thin film thickness, the structure is configured such that the amount of charge storage of the information storage capacitive element C can be increased and the area of the memory cell DM can be reduced. ing.

Plate electrode 9 is constructed on top of dielectric film 8 .

The plate electrode 9 contains, for example, impurities (P,
It is formed of a polycrystalline silicon film into which As or B) is introduced. The plate electrode 9 has, for example, 3000 to 4000 [λ]
It is formed with a film thickness of approximately This plate electrode 9 is formed of the first layer of gate electrode material in the manufacturing process. A glabellar insulating film 10 is provided on the surface of the plate electrode 9.

The memory cell selection MISFET Qd5 mainly consists of the semiconductor substrate 1, the gate insulation 11i12 . Gate electrode 13° A pair of n-type semiconductor regions 1 serving as a source region and a drain region
5 and a pair of Go-type semiconductor regions 19. In other words, the memory cell selection MISFETQds is composed of an n-channel MISFET.

Semiconductor substrate 1 is used as a channel forming region.

The gate insulating film 12 is formed of a silicon oxide film obtained by oxidizing the main surface of the semiconductor substrate 1. As described above, this gate insulating film 12 is formed to have a thickness that is thicker than the dielectric film 8 of the information storage capacitive element C, for example, about 25 degrees. That is, the gate insulating film 12 has a normal operating range of 1 (for example, the voltage between the semiconductor substrate 1 and the gate electrode 13 is 5
In [vl), semiconductor substrate! The structure is such that a dielectric strength voltage between the gate electrode 13 and the gate electrode 13 can be ensured.

Gate electrode 13 is formed on top of gate insulating film 12 . The gate electrode 13 is formed of, for example, a polycrystalline silicon film into which impurities are introduced to reduce the resistance value. The gate electrode 13 is formed to have a thickness of about 3000 to 4000 [people], for example. The gate electrode 13 is formed of a second layer of gate electrode material in the manufacturing process. In addition, the gate electrode 13 is made of a single layer of a high melting point metal film or a high melting point metal silicide film, or a high melting point metal film or a high melting point metal silicide film provided on a polycrystalline silicon film in order to reduce the resistance value. It may also be formed from a composite membrane. Furthermore, the gate electrode 13 is configured integrally with the word line (WL) 13.

The n-type semiconductor region 15 with a low impurity concentration is provided between the Go-type semiconductor region 19 with a high impurity concentration and the channel formation region. This semiconductor region 15 is a so-called LDD (Li
MISFET with a ghtly aped rain) structure
Configure. The semiconductor region 15 is configured to be self-aligned with the gate electrode 13. The Go-type semiconductor region 19 with a high impurity concentration is self-aligned with the gate electrode 13 with a sidewall spacer 18 interposed therebetween.

One semiconductor region 19 of this memory cell selection MISFET Qd5 is connected to the other semiconductor region 19 of the memory cell selection MISFET Qd5, which is integrally configured (connected) with the semiconductor region 7 which is the lower electrode of the information storage capacitive element C. A wiring 23 is connected through a connection hole 22 formed in the first interlayer insulating film 21 .

Wire 23 is used as a complementary data line (DL).

Arrangement 1A23 is made of aluminum, Si or Cu, for example.
Made of aluminum alloy with added. Si reduces the alloy spike phenomenon. Cu reduces stress migration.

Although not shown, a final passivation film is configured for memory cell selection configured in this manner.

EEFROM (7) /L/FM is a field effect transistor Qf of FLOTOX structure and a MISFET for memory cell selection, as shown in the center of FIG. 1A.
It consists of a series circuit with Qfs. In other words, the memory cell FM has a two-transistor structure.

The field effect transistor Qf is configured to have information "1" or "0". Field effect transistor Qf
mainly includes a semiconductor substrate 1, a semiconductor region 7, a gate insulating film 6. Tunnel insulation film 8. Floating gate electrode9.
Gate insulating film 11. Control gate electrode 13, a pair of n-type semiconductor regions 1 serving as a source region and a drain region
5 and a pair of d-type semiconductor regions 19.

The semiconductor substrate 1 is used as a channel forming region.

The semiconductor region 7 is formed integrally with a semiconductor region 19 used as a drain region, and extends to the main surface of the semiconductor substrate 1 below the tunnel insulating film 8 .

The gate insulating film 6 is formed of a silicon oxide film formed by oxidizing the main surface of the semiconductor substrate 1. The gate insulating film 6 is formed to have a thickness that is thicker than the dielectric film 8 of the information storage capacitive element C, for example, about 500 [layers]. In other words, the gate insulating film 6.

Normal information writing and erasing operation range (for example, the voltage between the semiconductor region 7 and the control gate electrode 13 is 17
~20 [V]), the structure is such that a dielectric breakdown voltage between the semiconductor region 7 and the floating gate electrode 9 can be ensured.

The tunnel insulating film 8 is formed of a silicon oxide film obtained by removing a portion of the gate insulating film 6 under the floating gate electrode 9 and oxidizing the main surface of the semiconductor substrate 1 in the removed portion. Like the dielectric film 8, the tunnel insulating film 8 is formed to have a thin film thickness, for example, about 100 [layers]. In this way, the tunnel insulating film 8 having a thin film thickness can increase the amount of tunnel current per unit area, so that the time required for the information writing operation and erasing operation of the memory cell FM can be shortened.

The floating gate electrode 9 is made of the first layer of gate electrode material similarly to the plate electrode 9 of the information storage capacitive element C.

The gate insulating film 11 is formed of a silicon oxide film in which the surface of the floating gate electrode 9 is oxidized.

The gate insulating film 11 is configured to ensure dielectric strength between the floating gate electrode 9 and the control gate electrode 13 in the range of information writing, reading, and erasing operations. The gate insulating film 11 is, for example, 30
It is formed with a relatively thick film thickness of about 0 to 400 [people].

Control gate electrode 13 is provided on gate insulating film 11 . The control gate electrode 13 is a DRAM
MI 5FETQ for memory cell selection of memory cell DM
Like the gate electrode 13 of ds, it is made of the 2Mth gate electrode material.

This field effect transistor Qf has an LDD structure.

The memory cell selection MISFET Qfs basically includes a semiconductor substrate 1, a gate insulating film 6, a gate electrode wA9, and a pair of n-type semiconductor regions 15 that are a source region and a drain region.
and a pair of n° type semiconductor regions 19.

Each of the gate insulating film 6 and the gate electrode 9 is formed by substantially the same manufacturing process as each of the field effect transistor Qf. MISFETQfs for memory cell selection is LD
It is composed of D structure.

The semiconductor region 19 which is the source region of the memory cell selection MISFET Qfs is formed integrally with the semiconductor region 19 which is the drain region of the field effect transistor Qf.

A shunt wiring 13 is provided on the gate electrode 9 of the memory cell selection MISFET Qfs with an interlayer insulating film 11 interposed therebetween. This shunt wiring 13 is connected to the MISFE for memory cell selection in the direction in which the word line extends.
It is connected to the gate electrode 9 through a connection hole (not shown) formed in the interlayer insulating film 11 every TQfs or every predetermined number. In other words.

The shunt wiring 13 is a MISFET for memory cell selection.
The resistance value of the gate electrode 9 of Qfs and the word line formed integrally therewith can be reduced.

Also, MISFETQfs for memory cell selection.

Like the field effect transistor Qf, it has a two-layer gate structure consisting of a gate electrode 9 and a shunt wiring 13. In this way, when each of the field effect transistor Qf and the memory cell selection MISFET QfS is configured with a two-layer gate structure, the dimension between the two gates can be determined only by the processing dimension, without requiring a mask alignment allowance in the manufacturing process. can do. In other words, the field effect transistor Qf and the memory cell selection M I S F E T Q
f s can be reduced, and the area occupied by the memory cell FM can be reduced.

The wiring 2 is connected to the semiconductor region 19, which is the source region of the field effect transistor Qf of the memory cell FM, through the connection hole 22.
3 is connected. This wiring 23 is a source wiring (SL
) used as A wiring 23 is connected through a connection hole 22 to the semiconductor region 19 which is the drain region of the memory cell selection MISFET Qfs of the memory cell FM. This wiring 23 is used as a data line (DL).

The memory cell EM of the EPROM is composed of a field effect transistor, as shown on the right side of FIG. 1A. The memory cell EM mainly includes a semiconductor substrate 1, a gate insulating film 6.
It is composed of a floating gate electrode 9, a gate insulating film 11, a control gate electrode 13, a pair of n-type semiconductor regions 16 and a pair of go-type semiconductor regions 19, which are source and drain regions.

This memory cell EM has a two-layer gate structure and an LDD structure similarly to the field effect transistor Qf of the memory cell FM of the EEPROM. The low impurity concentration n-type semiconductor region 16 of the field effect transistor which is this memory cell EM is the MISF of the LDD structure.
The impurity concentration is higher than that of the n-type semiconductor region 15 having a low impurity concentration such as ETQds, Qf, and Qfs. In addition, the semiconductor region 1B is connected to other MISFETQds,
n° type semiconductor region 19 with high impurity concentration such as Qf, QfS, etc.
It is composed of a lower impurity concentration compared to . This semiconductor region 16 is configured to increase the electric field strength in the vicinity of the drain region of the field effect transistor to increase the amount of hot carriers generated. In other words, semiconductor region 1
6 is configured to increase the amount of hot electrons generated to be injected into the floating gate electrode 9 of the memory cell EM and shorten the information writing operation time. Further, the semiconductor region 16 is configured to reduce the resistance value of the source region and drain region near the channel forming region, reduce the transfer conductance, and shorten the information read time.

The wiring 2 is connected to the semiconductor region 19 which is the source region of the field effect transistor which is the memory cell EM through the connection hole 22.
3 is connected. Wiring 23 is source wiring (S L)
used as. A wiring 23 is connected to the semiconductor region 19, which is the drain region of the field effect transistor, through a connection hole 22. Wiring 23 is a data line (DL)
used as.

CMO8 of the peripheral circuit, that is, n-channel MIS
F E T Q n L, Qnz, p channel MISF
Each of ET Q P L -Q px is configured as shown in FIG. 1B.

The n-channel M I S F E T Q n□ includes a semiconductor substrate 1, a gate insulating film 6. Gate electrode 9. It is composed of a pair of n-type semiconductor regions 15 and a pair of go-type semiconductor regions 19, which are a source region and a drain region.

The n-channel M I S F E T Q n z includes a semiconductor substrate 1 , a gate insulating film 12 . A pair of n-type semiconductor regions 1 which are a gate electrode 13, a source region and a drain region
5 and a pair of Go-type semiconductor regions 19.

The p-channel MISFET Q'Pt is composed of a well region 2, a gate insulating film 6, a gate electrode 9, a pair of n-type semiconductor regions 17 serving as source and drain regions, and a pair of p-type semiconductor regions 20.

The p-channel M I S F E T Q P z includes a well region 2, a gate insulating film 12, a gate electrode 13, and a pair of n-type semiconductor regions 1 which are a source region and a drain region.
7 and a pair of p' type semiconductor regions 20.

The n-channel MISFETQn, p-channel MIS
Each of the FETs QPI is connected to the gate insulating film 6. of the field effect transistor Qf of the memory cell FM. The gate insulating film 6. is formed by the same manufacturing process as the floating gate electrode 9. Each gate electrode 9 is formed. In other words,
n-channel MI 5FETQn, p-channel MISF
In each of the ETQPts, a gate electrode 9 is formed of the first layer gate electrode material.

On the other hand, the n-channel M I S F E T Q n
z, p channel M I S F E T Q P z
each of the memory cell selection MI of the memory cell DM.
Gate insulating film 12 of SFETQd5. Each of the gate insulating film 12 and the gate electrode 13 is formed by the same manufacturing process as that of the gate electrode 13. That is, the n-channel MISFETQn, p-channel MISFETQ
In each of pz, a gate electrode 13 is formed of the second layer gate electrode material.

Said MISFETQn, , Q n 2. Q p t,
Each of Qp2 has an LDD structure. n-channel M I S F E T Q n L -Q n z
A wiring 23 is connected to each semiconductor region 19 . p-channel MIS FET QPL, Q
A wiring 23 is connected to each semiconductor region 20 of Pz.

In this way, the MISFET of DRAM memory cell DM (dynamic memory element), FLOTOX structure memory cell FM (non-volatile memory element), and peripheral circuit
(Q nxeQ nztQ PztQ pz), the dielectric film 8 of the information storage capacitive element C of the memory cell DM and the memory cell F
The tunnel insulating film 8 of the M field effect transistor Qf is
By configuring the film to be thinner than the gate insulating film 6 or 12 of the MISFET, the information storage capacitive element C
Since the amount of charge storage in the memory cell DM can be improved and the area occupied by the memory cell DM can be reduced, the degree of integration of the DRAM can be improved, and the amount of tunnel current that can flow through the tunnel insulating film 8 can be increased. , it is possible to shorten the information writing time of the memory cell FM of the EEPROM, and it is possible to improve the dielectric strength voltage of the gate insulating film 6 or 12 of the MISFET, so that the electrical reliability can be improved. .

Next, the method for manufacturing the semiconductor integrated circuit device will be briefly explained using FIGS. 2A and 2B to 9A and 9B (cross-sectional views of main parts shown for each manufacturing process). do.

First, a p-type semiconductor substrate 1 made of single crystal silicon is prepared.

Next, P-channel MISFETQ of CMO3 in the peripheral circuit
In the PI and Qpz formation region, an n-type well region 2 is formed on the main surface of the semiconductor substrate 1.

Further, the entire area of the main surface of the semiconductor substrate 1 different from the type 1 well region 2 or the n-channel M of the CMO 8 of the peripheral circuit
A p-type well region may be formed in the ISFET Qn 1 and Qn formation regions.

Next, between the semiconductor element formation regions, the semiconductor substrate 1,
A field insulating film 3 is formed on each main surface of the well region 2 . Field insulating film 3 is formed of a silicon oxide film in which the main surfaces of semiconductor substrate 1 and well region 2 are selectively oxidized. A p-type channel stopper region 4 is formed under the field insulating film 3 on the main surface of the semiconductor substrate 1 by substantially the same manufacturing process as that for forming the field insulating film 3.

Next, as shown in FIGS. 2A and 2B, the semiconductor substrate 1. A gate insulating film 6A is formed on each main surface of the well region 2. This gate insulating film 6A is used as a part of the gate insulating film of a field effect transistor or MISFET. The gate insulating film 6A is formed of a silicon oxide film obtained by oxidizing the main surfaces of the semiconductor substrate 1 and the well region 2, respectively.

Next, as shown in FIGS. 3A and 3B, the information storage capacitive element C forming region and E of the memory cell DM of the DRAM are shown.
Field effect transistor Q of memory cell FM of EPROM
In the f formation region, an n-type semiconductor region 7 is formed on the main surface of the semiconductor substrate 1 in the same manufacturing process. The semiconductor region F forms a lower electrode (one electrode) in the information storage capacitive element C formation region. Further, the semiconductor region 7 is formed in the field effect transistor Qf formation region to allow a tunnel current to flow between the drain region (19) and the floating gate electrode (9). The semiconductor region 7 is formed by introducing an n-type impurity such as As or P into the main surface of the semiconductor substrate 1 through the gate insulating film 6A. The semiconductor region 7 is formed, for example, by introducing As at a concentration of about 101s [atoms/am''1] by ion implantation with an energy of about 60~loO[KeV].When introducing this n-type impurity, a photoresist (not shown) Use the membrane as an introduction mask.

Next, the gate insulating film 6A is selectively removed in the information storage capacitor C forming region of the memory cell DM of the DRAM and the field effect transistor Qf forming region of the memory cell FM of the EEPROM.

Gate insulating film 6A in field effect transistor Qf formation region
A portion under the floating gate electrode (9) formation region is removed.

Next, as shown in FIGS. 4A and 4B, in the region where the gate insulating film 6A has been removed, a dielectric film 8 and a tunnel insulating film are formed on the main surface of the semiconductor substrate 1 (actually, the semiconductor region 7). [8 is formed in the same manufacturing process. The dielectric film 8 is formed on the main surface of the semiconductor region 7 in the information storage capacitive element C formation region. Tunnel insulating film 8 is formed on the main surface of semiconductor region 7 in the field effect transistor Qf formation region. Each of the dielectric film 8 and the tunnel insulating film 8 is formed of a silicon oxide film obtained by oxidizing the main surface of the semiconductor region 7, and is formed to have a thin film thickness as described above. This dielectric film 8 and tunnel insulating film 8
As shown in FIGS. 4A and 4B, the gate insulating film 6A is grown to form the gate insulating film 6. This gate insulating film 6 is a gate insulating film 6
Since the film thickness of the dielectric material 118 or the tunnel insulating film 8 is added to A, the film is formed with a large film thickness as described above.

Next, a first gate electrode layer 9 is deposited over the entire surface of the substrate including the dielectric film 8, the tunnel insulating film 8, the gate insulating film 6, and the like. This first gate electrode layer 9 is made of, for example, C.
It is formed from a polycrystalline silicon film deposited by VD. After the polycrystalline silicon film is deposited, an n-type impurity such as P is introduced (by ion implantation or thermal diffusion) to reduce the resistance value.

Next, the first gate electrode layer 9 is subjected to predetermined patterning, and as shown in FIGS. 5A and 5B, the plate electrode 9. Floating gate electrode 9 and gate electrode 9 are each formed in the same manufacturing process. Plate electrode 9
is the information storage capacitive element C of the DRAM memory cell DM.
It is formed on the dielectric film 8 in the formation region. The floating gate electrode 9 is formed on the tunnel insulating film 8 and the gate insulating film 6 in the field effect transistor Qf forming region of the EEPROM, and on the gate insulating film 6 in the field effect transistor forming region of the EPROM. Each floating gate electrode 9 is patterned only in the gate width direction. The gate electrode 9 is a MISFET Qfs formation region for memory cell selection of the EEPROM, an n channel MISFET Qn of the CMO 8, a formation region, and a p channel M
It is formed on each gate insulating film 6 in the ISFETQPL formation region. Through the step of forming the plate electrode 9, the information storage capacitive element C of the memory cell DM of the DRAM is formed by sequentially overlapping the semiconductor region (lower electrode) 7, dielectric film 8, and plate electrode (upper electrode) 9.
is completed.

Next, an insulating film is formed to cover the plate electrode 9, the floating gate electrode 9, and the gate electrode 9. This insulating film serves as the plate electrode 9. Each surface of floating gate electrode 9 and gate electrode 9 is formed of an oxidized silicon oxide film.

Next, while the insulating film on the plate electrode 9 remains, the insulating film on the floating gate electrode 9 and the gate electrode 9, and the gate in the area where the first gate electrode layer 9 is not formed. Insulating film 6 is selectively removed.

Next, the entire surface of the substrate is oxidized, and as shown in FIGS. 6A and 6B, an interlayer insulating film 1 is formed on the surface of the plate electrode 9.
0. A gate insulating film 11 is formed on the surface of the floating gate electrode 9. An insulating film 11 is formed on the surface of the gate electrode 9. Semiconductor substrate 1
A gate insulating film 12 is formed on the main surface of the well region 2 and on the main surface of the well region 2.
form each. Each of these interlayer insulating film 10, gate insulating film 11, insulating film 11, and gate insulating film 12 is formed by the same manufacturing process. The interlayer insulating film 10 is formed to have a thick film thickness of, for example, about 2000 to 3000 mm. Each of the gate insulating film 11 and the insulating film 11 has a thickness of, for example, 300.
It is formed with a film thickness of about 400 people. The gate insulating film 12 is formed to have a thickness of, for example, about 250 [people]. Note that the interlayer insulating film 10 on the surface of the plate electrode 9 is preferably thicker because it basically insulates the plate electrode 9 and the word line 13 extending in the layer above it, but it is similar to the gate insulating film 11 etc. It may be formed with a thin film thickness to reduce the number of manufacturing steps.

Next, a second gate electrode layer 13 is deposited over the entire surface of the substrate including on the glabella insulating film 10, on the gate insulating film 11, on the insulating film 11, and on the gate insulating film 12. The second gate electrode layer 13 is formed of, for example, a polycrystalline silicon film deposited by CVD. An n-type impurity is introduced into this polycrystalline silicon film similarly to the first gate electrode layer 9.

Next, the EEPROM memory cell FM formation region, EPR
In each of the memory cell EM formation regions of the OM, the second gate electrode layer 13 is patterned for the first time.

While patterning the second gate electrode layer 13, the glabella insulating film 11 is patterned using the same mask. Each of the floating gate electrodes 9 is sequentially patterned (cut in an overlapping manner). By this patterning, E E P
In the memory cell FM formation region of the ROM, the control gate electrode 13 of the field effect transistor Qf and the shunt wiring 1 of the memory cell selection MISFET Qfs
3 can be formed. Furthermore, the control gate electrode 13 of the field effect transistor can be formed in the memory cell EM formation region of the EPROM. The patterning is performed using anisotropic etching such as RIE. In the memory cell FM of the E E P ROM, by forming each of the field effect transistor Qf and the memory cell selection MISFET Qfs with a two-layer gate structure in which the field effect transistor Qf and the memory cell selection MISFET Qfs are overlapped, the dimension between each gate electrode and the mask alignment margin dimension in the manufacturing process can be reduced. Since the dimension between the gate electrodes can be defined by the processing accuracy of the mask, the area occupied by the memory cell FM can be reduced.

Next, the memory cell DM formation region of the DRAM, the n-channel MISFETQn of CMO8, the formation region, and the p-channel M
In each of the ISFETQPz formation regions, the second gate electrode layer 13 is patterned for a second time. By performing this patterning, as shown in FIGS. 7A and 7B, the memory cell selection MISFETQd5. n-channel MISF
ETQn! .

Each gate electrode 13 of the p-channel M I S F E T Q P 2 can be formed. Patterning is performed using anisotropic etching such as RIE.

Next, the entire surface of the substrate is oxidized, and the gate electrode 9.13 is
, an insulating film 14 covering the surfaces of the floating gate electrode 9 and the control gate electrode 13 is formed. Insulating film 14
are the gate insulating films 6 at the ends of the respective gate electrodes 9 and 13,
This is done to increase the thickness of each of the 12 films and improve the dielectric strength.

Next, the memory cell selection M of the memory cell DM of the DRAM is
ISFETQd5 formation region, EEPROM memory cell FM formation region, CMO5 n-channel MISF
In each of the Qn2 formation regions,
An n-type semiconductor region 15 is formed on the main surface of the semiconductor substrate 1 . The semiconductor region 15 is, for example, 10'3 [at.

It can be formed by introducing P of about 1 as/am'' by ion implantation with an energy of about 50 to 80 KeV.

Next, the CMO5 (7) p-channel/L/MISFET
In the Qp Qpz formation region, a p-type semiconductor region 17 is formed on the main surface of the well region 2 . The semiconductor region 17 can be formed by introducing, for example, about 101'' [atoms/an 2] of B by ion implantation with an energy of about 10 to 20 [KaV].

Next, as shown in FIGS. 8A and 8B, the EPROM
In the memory cell EM forming region, an n-type semiconductor layer having a higher impurity concentration than the n-type semiconductor region 15 is formed on the main surface of the semiconductor substrate 1.
A type semiconductor region 16 is formed.

The semiconductor region 16 is configured to increase the electric field strength mainly in the vicinity of the drain region to increase the amount of hot carriers generated. The semiconductor region 16 is, for example, 10'' [
About 60 to 100 [Ke
It can be formed by ion implantation with an energy of about V].

Semiconductor region 15 for forming these LDD structures.
16.17 are respectively connected to the gate electrodes 9.13. Floating gate electrode9. It is formed in self-alignment with one of the control gate electrodes 13. Semiconductor area 1
5, 16, and 17 may be formed in a different order, or may be formed before forming the insulation @14.

Next, each gate electrode 9.13. Floating gate electrode9. Sidewall spacers 18 are formed on each sidewall of control gate electrode 13.

The sidewall spacer 18 can be formed, for example, by subjecting a silicon oxide film deposited by CVD to anisotropic etching such as RIE.

Next, the memory cell selection M of the memory cell DM of the DRAM is
I S F E T Q d s formation region, EEPR
OM memory cell FM formation region, EPROM memory cell EM formation region, 0MO8 n-channel MISFETQ
A Go-shaped semiconductor region 19 is formed on the main surface of the semiconductor substrate 1 in the nQn formation region.

The semiconductor region 19 is, for example, lQ''['atoms/
The semiconductor region 19 can be formed by introducing As of about 1 am by ion implantation with an energy of about 60 to 100 [KeV].
．． 13, the floating gate electrode 9 and the control gate electrode 13 are formed in self-alignment. By this step of forming the semiconductor region 19, the memory cell selection MISFET Qd5 of the memory cell DM, the memory cell FM
Field effect transistor Qf, MIS for memory cell selection
FETQfs, field effect transistor of memory cell EM, and n-channel MISFE TQn1, Qn2 are completed.

Next, as shown in FIGS. 9A and 9B, a p-type semiconductor region 20 is formed on the main surface of the well region 2 in each of the formation regions of the 0MO8 p-channel MISFETs Qp, Qpz. . The semiconductor region 20 is, for example, 10"
[:atoms/a12] B of about 10 to 20[
It can be formed by introducing ion implantation with an energy of about [KeV]. By the process of forming this semiconductor region 20, the p-channel MTSF E T
Each of Q P i and Q P z is completed.

Next, an interlayer insulating film 21 and a contact hole 22 are formed in sequence, as shown in FIGS. 1A and 1B.

Wiring 23 is formed. The interlayer insulating film 21 is made of, for example, BPSG.
It is formed of a single layer of film or PSG film, or a composite film mainly composed of PSG film.

Thereafter, a final passivation film (not shown) is formed over the entire surface of the substrate, thereby completing the semiconductor integrated circuit device of the first embodiment.

In this way, a semiconductor integrated circuit device including a DRAM memory cell (dynamic memory element) DM having an information storage capacitive element C and an EEPROM memory cell (nonvolatile memory element) FM having a tunnel insulating film 8 is manufactured. In the method, the step of forming a dielectric film 8 of the information storage capacitive element C of the memory cell DM;
By performing the process of forming the tunnel insulating film 8 in the same manufacturing process, the tunnel insulating film 8 can be formed in the process of forming the dielectric film 8. The manufacturing process of the semiconductor integrated circuit device can be reduced by a corresponding amount.

Further, a DRAM memory cell DM having an information storage capacitive element C and an E E P R having a tunnel insulating film 8
In a method of manufacturing a semiconductor integrated circuit device including a memory cell FM of an OM, a step of forming a semiconductor region 7 forming a lower electrode of an information storage capacitive element C of the memory cell DM, and a field effect of the memory cell FM are provided. Transistor Qf
The step of forming the semiconductor region F is performed in the same manufacturing process, and then the step of forming the dielectric film 8 of the information storage capacitive element C and the tunnel insulating film 8 of the field effect transistor Qf are performed. By performing the steps in the same manufacturing process, the field effect transistor Qf is formed in the step of forming the semiconductor region 7 and dielectric film 8 of the information storage capacitive element C.
Since the semiconductor region 7 and the tunnel insulating film 8 can be formed, the manufacturing process of the semiconductor integrated circuit device can be reduced by an amount equivalent to the step of forming the semiconductor region 7 and the tunnel insulating film 8.

Further, a DRAM memory cell DM having an information storage capacitive element C and an EE having a floating gate electrode 9 are also included.
In a method of manufacturing a semiconductor integrated circuit device including memory cell FM of FROM (or memory cell EM of EPROM), a step of forming a plate electrode (upper electrode) 9 of an information storage capacitive element C of the memory cell DM; , by performing the step of forming the floating gate electrode 9 of the memory cell FM (and memory cell EM) in the same manufacturing process, the floating gate electrode is formed in the step of forming the plate electrode 9 of the information storage capacitive element C. 9 can be formed, so the floating gate electrode 9
The manufacturing process of the semiconductor integrated circuit device can be reduced by the amount corresponding to the process of forming the semiconductor integrated circuit device.

In addition, a capacitive element C for information storage and M for memory cell selection are also provided.
Manufacture of a semiconductor integrated circuit device equipped with a DRAM memory cell DM having I S F E T Q d s and an EEPROM memory cell FM (or an EPROM memory cell EM) having a floating gate electrode 9 and a control gate electrode 13 In the method, a step of forming a plate electrode (upper electrode) 9 of an information storage capacitive element C of the memory cell DM, and a step of forming a floating gate electrode 9 of the memory cell FM (or memory cell EM).
The process of forming the gate electrode 13 of the memory cell selection MISFET Qd5 of the memory cell DM and the control gate electrode 13 of the memory cell FM (or memory cell EM) are performed in the same manufacturing process. By performing the steps in the same manufacturing process, the floating gate electrode 9 and control gate electrode 9 of the memory cell FM are formed in the step of forming the plate electrode 9 of the information storage capacitive element C and the gate electrode 13 of the memory cell selection MISFET Qd5. can be formed, so
The manufacturing process of the semiconductor integrated circuit device can be reduced by the amount corresponding to the process of forming the floating gate electrode 9 and the control gate electrode 13.

Furthermore, in the method for manufacturing a semiconductor integrated circuit device having a memory cell DM of a DRAM and a memory cell FM of an EEPROM, an information storage capacitive element C of the memory cell DM is provided.
a step of forming each of the semiconductor region 7, the dielectric film 8, the plate electrode 9, and the gate electrode 13 of the memory cell selection MISFETQds; tunnel insulating film 8, floating gate electrode 9,
By performing the process of forming each of the control gate electrodes 13 in the same manufacturing process, the process of forming each of the semiconductor region 7, dielectric film 8, plate electrode 9, and gate electrode 13 of the memory cell DM, Since each of the semiconductor region 7, tunnel insulating film 8, floating gate electrode 9, and control gate electrode 13 of the memory cell FM can be formed, the manufacturing process of the semiconductor integrated circuit device can be further reduced by the corresponding amount. .

(Example ■) In this example ■, in the semiconductor integrated circuit device of the above-mentioned example This is a second embodiment of the present invention in which the gate electrode of the selection MISFET is formed using the first layer gate electrode material.

A semiconductor integrated circuit device incorporating a microcomputer, which is Embodiment 2 of the present invention, is shown in FIG. 10 (a sectional view of the main parts showing each element). Since this embodiment (2) has the same structure as the above embodiment (2) except for the DRAM memory cell, FIG.
Only memory cells FM of M and memory cells EM of EPROM are shown.

As shown in FIG. 10, a DRAM of a semiconductor integrated circuit device
The memory cell DM is a memory cell selection MISFETQ
It is composed of a series circuit of d5 and an information storage capacitive element C.

The information storage capacitive element C of the memory cell DM includes an n-type semiconductor region (lower electrode) 7, a dielectric film 8. Plate electrode (
It has a planar structure in which upper electrodes 13 are stacked one on top of the other. The plate electrode 13 is made of a second layer gate electrode material. The dielectric film 8 is E E P
Field effect transistor Qf of memory cell FM of ROM
Similarly to the tunnel insulating film 8, it is formed with a thin film thickness.

The memory cell selection MISFET Qd5 is connected to the semiconductor substrate 1.
, gate insulating film 6, gate electrode 9. It is composed of a pair of n-type semiconductor regions 15 and a pair of go-type semiconductor regions 19, which are a source region and a drain region. The gate electrode 9 is formed of a first layer gate electrode material.

Next, regarding the manufacturing method of the semiconductor integrated circuit device, FIGS. 11 to 13 (cross-sectional views of main parts shown for each manufacturing process)
Let's briefly explain using.

First, as in Example I, a well region 2 is formed in a semiconductor substrate 1, and then a field insulating film 3 and a p-type channel stopper region 4 are formed in sequence.

Next, in the semiconductor element formation region, the semiconductor substrate 1. A gate insulating film 6A is formed on each main surface of the well region 2.

Next, an n-type semiconductor region 7 is formed on the main surface of the semiconductor substrate 1 in each of the information storage capacitor C forming region of the memory cell DM of the DRAM and the field effect transistor Qf forming region of the memory cell FM of the EEPROM.

Next, in the field effect transistor Qf forming region of the memory cell FM of the EEPROM, a part of the gate insulating film 6A on the semiconductor region 7 is removed, and as shown in FIG. 11, a tunnel insulating film is formed in the removed region. form 8. Through this process of forming the tunnel insulating film 8, the gate insulating film 6A in other regions is grown into the gate insulating film 6.

Unlike the above-mentioned embodiment (■), this embodiment (2) has a tunnel insulating film 8.
The dielectric film 8 of the information storage capacitive element C is formed in a step different from the step of forming the information storage capacitive element C.

Next, a first gate electrode layer 9 is formed over the entire surface of the substrate including on the gate insulating film 6 and the tunnel insulating film 8. Then, the first gate electrode layer 9 is subjected to predetermined patterning, and the gate electrode 9 and floating gate electrode 9 are
form. The gate electrode 9 is connected to the memory cell D of the DRAM.
M memory cell selection MISFET Qd5 formation region, E
MIS for memory cell selection of EPROM memory cell FM
It is formed on each gate insulating film 6 in the FETQfs formation region. Bloating gate electrode 9 is an EEPROM
are formed on the gate insulating film 6 and tunnel insulating film 8 of the field effect transistor Qf of the memory cell FM, and on the gate insulating film 6 of the memory cell EM of the EPROM. Although not shown in the figure, the gate electrode 9 is connected to the CMO3 of the peripheral circuit 1.
It is also formed on the gate insulating film 6 of each of the n-channel MISFET Qnx formation region and the p-channel MISFET QP1 formation region.

Next, the gate electrode 9, the floating gate electrode 9
An insulating film 11A is formed on each surface.

The insulating film 11A is formed of a silicon oxide film in which the surfaces of the gate electrode 9 and the floating gate electrode 9 are each oxidized. Through the process of forming the insulating film 11A, although not shown, the n-channel MISFET Qn of the peripheral circuit and the p-channel MISFET Qn are formed on the main surface of the semiconductor substrate 1 in the formation region.
A gate insulating film used as a part of the gate insulating film (12) is formed on each main surface of the well region 2 in the T Q P 2 forming region.

Next, as shown in FIG. 12, the DRAM memory cell D
The gate insulating film 6 in the region where the information storage capacitive element C of M is formed is selectively removed to expose the main surface of the semiconductor region 7.

Next, a dielectric film 8 is formed on the main surface of the exposed semiconductor region. The dielectric film 8 is formed of, for example, a silicon oxide film formed by oxidizing the main surface of the semiconductor substrate 1. Dielectric film 8
is formed in a separate process from the tunnel insulating film 8, but
Formed with substantially the same thin film thickness. By the step of forming this dielectric film 8, the insulating film 11A is grown,
An insulating film 11. is formed on the surface of the gate electrode 9. A gate insulating film 11 can be formed on the surface of floating gate electrode 9. Also, 1 peripheral circuit 0MO8 n channel M
The gate insulating film 12 can be formed by growing the gate insulating film in each of the I S F E T Q n * formation region and the p-channel MISFET QP2 formation region.

Next, a second gate electrode layer 13 is formed over the entire surface of the substrate, including on the dielectric film 8, on the gate insulating film 11 (and on the gate insulating film 12, not shown), and the like. and.

This second gate electrode layer 13 is patterned twice, and as shown in FIG.
Each of the control gate electrode 13 and the shunt wiring 13 (and the gate electrode 13 of the peripheral circuit) is formed.

After this, as in the summer of the embodiment, the insulating film 14, the semiconductor regions 15, 16, 17 . By sequentially forming the sidewall spacer 18, semiconductor region 19, 20, interlayer insulation film 21, connection hole 22, and wiring 23, this embodiment
The semiconductor integrated circuit device is completed.

A semiconductor integrated circuit device configured in this manner.

In addition to the effects of the embodiment (2), the following effects can be achieved.

DRAM memory cell D having information storage capacitive element C
E E P with M and control gate electrode 13
In a method for manufacturing a semiconductor integrated circuit or device comprising a memory cell FM of a ROM (or a memory cell EM of an EPROM), an information storage capacitive element C of the memory cell DM;
By performing the step of forming the plate electrode (upper electrode) 13 of the memory cell FM (or the control gate electrode 13 of the memory cell EM) in the same manufacturing process, the information storage capacitive element In the process of forming the plate electrode 13 of C, the control gate electrode 1
3 can be formed, the manufacturing process of the semiconductor integrated circuit device can be reduced by an amount corresponding to the process of forming the control gate electrode 13.

In addition, an information storage capacitive element C and a memory cell selection MI
A DRAM memory cell DM having an SFET Qd5 and an EEPROM memory cell FM having a floating gate electrode 9 and a control gate electrode 13 (
or EPROM memory cell EM), in which the memory cell FM
the process of forming the floating gate electrode 9 of the memory cell DM;
A step of forming the gate electrode 9 of the memory cell FM is performed in the same manufacturing process, a step of forming the control gate electrode 13 of the memory cell FM, and a step of forming the plate electrode 13 of the information storage capacitive element C of the memory cell DM. By performing the above in the same manufacturing process, the memory cell selection MISF
Since the floating gate electrode 9 and the control gate electrode 9 of the memory cell FM can be formed in the process of forming the gate electrode 9 of the ETQd5 and the plate electrode 13 of the information storage capacitive element C, the floating gate electrode 9 and the control gate electrode 9 can be formed. The manufacturing process of the semiconductor integrated circuit device can be reduced by an amount corresponding to the process of forming the gate electrode 13.

Furthermore, in the method for manufacturing a semiconductor integrated circuit device having a memory cell DM of a DRAM and a memory cell FM of an EEPROM, an information storage capacitive element C of the memory cell DM is provided.
Semiconductor region 7. Plate electrode 13. A step of forming each of the gate electrodes 9 of the memory cell selection MISFET Qd5, the semiconductor region 7 of the memory cell FM, the control gate electrode 13 . By performing the process of forming each of the floating gate electrodes 9 in the same manufacturing process, the semiconductor region 7, plate electrode 13, and
Since it is possible to form each of the semiconductor region 7, control gate electrode 13, and floating gate electrode 9 of the memory cell FM in the step of forming each of the gate electrodes 9, the amount of time required for forming the semiconductor integrated circuit device is equivalent to that. The manufacturing process can be further reduced.

(Example 2) Example 2 is a third example of the present invention in which the semiconductor element in the semiconductor integrated circuit device of Example I is configured with a single-layer gate structure.

A semiconductor integrated circuit device incorporating a microcomputer, which is Embodiment 2 of the present invention, is shown in FIGS. 14A and 14B (cross-sectional views of essential parts showing each element).

As shown in FIGS. 14A and 14B, the information storage capacitive element C of the memory cell DM of the DRAM has an n-type semiconductor region (lower electrode) 7. Dielectric film 8. It has a planar structure in which plate electrodes (upper electrodes) 9 are stacked one on top of the other. The plate electrode 9 is formed of the first layer of gate electrode material. The dielectric film 8 is formed with a thin film thickness as in the embodiment (2).

M I S F E T Q d s for memory cell selection
is a semiconductor substrate 1. Gate insulating film 6. Gate electrode 9. It is composed of a pair of n-type semiconductor regions 15 and a pair of n-type semiconductor regions 19, which are a source region and a drain region. The gate electrode 9 is formed of a first layer of gate electrode material. In other words, the memory cell DM of the DRAM has a one-layer gate structure.

EEPRoM memory cell) l/FM is shown in Figure 14A.
Although the cross-sectional structure is not shown in FIG. 14B.

As shown in FIG. 17 (plan view of memory cell), a field effect transistor Qf and a memory cell selection MISFET Q
It consists of a series circuit with fs.

The field effect transistor Qf includes a semiconductor substrate 1, an n-type semiconductor region 7, a gate insulating film (first gate insulating film) 6, a tunnel insulating film 8. It is composed of a floating gate electrode 9, a gate insulating film (second gate insulating film) 6, a control gate electrode 7A, a pair of n-type semiconductor regions 15 serving as a source region and a drain region, and a negative pair of di-type semiconductor regions 19. . The floating gate electrode 9 is formed of the first layer of gate electrode material. The floating gate electrode 9 is provided extending in the gate width direction to above the control gate electrode 7A formed of an n-type semiconductor region. A gate insulating film (second gate insulating film) 6 is provided between the floating gate electrode 9 and the control gate electrode 7A. The control gate electrode (semiconductor region) 7A is formed in the same manufacturing process as the semiconductor region 7. The control gate electrode 7A is connected through the connection hole 22 to a wiring [23] used as a word line WL.

M I S F E T Q f s for memory cell selection
As shown in FIG. 17, it is composed of a semiconductor substrate 1, a gate insulating film 6, a gate electrode 9, a pair of n-type semiconductor regions 15 and a pair of n°-type semiconductor regions 19, which are source and drain regions. There is. The gate electrode 9 is made of a first layer of gate electrode material. This gate electrode 9 is constructed integrally with a word line (WL) 9. This memory cell selection MISFET Qfs has substantially the same structure as the memory cell selection MISFET Qd5 of the memory cell DM of the DRAM and the n-channel MISFET Qn of the peripheral circuit. That is, each of the field effect transistor Qf of the memory cell FM of the EEPROM and the memory cell selection MISFET Qfs has a single-layer gate structure.

The memory cell EM of the EPROM has a structure similar to the field effect transistor Qf of the memory cell FM of the EEPR0M. In other words, the memory cell EM includes the semiconductor substrate 1. Gate insulating film (first gate insulating film) 6, floating gate electrode 9, gate insulating film (second gate insulating film) 6, control gate electrode (n-type semiconductor region)
It consists of This memory cell (field effect transistor) EM has a one-layer gate structure.

The n-channel MISFETQn of CMO3 in the peripheral circuit is
A semiconductor substrate 1, a gate insulating film 12, a gate electrode 9, a pair of n-type semiconductor regions 1 serving as a source region and a drain region.
5 and a pair of Go-type semiconductor regions 19. The gate electrode 9 is formed of a first layer gate electrode material.

The p-channel MISFET QP is composed of a well region 2, a gate insulating film 12, a gate electrode 9, a pair of P-type semiconductor regions 17 serving as a source region and a drain region, and a pair of p°-type semiconductor regions 20. The gate electrode 9 is formed of a first layer gate electrode material. In other words, CMO
8 n-channel MISFETQn, p-channel MISF
Each ETQp has a single-layer gate structure.

Next, regarding the manufacturing method of the semiconductor integrated circuit device, FIGS. 15A and 15B and FIGS. 16A and 16B (
This will be briefly explained using sectional views of main parts shown for each manufacturing process.

First, a well region 2 is formed on the main surface of a semiconductor substrate 1 in the same manner as in Example 2, and then a field insulating film 3.
Each of the P-type channel stopper regions 4 is formed.

Next, in the semiconductor element formation region, the semiconductor substrate 1. An insulating film 6A used as a part of the gate insulating film is formed on each main surface of the well region 2.

Next, the n-channel MISFETQ of CMO8 in the peripheral circuit
The insulating film 6A is selectively removed in each of the n-formation region and the p-channel MISFET Qp formation region.

Next, the n-channel MIS with the insulating film 6A removed
In each of the FETQn formation region and the p-channel MISFETQp formation region, a gate insulating film 12 is newly formed on the main surfaces of the semiconductor substrate 1 and the well region 2, respectively. In this step of forming the gate insulating film 12, the insulating film 6A is grown, and the gate insulating film 6 is formed on the main surfaces of the semiconductor substrate 1 and the well region 2, respectively.

Next, as shown in FIGS. 15A and 15B, the DRA
information storage capacitive element C formation region of memory cell DM of M;
In each of the field effect transistor Qf and memory cell selection MISFET Qfs formation region of the memory cell FM of the EEPROM, and the memory cell EM formation region of the EEPROM, an n-type semiconductor region F and a control gate electrode 7A are formed on the main surface of the semiconductor substrate 1. form. Semiconductor area 7
, control gate electrode 7A can be formed by introducing n-type impurities by ion implantation.

Next, the gate insulating film 6 is selectively removed in each of the formation region of the information storage capacitive element C of the memory cell DM of the DRAM and the formation region of the field effect transistor Qf of the memory cell FM of the EEPROM.

Then, a dielectric film 8 and a tunnel insulating film 8 are formed on the main surface of the removed semiconductor substrate 1, respectively.

Next, a first gate electrode layer 9 is formed over the entire surface of the substrate including on the gate insulating films 6 and 12, on the dielectric film 8, and on the tunnel insulating film 8. Thereafter, by performing predetermined patterning on the first gate electrode layer 9, the 16th
As shown in FIG. A and FIG. 16B, each of the plate electrode 9, gate electrode 9, and floating gate electrode 9 can be formed. The plate electrode 9 forms the upper electrode of the information storage capacitive element C of the memory cell DM of the DRAM. The gate electrode 9 forms the gate electrodes of the memory cell selection MISFET Qds of the memory cell DM, the memory cell selection MISFET Qfs of the memory cell FM of the EEPROM, and the MISFETs Qn and Qp of the peripheral circuit CMO3. The floating gate electrode 9 is connected to the field effect transistor Qf, EPRO of the memory cell FM.
Each floating gate electrode of M memory cells EM is formed.

Next, in the same manner as in Example (2), semiconductor regions 15°, 16.
17, sidewall spacer 18, semiconductor region 19.
201 interlayer insulating film 21, connection hole 22. By sequentially forming each of the wirings 23,
As shown in FIG. B, the semiconductor integrated circuit device is completed.

The semiconductor integrated circuit device configured in this manner can provide the following effects in addition to the effects of the embodiment (2).

In a method for manufacturing a semiconductor integrated circuit device including a memory cell DM of a DRAM and a memory cell FM of an EEPROM (and a memory cell EM of an EPROM), an n-type semiconductor region (lower part) of an information storage capacitive element C of the memory cell DM is provided. (electrode) 7 and the step of forming the n of the memory cell FM.
By performing the steps of forming the type semiconductor region 7 and the control gate electrode (n-type semiconductor region) 7A in the same manufacturing process, the memory cell FM is Since the semiconductor region 7 and the control gate electrode 7A can be formed, the manufacturing process of the semiconductor integrated circuit bag can be reduced by the amount corresponding to the process of forming the semiconductor region 7 and the control gate electrode 7A.

In addition, the memory cell DM of DRAM and the memory cell FM of EEPROM (or the memory cell EM of EPROM)
In the method of manufacturing a semiconductor integrated circuit device, the plate electrode (upper electrode) 9 of the information storage capacitive element C of the memory cell DM and the memory cell selection MISF
a step of forming a gate electrode 9 of E T Q d s;
By performing the step of forming the floating gate electrode 9 of the field effect transistor Qf of the memory cell FM in the same manufacturing process, the plate electrode 9 of the information storage capacitive element C and the memory cell selection M I S F E
Since the floating gate electrode 9 of the memory cell FM can be formed in the process of forming the gate electrode 9 of TQds, the process of forming the bloating gate electrode 9 is equivalent to the process of forming the semiconductor integrated circuit device. Manufacturing steps can be reduced.

Furthermore, since the semiconductor integrated circuit device has a single-layer gate structure, the number of conductive layers is small, and the manufacturing process of the semiconductor integrated circuit device can be simplified. .

(Embodiment 2) Embodiment 2 is a fourth embodiment of the present invention in which, in the semiconductor integrated circuit device of Embodiment I, the information storage capacitor of the DRAM memory cell is configured in a stacked structure.

A semiconductor integrated circuit device incorporating a microcomputer, which is Embodiment 2 of the present invention, is shown in FIG. 18 (a cross-sectional view of essential parts showing each element).

As shown in FIG. 18, the memory cell DM of the DRAM is
It is constituted by a series circuit of a memory cell selection MISFET Qd5 and a stacked information storage capacitive element C.

The memory cell selection MISFET Qd5 is the same as in the above embodiment
Similarly, the gate electrode 9 is made of the first layer gate electrode material.

The information storage capacitive element C has a plate electrode (lower electrode) 1
3. It is constructed by sequentially overlapping the dielectric film 2B and the plate electrode 27, respectively. The plate electrode 13 is connected to the semiconductor region 19 of the memory cell selection MISFET Qd5 on the side not connected to the data line 23. This connection is made through a connection hole 25 formed in the interlayer insulation film 24.
Moreover, it is defined by the side wall spacer 18. The plate electrode 13 is made of a second J5 gate electrode material, for example, a polycrystalline silicon film. The dielectric film 26 is formed of a single layer of a silicon oxide film, a silicon nitride film, a tantalum oxide film, or a composite film thereof, which is formed by an insulating film forming method such as CVD or sputtering. The plate electrode 27 is formed of a third layer of gate electrode material, for example, a polycrystalline silicon film. the second layer gate electrode material, the third layer gate electrode material,
Although not shown, each of the electrode materials is used as a wiring or a resistance element in other areas.

Each of the EEPROM memory cell FM, the EPROM memory cell EM, and the peripheral circuit CMO8 (not shown) is
Similar to the embodiment (2), it has a single-layer gate structure.

Although the manufacturing method of the semiconductor integrated circuit device of this embodiment is omitted, basically, a semiconductor element with a single-layer gate structure, such as a memory cell selection MISFET Qds of a DRAM memory cell DM, is used. After forming the memory cell DM
An information storage capacitive element C is formed.

The semiconductor integrated circuit device configured in this manner can achieve the same effects as those of the embodiment (2).

Although the invention made by the present inventor has been specifically explained based on the above embodiments, the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, in the present invention, the memory cell of the EEPROM may be configured with a one-transistor structure (only one field-effect transistor Qf).

In addition, one aspect of the present invention is that the memory cells of the EEPROM are M N
OS (Metal N1tride Oxide S
It may be configured with a field effect transistor having an em1conductor structure.

〔Effect of the invention〕

Among the inventions disclosed in this application, the effects that can be obtained by typical ones are as follows.

In a semiconductor integrated circuit device including a dynamic memory element and a nonvolatile memory element, the number of manufacturing steps can be reduced.

[Brief explanation of the drawing]

1A and 1B are cross-sectional views of main parts of a semiconductor integrated circuit device incorporating a microcomputer, which is an embodiment (1) of the present invention, and FIGS. 2A and 2B to 9A and FIG. 9B is a cross-sectional view of essential parts shown in each manufacturing process of the semiconductor integrated circuit device. FIG. 10 is a sectional view of main parts of a semiconductor integrated circuit device incorporating a microcomputer, which is Embodiment ① of the present invention, and FIGS. 11 to 13 are main parts shown for each manufacturing process of the semiconductor integrated circuit device. 14A and 14B are sectional views of main parts of a semiconductor integrated circuit device incorporating a microcomputer, which is Embodiment 2 of the present invention. Figure 15A and Figure 15B and Figure 16A and Figure 16B
17 is a plan view showing a memory cell of an EEPROM of the semiconductor integrated circuit device, and FIG. 18 is an embodiment of the present invention. 3 is a cross-sectional view of a main part of a semiconductor integrated circuit device incorporating a microcomputer; FIG. In the figure, DM, FM, EM--memory cells, Qds. Qfs...MISFET for memory cell selection, C...
Capacitive element for information storage, Qf...field effect transistor, Qn, Qp-MISFET, 6, 11.12-...
Gate insulating film, 7, 15.16.17.19.20・
... Semiconductor region, 8... Dielectric film, tunnel insulating film,
9...Gate electrode. Plate electrode, floating gate electrode, 13...
These are a gate electrode and a control gate electrode.

Claims (1)

[Claims] 1. Information storage capacitive element and memory cell selection MISF in which an upper electrode is formed with a dielectric film interposed on the lower electrode
In a method for manufacturing a semiconductor integrated circuit device including a dynamic memory element having an ET and a nonvolatile memory element having a floating gate electrode and a control gate electrode, the step of forming a floating gate electrode of the nonvolatile memory element; forming a control gate electrode of the non-volatile memory element by performing a step of forming an upper electrode of the information storage capacitive element of the dynamic memory element or a gate electrode of the memory cell selection MISFET in the same manufacturing process; A method of manufacturing a semiconductor integrated circuit device, characterized in that the step of forming the gate electrode of the memory cell selection MISFET of the dynamic storage element or the upper electrode of the information storage capacitor element is performed in the same manufacturing process. 2. Claims characterized in that each of the upper electrode of the information storage capacitive element, the gate electrode of the memory cell selection MISFET, and the floating gate electrode of the nonvolatile memory element is formed of a polycrystalline silicon film. 2. A method for manufacturing a semiconductor integrated circuit device according to item 1. 3. The gate electrode of the memory cell selection MISFET, the upper electrode of the information storage capacitor, and the control gate electrode of the nonvolatile memory element are each made of a polycrystalline silicon film, a high melting point metal silicide film, or a high melting point metal film. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is formed of a single layer or a composite film thereof. 4. The nonvolatile memory element is an electrically erasable FLOT
4. A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device has an OX structure or an ultraviolet erasable type.